717results about "Synchronisation signal speed/phase control" patented technology

In one embodiment, a system includes a digitally controlled oscillator (DCO) to generate a local clock having a local clock frequency, and clock synchronization circuitry to receive from a device a signal indicative of a remote clock frequency, compare measures of the remote clock frequency and the local clock frequency; generate a digital control command based on the comparison; and provide the digital control command to the DCO, wherein the DCO is to adjust the local clock frequency responsively to the digital control command.

The invention relates to an ultra-low power consumption multichannel high-speed signal synchronous acquisition and emission system suitable for satellite communication. The system comprises an acquisition and emission board card which mainly comprises a plurality of radio frequency transceivers, an optical module, a clock unit, an FPGA (Field Programmable Gate Array) 1 processor and the like; the clock unit comprises a clock chip, a clock Buffer and the like; the optical module is used for receiving data, sending the data to an FPGA (Field Programmable Gate Array) 1 for processing, then sending the data to a transmitting channel of the radio frequency transceiver through a JESD204B interface for interpolation filtering, QEC (Quadrature Error Correction) calibration and refreshing, and then performing up-conversion to output an I / Q analog modulation signal; a receiving channel of the radio frequency transceiver receives an I / Q analog signal, the I / Q analog signal is sampled after low-pass filtering, the sampled data is sent to the FPGA1 for processing through the JESD204B interface after QEC calibration, and then the data is forwarded through the optical module. The system can realize ultra-low power consumption and reduce the weight of the whole machine.

The invention provides a timing synchronization recovery system based on a Gardner algorithm, relates to the technical field of signal processing, and is used for solving the problem that in the prior art, in long-distance communication, due to the fact that signals are affected by noise and errors caused by factors such as atmospheric turbulence and Doppler effect in the transmission process, the transmission efficiency of the signals is improved. And complete synchronization of the clock, the phase and the frequency is difficult to guarantee. The system comprises a signal sending end used for generating a random binary signal and modulating the binary signal into a simulation signal suitable for transmission, and the simulation signal is used for simulating transmitted bit data; the channel is used for transmitting the simulation signal and introducing noise in the transmission process to carry out simulation interference on the simulation signal to obtain a distortion signal; and the signal receiving end is used for receiving the distorted signal, performing timing synchronization and interpolation processing on a symbol of the distorted signal by using a Gardner loop, correcting a sampling deviation introduced by a channel, and recovering original bit data from the distorted signal.

A receiving device, comprising: a clock generator circuit configured to generate a base clock signal; a counter configured to count cycles or edges of the base clock signal while a measurement pulse is received over a one-wire serial bus during a first transaction conducted over the one-wire serial bus, the measurement pulse having a pulse duration defined by a number of clock cycles of a transmitter clock signal; and a controller configured to adjust a count value of the counter when the counter is timing actuation of a trigger using a correction value that represents a difference between the cycles or edges of the base clock signal counted while the measurement pulse was being received and the number of clock cycles of the transmitter clock signal that defines the pulse duration.

The present application provides a chip communication circuit, method and apparatus based on automatic clock synchronization. The method includes: determining clock synchronization information of a first battery management chip in response to a received control instruction; replacing a chip selection enable signal in the control instruction with a clock synchronization signal carrying the clock synchronization information of the first battery management chip to obtain a new control instruction; and transmitting the new control instruction to other battery management chips, so that the other battery management chips perform automatic clock synchronization based on the clock synchronization information carried in the new control instruction; where the other battery management chips are battery management chips among the multiple battery management chips except for the first battery management chip, and a daisy chain with a sinusoidal sawtooth waveform is used for isolated communication between different battery management chips.

The invention relates to the technical field of radio frequency signal processing, and discloses a self-adaptive digital phase calibration method and device, a radio frequency system-on-chip board card, a multi-channel radio frequency receiving system and electronic equipment. Comprising the following steps: under the condition that a synchronous acquisition instruction is received, synchronously acquiring radio frequency signals of each antenna channel at the same moment by using a signal acquisition unit; performing digital domain signal processing on the radio frequency signal by using a digital processing unit to obtain respective baseband signal data of each antenna channel; performing phase calculation on the baseband signal data, and determining respective relative phase data of each antenna channel; and dynamically configuring a digitally controlled oscillator corresponding to each antenna channel based on the relative phase data so as to perform adaptive phase calibration on each antenna channel. The phase difference between the channels can be dynamically corrected without depending on additional hardware devices such as a phase shifter or a delayer, the application requirement of a large-scale multi-channel radio frequency receiving system is met, and the phase synchronization requirement between the channels is effectively met.

A disclosed method is performed by a primary device that is configured to code data using forward error correction (FEC) coding for transmission to a secondary device. The FEC coding adds a FEC marker to FEC coded data. The method by the primary device includes transmitting to the secondary device a marker planned transmission time indication which indicates when the primary device will transmit the FEC marker toward the secondary device. The method also includes transmitting the FEC marker of the FEC coded data at the time indicated by the marker planned transmission time indication.

An interface device distributes data from a plurality of input data streams to a smaller number first data streams, and periodically inserts a set of alignment markers (AMs) into the first data streams. After using the AMs, the interface device removes the AMs and reinserts the AMs at particular positions. A forward error correction (FEC) encoder encodes data corresponding to the first data stream to generate FEC codewords and distributes data from the FEC codewords to multiple outputs streams. Within the output streams, the AMs are located at FEC codeword boundaries and bits of a first AM, among the set of AMs, are spread across multiple outputs stream. A single output data stream is generated based on the multiple output streams of the FEC encoder.

The invention discloses a synchronous demodulation method for a passive RFID tag, and the method comprises the following steps: carrying out the DC removal and smooth filtering operation of an input signal, and outputting a preprocessing signal; according to the signal peak value distribution, roughly estimating a backscattering link frequency deviation condition of a label signal in the preprocessed signal, and calculating and outputting a roughly estimated oversampling rate; calculating a correlation coefficient between the preprocessed signal and a standard lead code under different oversampling rates, and preliminarily judging a possible position of the lead code in the tag signal; and comparing calculation results of the correlation coefficients under different oversampling rates, judging and outputting an oversampling rate precise estimation value, and completing synchronous detection of the lead code. According to the fine estimation value of the oversampling rate, a corresponding local 0 / 1 bit sequence is used, the preprocessed signal is judged to be 0 / 1 bit output through correlation operation, and demodulation of the input signal is completed. According to the invention, through a mode of first rough estimation and then fine estimation, consumption of hardware computing resources is reduced, and reduction of communication performance is avoided.

Fast sampling phase and frequency acquisition suitable for incorporation into various high bandwidth receivers and receiving methods. One illustrative integrated circuit receiver or “deserializer” design has: a clock circuit that provides a sample clock; an analog to digital converter that samples a receive signal in accordance with the sample clock to provide receive signal samples; and a clock recovery circuit. The clock recovery circuit includes: a phase and frequency acquisition module to determine and correct an initial frequency offset and an initial phase offset of the sample clock; and a feedback circuit to minimize timing error of the sample clock after the initial frequency offset and initial phase offset have been corrected.

In one embodiment, a system includes a digitally controlled oscillator (DCO) to generate a local clock having a local clock frequency, and clock synchronization circuitry to receive from a device a signal indicative of a remote clock frequency, compare measures of the remote clock frequency and the local clock frequency; generate a digital control command based on the comparison; and provide the digital control command to the DCO, wherein the DCO is to adjust the local clock frequency responsively to the digital control command.

A communication system for performing communication between devices includes: a master device configured to transmit a clock and data through one serial line; and a slave device configured to receive the clock and the data from the master device through the one serial line. The slave device may be configured to receive the clock, search for a reception start point based on a frame block representing a start of the data, and set or change an operation mode based on a sequence of a second frame block subsequent to the frame block.

Techniques, methods and system, for synchronization of sparse data signals are disclosed, comprising mixing a serial stream of sparse data signals with a serial stream of synchronization signals, to thereby add redundancy to the serial stream of sparse data signals and enable clock regeneration from a serial stream of mixed signals produced by said mixing, emulating the serial stream of synchronization signals by applying the clock regeneration to the serial stream of mixed signals, and generating a stream of parallel synchronization signals having a frequency of the serial stream of synchronization signals, deserializing the serial stream of mixed signals into a stream of parallel mixed signals having a data rate lower than a data rate of the serial signal streams, and demixing the stream of parallel synchronization signals with the stream of parallel mixed signals and thereby removing the redundancy introduced by the mixing into the sparse data signals and generating a parallel stream of demixed signals substantially synchronized with said synchronization signals.

Communication systems and methods in accordance with various embodiments of the invention utilize modulation on zeros. Carrier frequency offsets (CFO) can result in an unknown rotation of all zeros of a received signal's z-transform. Therefore, a binary MOCZ scheme (BMOCZ) can be utilized in which the modulated binary data is encoded using a cycling register code (e.g. CPC or ACPC), enabling receivers to determine cyclic shifts in the BMOCZ symbol remitting from a CFO. Receivers in accordance with several embodiments of the invention include decoders capable of decoding information bits from received discrete-time baseband signals by: estimating a timing offset for the received signal; determining a plurality of zeros of a z-transform of the received symbol; identifying zeros from the plurality of zeros that encode received bits by correcting fractional rotations resulting from the CFO; and decoding information bits based upon the received bits using a cycling register code.

This application provides example communication methods and devices. One example method is applied to a receiving device, and the method includes receiving a first data frame, where the first data frame includes a plurality of pieces of synchronization information, and the plurality of pieces of synchronization information are all used for frame synchronization. Frame synchronization is performed on the first data frame based on one or more of the plurality of pieces of synchronization information.

Fast sampling phase and frequency acquisition suitable for incorporation into various high bandwidth receivers and receiving methods. One illustrative integrated circuit receiver or “deserializer” design has: a clock circuit that provides a sample clock; an analog to digital converter that samples a receive signal in accordance with the sample clock to provide receive signal samples; and a clock recovery circuit. The clock recovery circuit includes: a phase and frequency acquisition module to determine and correct an initial frequency offset and an initial phase offset of the sample clock; and a feedback circuit to minimize timing error of the sample clock after the initial frequency offset and initial phase offset have been corrected.

To provide a sequence pattern generating device which enables a user to arbitrarily set output to be restarted synchronously with the restart of a sequence.SOLUTION: A sequence pattern generating device includes a synchronous setting screen 301 having a primary module selection button 311 and a secondary module selection button 312 for selecting a module to be synchronized, and synchronous selection buttons 313, 314, 315, and 316 provided for each output of the selected module and for selecting whether or not to synchronize when restarting a sequence.SELECTED DRAWING: Figure 5

The embodiments of the present application provide a method, device and system for sending precision information. The method includes: a first network element switches from a tracking state to a holding state; the first network element sends status information to a second network element, and the status information includes the precision information of the first network element in the holding state. Through the above method, the second network element can obtain the status information of the first network element in the holding state, and perform clock synchronization with the first network element or with the second network element according to the status information, ultimately achieving more accurate clock synchronization and further improving the performance of the clock synchronization system.

Some embodiments relate to a communication network comprising at least one receiver system optically coupled to a plurality of transmitter systems for transmission of synchronization signals generated by the at least one receiver system to the plurality of transmitter systems over a unidirectional synchronization channel. The at least one receiver system configured to embed into the synchronization signals thereby generated additional data indicative of an internal time count thereof for synchronization of transmission of data / signals from each one of the plurality of transmitter systems to said at least one receiver system over a sparse data / signals unidirectional communication channel.

To provide a communication device, a communication system, and a communication method that can accommodate baud rate fluctuations with a relatively simple configuration.SOLUTION: A communication device includes a measurement unit that measures the duration of a known signal level using communication data transmitted from an opposing device, in which one or more predetermined bits are set to a known signal level, and an adjustment unit that adjusts the time per bit in asynchronous serial communication with the opposing device on the basis of the duration and the number of the one or more bits.SELECTED DRAWING: Figure 4

This disclosure generally relate to a method and system for mapping application dependency information. The present technology relates techniques that enable user-adjustable application dependency mapping of a network system. By collecting internal network data using various sensors in conjunction with external user inputs, the present technology can provide optimized application dependency mapping using user inputs.

In-band communication methods and transceivers are provided to enable protocol-agnostic management channel. One illustrative in-band communications method includes: buffering an outbound data stream from a host-side receiver with a data stream buffer, the outbound data stream having a first bit rate; and providing a line-side data stream representing the outbound data stream with an additional word after every N words of the outbound data stream, the line-side data stream having a second bit rate derived from a fill level of the data stream buffer, the additional words including message words and idle words with adjacent message words potentially separated by a predetermined number of idle words.

The invention relates to the resetting of a receiver timer of a receiver for correlating receiver time information with a time generated by a transmitter timer of a transmitter, wherein the receiver is designed to receive radio messages transmitted to it by the transmitter. During this resetting, a first message from the transmitter is received by the receiver, wherein the reception comprises a radio time period during which the receiver's radio is active. Information is determined from which the start time or end time of the radio time period can be determined. The receiver timer is then reset according to the determined information. The method is flexible and can be used in particular for so-called "sleepy devices" or receivers that are temporarily in a sleep state.

A clock synchronization method is disclosed. The method comprises receiving master timing synchronization data from a master clock device, wherein the master timing synchronization data is based at least in part on quantum data obtained from a first quantum device of the master clock device. The method comprises determining local timing synchronization data that is based at least in part on local quantum data obtained from a second local quantum device, wherein the second local quantum device is entangled with the first quantum device such that the local quantum data and the quantum data obtained from the first quantum device are identical at a same time. The method comprises using the determined local timing synchronization data and the received master timing synchronization data to determine a timing correction factor. The method comprises correcting a local system time using the timing correction factor.

Systems and methods for reducing a number of comparators used during an alignment marker (AM) search are presented. A method includes enabling communication between a physical coding sublayer (PCS) having a PCS transmit side and a PCS receive side with a physical medium attachment (PMA) sublayer, at a first end, using multiple PCS lanes that receives data blocks from the multiple PCS lanes, wherein a PCS lane includes an alignment marker (AM) on the PCS transmit side and performs an AM search using a first AM search stage circuit, wherein, in the first AM search stage circuit, all of the multiple PCS lanes are consecutively searched with read components on the PCS receive side until an AM is detected in all of the multiple PCS lanes.

A communication system comprising a light source associated with a first item of interest; a visible light communications system operably coupled to the light source of the first item of interest, the visible light communications system configured to process information as an encoded signal and output the encoded signal via the light source; and a receiver associated with a second item of interest, the receiver configured to receive the encoded signal from the light source and process the encoded signal to obtain the information.

The present disclosure proposes a method for sending a cell stream, an apparatus for sending a cell stream, a network device, and a computer-readable storage medium. The method includes: detecting a time deviation value between an actual time of sending a cell in a designated device and a reference time; calculating a total number of code blocks corresponding to the time deviation value; and controlling the designated device to insert code blocks of a preset type into the cell stream to be sent according to the calculated number of code blocks, so as to adjust the actual time of sending the cell in the designated device to the reference time.

Transceiver array synchronization by receiving a clock signal and at least one synchronization pulse signal at each transceiver IC of a plurality of transceiver integrated circuit (IC) subarrays, wherein each transceiver IC subarray contains a respective set of serially connected transceiver ICs; and synchronizing the transceiver IC with other transceiver ICs of the respective set of serially connected transceiver ICs by resetting a delta-sigma modulator (DSM) circuit to a predetermined state in accordance with the received at least one synchronization pulse signal.