574results about "Synchronisation signal speed/phase control" patented technology

The invention relates to an ultra-low power consumption multichannel high-speed signal synchronous acquisition and emission system suitable for satellite communication. The system comprises an acquisition and emission board card which mainly comprises a plurality of radio frequency transceivers, an optical module, a clock unit, an FPGA (Field Programmable Gate Array) 1 processor and the like; the clock unit comprises a clock chip, a clock Buffer and the like; the optical module is used for receiving data, sending the data to an FPGA (Field Programmable Gate Array) 1 for processing, then sending the data to a transmitting channel of the radio frequency transceiver through a JESD204B interface for interpolation filtering, QEC (Quadrature Error Correction) calibration and refreshing, and then performing up-conversion to output an I / Q analog modulation signal; a receiving channel of the radio frequency transceiver receives an I / Q analog signal, the I / Q analog signal is sampled after low-pass filtering, the sampled data is sent to the FPGA1 for processing through the JESD204B interface after QEC calibration, and then the data is forwarded through the optical module. The system can realize ultra-low power consumption and reduce the weight of the whole machine.

The invention relates to the technical field of radio frequency signal processing, and discloses a self-adaptive digital phase calibration method and device, a radio frequency system-on-chip board card, a multi-channel radio frequency receiving system and electronic equipment. Comprising the following steps: under the condition that a synchronous acquisition instruction is received, synchronously acquiring radio frequency signals of each antenna channel at the same moment by using a signal acquisition unit; performing digital domain signal processing on the radio frequency signal by using a digital processing unit to obtain respective baseband signal data of each antenna channel; performing phase calculation on the baseband signal data, and determining respective relative phase data of each antenna channel; and dynamically configuring a digitally controlled oscillator corresponding to each antenna channel based on the relative phase data so as to perform adaptive phase calibration on each antenna channel. The phase difference between the channels can be dynamically corrected without depending on additional hardware devices such as a phase shifter or a delayer, the application requirement of a large-scale multi-channel radio frequency receiving system is met, and the phase synchronization requirement between the channels is effectively met.

The invention discloses a synchronous demodulation method for a passive RFID tag, and the method comprises the following steps: carrying out the DC removal and smooth filtering operation of an input signal, and outputting a preprocessing signal; according to the signal peak value distribution, roughly estimating a backscattering link frequency deviation condition of a label signal in the preprocessed signal, and calculating and outputting a roughly estimated oversampling rate; calculating a correlation coefficient between the preprocessed signal and a standard lead code under different oversampling rates, and preliminarily judging a possible position of the lead code in the tag signal; and comparing calculation results of the correlation coefficients under different oversampling rates, judging and outputting an oversampling rate precise estimation value, and completing synchronous detection of the lead code. According to the fine estimation value of the oversampling rate, a corresponding local 0 / 1 bit sequence is used, the preprocessed signal is judged to be 0 / 1 bit output through correlation operation, and demodulation of the input signal is completed. According to the invention, through a mode of first rough estimation and then fine estimation, consumption of hardware computing resources is reduced, and reduction of communication performance is avoided.

In one embodiment, a system includes a digitally controlled oscillator (DCO) to generate a local clock having a local clock frequency, and clock synchronization circuitry to receive from a device a signal indicative of a remote clock frequency, compare measures of the remote clock frequency and the local clock frequency; generate a digital control command based on the comparison; and provide the digital control command to the DCO, wherein the DCO is to adjust the local clock frequency responsively to the digital control command.

Techniques, methods and system, for synchronization of sparse data signals are disclosed, comprising mixing a serial stream of sparse data signals with a serial stream of synchronization signals, to thereby add redundancy to the serial stream of sparse data signals and enable clock regeneration from a serial stream of mixed signals produced by said mixing, emulating the serial stream of synchronization signals by applying the clock regeneration to the serial stream of mixed signals, and generating a stream of parallel synchronization signals having a frequency of the serial stream of synchronization signals, deserializing the serial stream of mixed signals into a stream of parallel mixed signals having a data rate lower than a data rate of the serial signal streams, and demixing the stream of parallel synchronization signals with the stream of parallel mixed signals and thereby removing the redundancy introduced by the mixing into the sparse data signals and generating a parallel stream of demixed signals substantially synchronized with said synchronization signals.

This application provides example communication methods and devices. One example method is applied to a receiving device, and the method includes receiving a first data frame, where the first data frame includes a plurality of pieces of synchronization information, and the plurality of pieces of synchronization information are all used for frame synchronization. Frame synchronization is performed on the first data frame based on one or more of the plurality of pieces of synchronization information.

To provide a sequence pattern generating device which enables a user to arbitrarily set output to be restarted synchronously with the restart of a sequence.SOLUTION: A sequence pattern generating device includes a synchronous setting screen 301 having a primary module selection button 311 and a secondary module selection button 312 for selecting a module to be synchronized, and synchronous selection buttons 313, 314, 315, and 316 provided for each output of the selected module and for selecting whether or not to synchronize when restarting a sequence.SELECTED DRAWING: Figure 5

Some embodiments relate to a communication network comprising at least one receiver system optically coupled to a plurality of transmitter systems for transmission of synchronization signals generated by the at least one receiver system to the plurality of transmitter systems over a unidirectional synchronization channel. The at least one receiver system configured to embed into the synchronization signals thereby generated additional data indicative of an internal time count thereof for synchronization of transmission of data / signals from each one of the plurality of transmitter systems to said at least one receiver system over a sparse data / signals unidirectional communication channel.

In-band communication methods and transceivers are provided to enable protocol-agnostic management channel. One illustrative in-band communications method includes: buffering an outbound data stream from a host-side receiver with a data stream buffer, the outbound data stream having a first bit rate; and providing a line-side data stream representing the outbound data stream with an additional word after every N words of the outbound data stream, the line-side data stream having a second bit rate derived from a fill level of the data stream buffer, the additional words including message words and idle words with adjacent message words potentially separated by a predetermined number of idle words.

The invention relates to the resetting of a receiver timer of a receiver for correlating receiver time information with a time generated by a transmitter timer of a transmitter, wherein the receiver is designed to receive radio messages transmitted to it by the transmitter. During this resetting, a first message from the transmitter is received by the receiver, wherein the reception comprises a radio time period during which the receiver's radio is active. Information is determined from which the start time or end time of the radio time period can be determined. The receiver timer is then reset according to the determined information. The method is flexible and can be used in particular for so-called "sleepy devices" or receivers that are temporarily in a sleep state.

A clock synchronization method is disclosed. The method comprises receiving master timing synchronization data from a master clock device, wherein the master timing synchronization data is based at least in part on quantum data obtained from a first quantum device of the master clock device. The method comprises determining local timing synchronization data that is based at least in part on local quantum data obtained from a second local quantum device, wherein the second local quantum device is entangled with the first quantum device such that the local quantum data and the quantum data obtained from the first quantum device are identical at a same time. The method comprises using the determined local timing synchronization data and the received master timing synchronization data to determine a timing correction factor. The method comprises correcting a local system time using the timing correction factor.

Systems and methods for reducing a number of comparators used during an alignment marker (AM) search are presented. A method includes enabling communication between a physical coding sublayer (PCS) having a PCS transmit side and a PCS receive side with a physical medium attachment (PMA) sublayer, at a first end, using multiple PCS lanes that receives data blocks from the multiple PCS lanes, wherein a PCS lane includes an alignment marker (AM) on the PCS transmit side and performs an AM search using a first AM search stage circuit, wherein, in the first AM search stage circuit, all of the multiple PCS lanes are consecutively searched with read components on the PCS receive side until an AM is detected in all of the multiple PCS lanes.

A communication system comprising a light source associated with a first item of interest; a visible light communications system operably coupled to the light source of the first item of interest, the visible light communications system configured to process information as an encoded signal and output the encoded signal via the light source; and a receiver associated with a second item of interest, the receiver configured to receive the encoded signal from the light source and process the encoded signal to obtain the information.

Transceiver array synchronization by receiving a clock signal and at least one synchronization pulse signal at each transceiver IC of a plurality of transceiver integrated circuit (IC) subarrays, wherein each transceiver IC subarray contains a respective set of serially connected transceiver ICs; and synchronizing the transceiver IC with other transceiver ICs of the respective set of serially connected transceiver ICs by resetting a delta-sigma modulator (DSM) circuit to a predetermined state in accordance with the received at least one synchronization pulse signal.

Transceiver array synchronization by receiving a clock signal and at least one synchronization pulse signal at each transceiver IC of a plurality of transceiver integrated circuit (IC) subarrays, wherein each transceiver IC subarray contains a respective set of serially connected transceiver ICs; and synchronizing the transceiver IC with other transceiver ICs of the respective set of serially connected transceiver ICs by resetting a delta-sigma modulator (DSM) circuit to a predetermined state in accordance with the received at least one synchronization pulse signal.

In-band communication methods and transceivers are provided to enable protocol-agnostic management channel. One illustrative in-band communications method includes: buffering an outbound data stream from a host-side receiver with a data stream buffer, the outbound data stream having a first bit rate; and providing a line-side data stream representing the outbound data stream with an additional word after every N words of the outbound data stream, the line-side data stream having a second bit rate derived from a fill level of the data stream buffer, the additional words including message words and idle words with adjacent message words potentially separated by a predetermined number of idle words.

Methods and system for one-line synchronous interface are described. A timing device including a first buffer can be connected to a line card including a second buffer. The timing device can control the first buffer to output a synchronization pulse to the line card periodically at a time interval. For each output of the synchronization pulse, the timing device can switch the first buffer from a first output mode to a first input mode. Under the first input mode, the timing device listen for incoming data on the trace. The line card can receive the synchronization pulse periodically at the time interval. For each receipt of the synchronization pulse, the line card can switch the second buffer from a second input mode to a second output mode. Under the second output mode, the line card can transmit outgoing data on the trace.

The invention relates to a device, in particular a microcontroller, for synchronizing or adjusting a clock signal for software, comprising a processor for executing the software based on the clock signal, wherein the clock signal defines the beginning or the end of a software period, a measurement timer module that increments a timer value based on a device clock, an output unit designed to output a signal to a signal output of the device at the beginning of a synchronization period defined by the software period or a multiple thereof, an input unit designed to receive an input signal at a signal input of the device, and a register unit designed to store a current timer value of the measurement timer module at the end of the synchronization period.wherein the measurement timer module is designed to reset the timer value to a start value, in particular to zero, upon receiving an input signal. The invention is characterized by a comparator unit designed to compare the timer value stored in the register unit with the synchronization period and, depending on the comparison result, to adjust at least one subsequent period of the clock signal for the software running on the processor, in particular to lengthen or shorten it.

A method for synchronizing a data frame and data symbols in a communication system includes generating a training sequence including a serial sequence of data symbols that are conjugate symmetric, inserting the training sequence in a transmitter-side data frame, converting constituent data symbols of the transmitter-side data frame to communication signals, transmitting the communication signals from a transmitter to a receiver, converting the communication signals to a stream of received data symbols, detecting presence of the training sequence in the stream of received data symbols, and identifying a position of a received data frame from the presence of the training sequence.

The invention provides a data receiving method, a data sending method and a data exchange device, and the method comprises the steps: changing the frequency of a second clock signal in response to the change of a reference clock from a first preset frequency to a second preset frequency, and enabling the frequency of the second clock signal and the frequency of the reference clock to meet a preset relation; according to a second preset frequency, performing delay processing or advanced processing on the second clock signal to obtain a third clock signal; receiving a serial data stream according to the third clock signal, wherein the serial data stream has a data transmission delay of a first preset duration; wherein the frequency of the third clock signal is equal to that of the first clock signal, and the phase difference between the third clock signal and the first clock signal is equal to the first preset duration. According to the invention, the transmission accuracy of the serial data stream can be ensured after the frequency of the reference clock is changed.

This disclosure generally relate to a method and system for network policy simulation in a distributed computing system. The present technology relates techniques that enable simulation of a new network policy with regard to its effects on the network data flow. By enabling a simulation data flow that is parallel and independent from the regular data flow, the present technology can provide optimized network security management with improved efficiency.

An apparatus for generating a data stream according to an embodiment is provided. The apparatus is configured to generate the data stream, such that the data stream has header data and payload data. The apparatus is configured to generate the header data such that the header data comprises a synchronization header. Moreover, the apparatus is configured to generate the synchronization header using binary coding. Furthermore, the apparatus is configured to generate the synchronization header such that the synchronization header comprises a synchronization sequence being a predefined bit sequence having a plurality of bits.

To provide a signal generation device capable of reducing the time required for phase matching while remarkably increasing a maximum phase difference, with which phases can be matched, between signals outputted from a plurality of transceivers and a signal generation method.SOLUTION: In a signal generation device, a phase synchronization control section 31 executes first phase move processing for moving a phase of a toggle pattern from an initial value just by a first initial phase difference PC1 and second phase move processing for moving the phase of the toggle pattern, which is moved by the first phase move processing, just by a second initial phase difference PC2. The second phase move processing is repeatedly executed while decreasing a frequency division ratio step by step by a frequency division ratio setting section 33. After the first phase move processing or the second phase move processing is executed when the frequency division ratio is equal to or less than a predetermined value, a clock selection section selects an external clock in place of a frequency divided clock.SELECTED DRAWING: Figure 6

Provided is a high frequency signal receiving unit that receives a first high frequency signal and that generates a first intermediate frequency signal. A packet generating unit generates a packet on the basis of the first high frequency signal. A packet output unit outputs the generated packet to a communication path. A packet receiving unit receives the packet via the communication path. A packet interpreting unit performs synchronization processing for the packet and generates a second intermediate frequency signal. A high frequency signal transmitting unit converts the second intermediate frequency signal into a second high frequency signal and transmits the second high frequency signal. A wireless receiver receives the second high frequency signal and performs positioning or time synchronization on the basis of the second high frequency signal.

A communication system includes a master communication device and a slave communication device. The master communication device includes a first signal generator, a second signal generator, a signal combiner, and a transmitting HBC (Human Body Communication) electrode. The signal combiner combines a first signal with a second signal, so as to generate a third signal. The transmitting HBC electrode transmits the third signal through a human body. The slave communication device includes a receiving HBC electrode, a signal splitter, a processor, and an injection-locked DCO (Digital Control Oscillator). The receiving HBC electrode receives a mix signal from the human body. The signal splitter divides the mix signal into a data signal and a synchronization signal. The injection-locked DCO performs a time synchronization process according to the synchronization signal.

This invention discloses a network synchronization device that may include a matched filter. The matched filter may be configured to generate an event for synchronizing the operation of elements in the network, at least in part in response to a timing frame generated at a network switch. The event for synchronizing the operation of the element may include a first event generated at least in part in response to first information associated with a first element and a second event generated at least in part in response to second information associated with a second element. Related systems and methods are also disclosed.

To provide a sequence pattern generating device which enables a user to arbitrarily set output to be restarted synchronously with the restart of a sequence.SOLUTION: A sequence pattern generating device includes a synchronous setting screen 301 having a primary module selection button 311 and a secondary module selection button 312 for selecting a module to be synchronized, and synchronous selection buttons 313, 314, 315, and 316 provided for each output of the selected module and for selecting whether or not to synchronize when restarting a sequence.SELECTED DRAWING: Figure 5

A wireless communication method using a large intelligent surface (LIS) is provided. The method includes transmitting preamble signals each with a different transmission time and transmission direction, receiving preamble signals through an LIS through which an incident radio wave is received and reflected and determining a reference angle of incidence for the preamble signals, receiving the preamble signals that are delivered through a multipath from the terminal, transmitting identification information of a preamble signal having the largest reception power among the received preamble signals to the LIS server, and when the preamble signals includes a preamble signal corresponding to the identification information received from the base station, controlling the LIS such that an angle of reflection at which a data service signal transmitted from the base station is reflected by the LIS corresponds to the reference angle of incidence determined for the preamble signal of the identification information.

A method for adjusting a periodicity of communication between a wheel unit and a remote monitoring and / or control device, a communication being carried out using ultra-high-frequency radio waves, the wheel unit sending with a predetermined first periodicity basic signaling messages indicating its presence to any communication device located in an environment of the wheel unit. The wheel unit, having previously stored a group of communication devices authorized to serve as monitoring devices therefor, checks whether the communication device having sent a response message belongs to the group, and, if this is the case, the wheel unit replaces the first periodicity with at least one shorter second periodicity resulting in a more intense two-way exchange for any signaling message subsequently sent from the wheel unit to the authorized device.