177results about "Correct operation testing" patented technology

The invention discloses a high-load data steganography method, system and device and a medium, and the method comprises the steps: obtaining secret data of a power system, and converting the secret data into a novenary sequence; a quantum key distribution system is utilized to generate a shared key, the novenary sequence is encrypted through an encryption key, encrypted information is obtained, and the shared key comprises the encryption key and a mapping key; determining a corresponding first unit matrix from a preset mapping library based on the mapping key, and performing non-overlapping tiling on the first unit matrix in a two-dimensional plane to obtain a second-order reference matrix; and scanning a preset carrier image into a non-overlapping first pixel pair sequence according to a Hilbert curve, and embedding the encrypted information into the first pixel pair sequence by using the second-order reference matrix to obtain a steganographic image, so that the data transmission security can be improved.

The invention provides a UCIe-based data transmission method, a storage medium and an artificial intelligence chip. The data transmission method comprises the following steps: communicating with a second core particle through a first core particle; receiving a bypass receive data signal and a bypass receive clock signal from the transmit module of the first core particle through the receive module of the second core particle; the serial-to-parallel conversion module is used for transmitting the bypass receiving data signal and the bypass receiving clock signal to the second core particle through the receiving module; counting the bypass receiving clock signal through a serial-to-parallel conversion module to obtain a bypass receiving frame count value, and sampling a bypass receiving data signal according to the bypass receiving frame count value; a serial-to-parallel conversion module decides to count a bypass burr removal count value according to a bypass burr removal counter starting signal; and when the bypass glitch removal count value is equal to the bypass glitch removal counter threshold value, resetting the bypass receiving frame count value through the serial-to-parallel conversion module. According to the invention, good data transmission quality among the core particles can be realized.

The invention provides a UCIe-based data transmission method, a storage medium and an artificial intelligence chip. The data transmission method of the present disclosure comprises the steps of: communicating with a second core particle through a first core particle; pre-sampling a plurality of previous valid frame signals by a second core particle; transmitting the current effective frame signal and the data signal to a second core grain through the first core grain; judging error bit positions of a plurality of previous effective frame signals through a second core grain; generating a detection signal according to the error bit position through the second core particle; and determining whether to write the data signal into a receiving cache module of the second core grain according to the detection signal through the second core grain. According to the UCIe-based data transmission method, the storage medium and the artificial intelligence chip, good data transmission quality can be provided.

The invention discloses a fusion terminal data processing method and system based on frame repair, which are applied to the technical field of intelligent communication, and the method comprises the following steps: detecting the integrity of a received data frame, and taking an incomplete data frame as a damaged data frame; identifying the data type of the data segment of the damaged data frame according to the damage condition of the damaged data frame, the adjacent data frame of the damaged data frame and the sample library, and judging whether the damaged data frame is repairable or not; and repairing the repairable damaged data frame according to the data type, verifying the repaired data segment through the verification segment, and using the repaired damaged data frame as a normal data frame. According to the method and the device, the data segments of the data frames are repaired, wrong retransmission in the network can be effectively reduced, the integrity and timeliness of data transmission are improved, channel blockage in the network caused by network fluctuation is avoided, and the method and the device have extremely high applicability.

The invention provides a satellite service data analysis method and system based on a dynamic protocol, belongs to the technical field of satellite real-time data processing, and is used for analyzing satellite data downloaded by a data transmission link so as to complete closed-loop verification on a satellite data transmission core data flow path. The method depends on the support capability of an on-satellite data transmission system for a multi-channel downloading mode, and the independent, lossless and time sequence fidelity binary disk falling capability of ground detection equipment for each channel data. The method comprises the following steps: acquiring original downlink data highly consistent with an on-orbit state; secondly, adopting a scheduler model to carry out structured segmentation and affiliation allocation on the AOS frame after the original data stream is restored; and finally, dynamically loading a corresponding protocol description file for each data unit, and performing field-by-field decoding according to a mapping rule of binary data and readable engineering quantity to generate structured table data. The method can be widely applied to whole-satellite integration test scenes of various remote sensing satellites such as optics, SAR and infrared.

The invention discloses a subcarrier-level diversity combining method and subcarrier-level diversity combining equipment for multi-frequency diversity, and relates to the technical field of wireless communication. The method comprises the following steps: receiving a plurality of frequency points bearing the same service, and respectively carrying out orthogonal frequency division multiplexing demodulation on each frequency point to obtain a symbol estimation value; calculating a soft decision log-likelihood ratio and a reliability vector according to the symbol estimation value; aligning the time deviation, the carrier frequency deviation and the sampling rate deviation generated by frequency crossing of each frequency point based on each symbol estimation value; performing decorrelation processing on the aligned soft decision log-likelihood ratio to obtain a decorrelated soft decision log-likelihood ratio, and performing merging operation on the decorrelated soft decision log-likelihood ratio according to the aligned reliability vector to obtain a merged soft decision log-likelihood ratio; and decoding the merged soft decision log-likelihood ratio to obtain a decoding result, and adjusting the merging operation according to the decoding result. By implementing the technical scheme provided by the invention, the diversity combining accuracy can be improved.

The invention provides a non-fragile state estimation method and system of a Chua's circuit system under an error code condition, and belongs to the field of signal processing. The problem that the existing state estimation method cannot consider communication limitation, random change coupling, multiple random time-varying delay, nonlinearity, bounded random noise and estimator gain change at the same time, so that the state estimation performance is reduced is solved. The method comprises the following steps of: sequentially establishing a mathematical model taking a Chua's circuit as a complex network system node, a mathematical model in which a binary bit obtained by coding randomly generates an error code when being transmitted, a mathematical model for recovering a measurement signal after compensating the error code, and a mathematical model of a non-fragile state estimator, and then calculating a node state estimation error. Obtaining an overall estimation error augmentation system of the complex network system, and finally solving the unknown gain of the non-fragile state estimator. And substituting the gain into the non-vulnerability state estimator to realize estimation of the mathematical model taking the Chua's circuit as the complex network system node.

Systems and methods are provided for detecting bit errors and further processing bit error information. A method, according to one implementation, includes the step of receiving a binary test sequence pattern generated by a pattern generator at an input to a digital communications system under test, wherein the binary test sequence pattern includes a plurality of sub-patterns. The method also includes the step of receiving an output binary sequence from an output of the digital communications system. Also, the method includes comparing the binary test sequence pattern with the output binary sequence to detect bit errors. Based on correlation characteristics between the bit errors and each of the sub-patterns, the method also includes the step of determining whether the bit errors are caused by random factors or are caused by deterministic factors associated with the digital communications system.

The invention discloses a multi-modal data encryption transmission method and system, and the method comprises the steps: carrying out the time sequence synchronization slicing of multi-modal data according to the data type, extracting the key frame of each slice after the time sequence synchronization slicing, and associating the key frames to the same timestamp, and the data type of the multi-modal data comprises video data, audio data and text data; based on the timestamp, the signaling header and the intra-frame data of the key frame, generating an encryption key through cross-modal feature fusion, and encrypting the header of the corresponding key frame to obtain an encryption slice; and transmitting the encrypted slice through the main transmission channel, generating an unencrypted virtual slice when the length of the slice is not matched with the minimum value of the length of the slice of the corresponding data type, and transmitting the virtual slice through the auxiliary signaling channel to coordinate a transmission path. Key frames of a video, an audio and a text are bound to the same timestamp through time sequence slices, and a dynamic key is generated based on cross-modal feature fusion, so that the problem of collaboration deficiency in multi-modal data encryption is solved.

Devices, networks, systems, methods, and processes for determining receiver performance metric of a network device are described herein. A device may utilize one or more error patterns associated with the network device to retrieve one or more symbol errors from the one or more error patterns. The device can determine an error threshold for a segment based on a predefined Bit Error Rate (BER) level for the segment. The device may generate a performance metric for the segment based on the error threshold and the retrieved symbol errors. The device can generate a receiver performance metric based on performance metrics of segments. The device may determine a Code Error Ratio (CER) and can predict a Frame Loss ratio (FLR) associated with the network device based on the CER.

The invention discloses a WiFi-to-LoRa long-distance transmission method based on cross-protocol communication, and the method comprises the steps: carrying out the up-sampling and cyclic prefix removal of a simulated LoRa signal, carrying out the calculation of a LoRa sub-signal through an FFT algorithm, obtaining a frequency domain component of a corresponding bandwidth, and determining a to-be-used OFDM sub-carrier; selecting the closest constellation point to replace the deviated frequency domain component, and zeroing other constellation points except the constellation point corresponding to the effective subcarrier to complete QAM decoding of the LoRa signal; converting the symbols after QAM decoding into bit data, performing convolutional coding on the bit data, grouping the bit data according to preset bits, and performing QAM coding to generate corresponding QAM symbols; a plurality of QAM symbols are distributed to OFDM subcarriers at the same time, frequency domain components are converted into time domain signals through inverse Fourier transform, and long-distance transmission is carried out. According to the invention, long-distance transmission from WiFi to LoRa can be realized.

This disclosure generally relate to a method and system for network policy simulation in a distributed computing system. The present technology relates techniques that enable simulation of a new network policy with regard to its effects on the network data flow. By enabling a simulation data flow that is parallel and independent from the regular data flow, the present technology can provide optimized network security management with improved efficiency.

The present disclosure provides a computer implemented method for mapping signal ports in a quantum computer control system comprising a plurality of signal ports, the method comprising outputting at least one test signal on at least one of the signal ports of the quantum computer control system, measuring at least one response signal on at least one of the signal ports of the quantum computer control system, and determining a port mapping for the quantum computer control system based on the at least one test signal, and the at least one response signal. Further, the present disclosure provides a respective quantum computer control system and a respective quantum computer.

A device includes a transmitter coupled to a node, where the node is to couple to a wired link. The transmitter has a plurality of modes of operation including a calibration mode in which a range of communication data rates over the wired link is determined in accordance with a voltage margin corresponding to the wired link at a predetermined error rate. The range of communication data rates includes a maximum data rate, which can be a non-integer multiple of an initial data rate.

A system and method for identifying and addressing vulnerabilities in artificial intelligence models using a large language model. The system generates a set of topics for at least one specific domain and a set of interaction topics associated with the topics. A matrix is created with the topics on one axis and the interaction topics on another. The system generates prompts for junctures in the matrix that violate a corresponding topic. The prompts are input into the large language model to generate violative responses. These responses are then scored based on a predetermined scoring rubric.

This invention discloses a frame header detection method and system for configurable multi-rate SDH lines, relating to the field of optical synchronous digital transmission. The method includes: acquiring the serial data stream rate; converting the serial data stream on the SDH line into parallel data; truncating the parallel data into eight segments of different lengths and buffering them into eight corresponding registers; performing bit alignment based on the A1 byte hit result of the data of different lengths; aligning the bit-aligned parallel data based on the A2 byte and outputting a frame header signal; judging the accuracy of each frame header and outputting valid data frames and valid frame header signals; obtaining the current system state based on the output valid frame header signals, and determining that a true frame header has been detected when the current system state is a fixed-frame state. This invention can flexibly configure frame headers for detecting multiple SDH rates, has high accuracy in frame header detection, and continuously provides indications of fixed-frame and frame loss states.

Embodiments of the present invention disclose a detection method, device, equipment and medium for a communication chip. The detection method for the communication chip includes a receiving-end detection method and a transmitting-end detection method for the communication chip. Specifically, the receiving-end detection method for the communication chip includes: during the operation of the communication chip, detecting the idle time slots at the receiving end of the communication chip; generating test vectors online and generating corresponding standard results; constructing a data frame containing the test vectors and sending the data frame to the receiving end of the communication chip through the idle time slots for processing to obtain a chip processing result; and performing a systematic comparison between the standard result and the chip processing result. The solution of the embodiments of the present invention realizes the online detection of the functional safety of the communication chip, and solves the problems of low detection coverage rate of the communication chip and consumption of a large amount of communication chip resources and performance during the detection process in the prior art.

A universal asynchronous receiver / transmitter includes a transmit register including information to be transmitted, a receive register including received information, a frame error check circuit that evaluates contents of the receive register for a frame error, and a control logic. The control logic routes contents of the transmit register to the receive register. During transmission of the contents of the transmit register to the receive register through a reprogrammable pin, the control logic modifies a bit inversion register to produce modified contents to be provided to the receive register. The modified contents cause a frame error. The control logic determines whether the frame error check circuit detects the frame error.

A device may receive a PDCCH signal, may decode encoded bits of the PDCCH signal to generate coded bits, may reencode the coded bits, and may calculate a detection error probability of each coded bit at an output of soft demodulation. The device may calculate a channel decoding error probability that cyclic redundancy check bits are still attached to the coded bits, and may calculate an error probability of channel reencoding, of each coded bit, due to error propagation of polar decoding and reencoding. The device may calculate a probability density of a BMR associated with the coded bits, and may calculate a threshold based on the detection error probability, the channel decoding error probability, the error probability of channel reencoding, and the probability density of a BMR. The device may determine that the PDCCH signal is invalid based on the BMR being greater than the threshold.

An example process determines a first error vector magnitude (EVM) of a signal output by a device under test (DUT). The process includes adding attenuation on a signal path between the DUT and a vector signal analyzer (VSA), where the attenuation is changeable; measuring, at the VSA, at least two second EVMs for different values of attenuation of the signal output by the DUT, where the at least two second EVMs are corrupted by noise from the VSA, and where each of the at least two second EVMs is based on two or more measurements; and determining the first EVM based on a linear relationship that is based on the first EVM, the at least two second EVMs, and a function based on the attenuation, where the first EVM is without at least some of the noise from the VSA.

Systems and methods related to charge locking circuits and control systems for qubits are provided. A system for controlling qubit gates includes a first packaging device including a quantum device including a plurality of qubit gates, where the quantum device is configured to operate at a low temperature. The system also includes a second packaged device including a control circuit configured to operate at a low temperature, where the first packaged device is coupled to the second packaged device, and where the control circuit includes a plurality of charge locking circuits configured to lock the charge of the first packaged device to the second packaged device. Wherein each charge locking circuit of the plurality of charge locking circuits is coupled to at least one qubit gate of the plurality of qubit gates via an interconnect such that each charge locking circuit of the plurality of charge locking circuits is configured to provide a voltage signal to the at least one qubit gate.

Systems, methods, and computer-readable media for updating configurations in sensors deployed in multi-layer virtualized environments. In some examples, a system can track information of sensors and collectors in the network. In response to determining that a specific collector becomes unavailable (e.g., the specific collector is down, offline or becomes unsupported), the system can determine affected sensors corresponding to the specific collector, determine a new collector among active collectors of the network for each of the affected sensors, and dynamically update configuration and settings of the affected sensors to maintain proper collector-to-sensor mappings and other settings on the affected sensors.

Systems and methods related to charge locking circuits and control systems for qubits are provided. A system for controlling qubit gates includes a first packaging device including a quantum device, the quantum device including a plurality of qubit gates, wherein the quantum device is configured to operate at cryogenic temperatures. The system further includes a second packaging device including a control circuit configured to operate at cryogenic temperatures, wherein the first packaging device is coupled to the second packaging device, and wherein the control circuit includes a plurality of charge locking circuits, wherein each charge locking circuit of the plurality of charge locking circuits is coupled to at least one qubit gate of the plurality of qubit gates via an interconnect, such that each charge locking circuit of the plurality of charge locking circuits is configured to provide a voltage signal to the at least one qubit gate.

A low voltage differential serial (LVDS) communication system includes a system-on-chip (SoC) which includes a transmitter configured to serially transmit data, a receiver configured to serially receive data, a loopback control circuit configured to provide transmitted test data from the transmitter directly to the receiver during testing, and a built-in self-test (BIST) circuit. The BIST circuit controls testing by setting a voltage level of a common mode voltage for the transmitter, providing a test data pattern for transmission by the transmitter and receiving the test data pattern from the receiver in which the loopback control circuit directly provides the transmitted test data pattern from the transmitter to the receiver when an internal loopback configuration is enabled, and determining whether the voltage level of the common mode voltage results in a pass or fail.

The present invention provides a redundant control method and system for SSI sensors based on the CAN FD bus. The master control module outputs a downstream CAN FD message through the CAN FD bus. A number of SSI sensor control devices respectively receive the downstream CAN FD message through their CAN FD bus transceiver interfaces. The CAN FD data unpacking module unpacks the downstream CAN FD message to obtain the data field. The SSI sensor configuration module analyzes the data field to obtain the configuration parameters for a specific SSI sensor, and the SSI sensor data transmission module drives the SSI sensor to operate. The SSI sensor data transmission module collects the measurement result feedback data of the SSI sensor. The CAN FD data packetizing module packetizes the measurement result feedback data to establish an upstream CAN FD message. The upstream CAN FD message is uploaded to the CAN FD bus, and finally the master control module receives the upstream CAN FD message, thereby realizing the real-time control and measurement data acquisition functions for the SSI sensors.

The invention discloses a test circuit for configuration channel logic, electronic equipment and a test method, an interface corresponding to a configuration channel is located at a Type-C interface, and the test circuit comprises a processor, an output selection module, an output excitation module, an output device, an input device and an input selection module. The processor comprises a test control module and a test code pattern output module, the test control module controls the output selection module to select a test code pattern output by the test code pattern output module, and analysis data is obtained through the output device, the input device and the input selection module according to the output excitation module. The test control module also controls the input selection module to select the test comparison module so as to determine a test result. According to the test circuit, hardware testing is adopted, the complexity of signal transmission is reduced, and on one hand, automatic, efficient and comprehensive testing is achieved according to a test case; on the other hand, the test range in the protocol is comprehensively covered according to the output excitation module, and test comprehensiveness is guaranteed.

This invention relates to network coding technology and discloses a network coding method based on maximum rank distance code. The method includes: performing network coding on transmitted data to obtain coded data; performing linear addition and multiplication on the coded data to obtain coded data packets; using a preset parity check matrix to perform error detection and location on the coded data packets to obtain an error matrix; and performing rank error correction on the coded data packets based on the error matrix to obtain the original source data. This invention also provides a network coding apparatus, device, and medium based on maximum rank distance code. This invention can reduce the amount of redundant data transmitted in the transmission network and maintain low latency and high data recovery success rate even in complex network environments.

This abnormality detecting device inputs a normal packet into a BERT model trained by using normal packets, and acquires the magnitude of attention with respect to each byte point when encoding the normal packet. Next, the abnormality detecting device randomly samples important byte points of the normal packet on the basis of the acquired magnitude of the attention of each byte point. Then, the abnormality detecting device rewrites the randomly sampled important byte points into random bytes, thereby generating a pseudo abnormal packet. Thereafter, on the basis of the abnormality levels for a normal packet group and a pseudo abnormal packet group, the abnormality detecting device determines a threshold value of abnormality level used for detecting abnormal packets. Thereafter, the abnormality detecting device uses the determined threshold value of abnormality level to detect abnormal packets.

An enhanced quadrature receiving serial interface circuit and a method for calibrating a quadrature receiving serial interface circuit are provided. A quadrature receiving serial interface circuit includes a first phase rotator and a second phase rotator that generate a same frequency quadrature clock. Calibration of the quadrature receiving serial interface circuit uses a pseudo-random bit sequence (PRBS) received by the quadrature receiving serial interface circuit. For calibration, half of the received PRBS bits are sampled, and phase rotators that generate in-phase 0 DEG and 180 DEG clock signals are adjusted to center the data eye of the half of the sampled PRBS bits. All data bits (even and odd data bits) of the received PRBS bits are then sampled, and a phase rotator that generates quadrature phase 90 DEG and 270 DEG clock signals is adjusted to center data eyes of all data bits of the PRBS bits, thereby completing calibration.

The application discloses a semantic communication decoding method based on space-based computing, comprising the following steps: receiving a semantic encoding signal transmitted through a channel, and generating an initial decoding distribution through a non-autoregressive semantic decoder; constructing an empty information observation adapting to the current channel characteristics, inputting the observation into the decoder to estimate an implicit language prior, and correcting the initial decoding distribution to obtain a corrected channel likelihood distribution; combining the semantic prior of a pre-trained language model, quantifying the channel uncertainty and semantic uncertainty of each word position respectively, and generating a refinement priority based on the source ratio of the channel uncertainty in the total uncertainty; and iteratively refining the text sequence according to the priority. The application can explicitly eliminate the internal prior bias of a large model by using an empty observation, suppress the illusion phenomenon under a low signal-to-noise ratio, and realize the on-demand allocation of computing resources by distinguishing the uncertainty sources, thereby improving the accuracy and efficiency of decoding.