14 results about "Gigabit Ethernet" patented technology

The application provides a vehicle-mounted Ethernet communication plug-in. The plug-in comprises an MCU unit, a switching chip, a PHY chip, a high-speed signal connector and a power connector. The MCU unit is configured to configure and manage the switching chip. The switching chip is connected with the PHY chip, the high-speed signal connector and the power connector, and is configured to provide at least two gigabit Ethernet interfaces and at least nine first hundred megabit Ethernet interfaces. One of the two gigabit Ethernet interfaces provides DC48V standard POE power supply externally through the power connector, and the other one of the two gigabit Ethernet interfaces is connected with a vehicle-mounted main control unit through the high-speed signal connector. The at least nine first hundred megabit Ethernet interfaces are respectively connected with one service unit through the high-speed signal connector.

The application relates to a ZYNQ-based fiber grating demodulation device and a gigabit Ethernet data transmission method thereof, and relates to the fields of optical fiber communication and sensing. The device takes a ZYNQ control module as a core, and is matched with a laser driver board, a laser, a beam splitter, an FBG sensor, a filter, a balanced photoelectric detector, a signal amplification module and an AD conversion module. The process is as follows: a terminal writes a filter characteristic curve into a PL end BRAM; the ZYNQ drives a laser, and the generated optical signal is reflected to the balanced photoelectric detector after passing through the beam splitter and the FBG sensor, is input into the PL end after photoelectric conversion, amplification and AD conversion; the PL end calculates and looks up a table to obtain a center wavelength; data is stored in a DDR3 through AXI and FIFO, and is uploaded to the terminal through a network port. Compared with a traditional MCU scheme, the application has the characteristics of fast operation speed, high integration degree and low transmission delay, and can be widely used in the fields of optical fiber communication and sensing measurement.

The utility model relates to communication technical field, concretely is a kind of gigabit ethernet port protection circuit.The protection circuit includes: difference signal positive electrode circuit and difference signal negative electrode circuit, for forming signal transmission path;Difference impedance matching circuit is used to suppress signal reflection;Power filter network circuit is used to filter high-frequency noise and suppress common-mode interference.The circuit architecture design of the utility model systematically solves the core technical problem in the high-speed transmission of gigabit ethernet port.In the signal transmission level, two-stage resistance-capacitance isolation and dynamic impedance matching mechanism construct the parameter self-adaptive signal transmission path, through the impedance buffer of series resistance, the direct current isolation of coupling capacitor and the dynamic adjustment of difference pair network, effectively suppress signal reflection and direct current bias interference, ensure the integrity of 10Gbps high-frequency signal in long-distance transmission.

This utility model relates to the field of computer equipment technology, and in particular to an integrated multi-USB remote access server chassis based on ARM architecture. It includes a casing and a heat dissipation assembly installed inside the casing. The casing includes a PCB board, power supply, USB port group, indicator light board, gigabit Ethernet port, and power socket. The heat dissipation assembly includes small heat dissipation vents on the back of the outer wall of the casing and large heat dissipation vents on both sides of the outer wall. Small cooling fans are bolted to the inside of the small heat dissipation vents, and water-cooling components are installed inside the large heat dissipation vents. This utility model, through the dual heat dissipation design of "small heat dissipation vents + small cooling fans" and "large heat dissipation vents + water-cooling components," forms a three-dimensional and efficient heat dissipation system, ensuring that the overall temperature of the chassis remains within a reasonable range, significantly improving the stability of server operation, and extending the service life of the equipment.

The utility model relates to control management module technical field, concretely relates to a 3UVPX control management module based on Feiteng E2000S, this module takes Feiteng tenglong E2000S CPU as the core, adopts specific package form, possesses advanced characteristic and rich integration function. Network design adopts WX1860AL4 and XPHY0111QFIGR combination, realizes gigabit ethernet interface function. Through leading out two way I2C as IPMB, combine chassis management unit ChMC and board card management unit IPMC, follow IPMI2.0 agreement, realize the collection and control to each module state information in chassis. The module high integration, the performance is superior, can effectively satisfy the multiple needs of rugged chassis management.

This invention relates to a VPX management and control arbitration device and method based on the Loongson 2K chip, belonging to the field of intelligent management and control and its localization technology. This invention, through a multi-bus, multi-redundancy mechanism, can achieve real-time decoding output of B-code timing information, multi-channel switching output of video and control functions, and interconnection of gigabit Ethernet networks. The core chip adopts an independently controllable domestic design, unaffected by bans. In unattended operation, the arbitration device can monitor the heartbeat of external host modules in real time, performing real-time monitoring, management, and control, achieving hot backup from modules to applications and rapid response intelligent management and control. All external display and control outputs are implemented by the arbitration device; the external host module only needs to focus on control calculations, while the management tasks are centralized in the arbitration device, and tasks are distributed among modules, reducing the failure rate.

This invention belongs to the field of information security and relates to a security monitoring device based on a VPX architecture. It includes: a main processing module for processing and computing business data; a bridge module electrically connected to the main processing module for expanding auxiliary peripherals; a management and control module electrically connected to both the main processing module and the bridge module for system status monitoring and management; a network communication module electrically connected to the bridge module for providing four gigabit Ethernet interfaces to enable data interaction between systems; and a first level conversion module electrically connected to both the management and control module and the main processing module. This invention achieves end-to-end autonomous control from computation and control to security, enabling the perception and management of device health status, significantly improving fault diagnosis efficiency and system maintainability. It can operate stably in harsh environments such as national defense and aerospace, significantly improving system reliability and lifespan.

This invention discloses a UAV computing module and design method for vision and IMU fusion, belonging to the field of UAV autonomous navigation. The computing module includes a minimum operating system based on the RK3588 chip, and a peripheral system integrating IMU data acquisition circuitry, a first interactive interface circuit (such as RS232 / RS422), a second interactive interface circuit (multiple gigabit Ethernet ports extended via an Ethernet switching chip), and multiple vision interface circuits. The module adopts a modular design of a core board and interface expansion boards, supporting wide voltage input and intelligent temperature control. Its design method includes constructing the minimum system, deploying peripheral circuits, and making electrical connections. This invention solves the problems of missing IMU data, insufficient flight control and swarm communication interfaces, poor compatibility, and low domestic production rate in existing solutions, significantly improving the autonomous navigation, swarm collaboration, and obstacle avoidance capabilities of UAVs in denied environments, and achieving independent control of the supply chain.

This invention discloses a method and system for 10 Gigabit Ethernet to PCIe protocol conversion based on FPGA. The method is implemented using FPGA and includes: optimizing the TCP receiving module in the network protocol stack; converting PCIe data to 10 Gigabit Ethernet UDP / TCP data; and converting the UDP / TCP data received from 10 Gigabit Ethernet back to PCIe data. This invention utilizes the parallel processing capabilities of FPGA to implement the conversion between 10 Gigabit Ethernet and PCIe interface protocols in hardware, eliminating the need for CPU intervention and external DDR memory, thus reducing system overhead and improving system performance.

This invention provides a conversion device and method for interferometer data acquisition, comprising: a front-end signal input unit, a core processing unit, a back-end protocol output unit, a debugging and monitoring unit, and a power management unit. The conversion device described herein communicates with the interferometer using a custom data format, LVDS level, with a maximum speed of 100Mbps; data for each of the three axes is on a separate channel, ensuring transmission speed while improving communication stability; the raw data input from the interferometer is processed by an FPGA and converted into three BiSSC signals, corresponding to each of the previous channels, and finally output externally through a high-density DB15 connector; a gigabit EtherNet is designed, allowing monitoring of the communication status of all channels via the network port; a host computer interface is designed, which can output the position information waveforms detected by the three channels in real time, facilitating application debugging; and the BiSSC communication parameters can be adjusted via the network port, improving usability.

The utility model relates to communication field, concretely is a kind of 10-gigabit ethernet port protection circuit.The protection circuit includes: chip end signal preprocessing module, between chip end differential signal node (10GPHY_MD IAP_P0, 10GPHY_MD IAN_P0) and intermediate signal node (10GE_AP_TSP0, 10GE_AN_TSP0) are configured, for realizing initial impedance matching of signal input.The utility model constructs integrated chip end signal preprocessing, double resistance-capacitance isolation transmission, hierarchical surge protection and the synergic processing framework of POE power coupling, and systematically solves the core technical problem in 10-gigabit ethernet signal transmission.

The utility model relates to communication technical field, concretely is a kind of gigabit ethernet port protection circuit of supporting POE.The protection circuit includes: chip end signal preprocessing module, between chip end differential signal node and intermediate signal node, for realizing initial impedance matching of signal input;Dual resistance-capacitance isolation transmission module, between the intermediate signal node and network interface end differential signal node, including two levels resistance-capacitance coupling unit, for realizing direct current isolation, high-frequency signal transmission and noise filtering.The utility model constructs multilevel signal processing architecture between chip end and network interface end, with the collaborative design of signal preprocessing module, dual resistance-capacitance isolation transmission module, surge protection module and POE power coupling module to replace traditional network transformer, fundamentally solve the technical contradiction of high-density integration and low-cost implementation.

The application provides a multi-type sensor compatible ultra-low noise signal acquisition system, comprising an input driving unit, a low noise adaptive differential gain unit, an analog-digital conversion unit, a fault detection unit and a control communication unit. The application realizes an ultra-low noise signal acquisition system compatible with voltage / current / driven-free modes, adaptive to gain for large dynamic range signals and supporting multi-channel synchronous acquisition; the input driving unit of the application adaptively drives different sensors and picks up sensor output signals, meanwhile, the fault detection unit can detect sensor channel working states, then the adaptive differential gain unit amplifies the signals, the analog-digital conversion unit converts the signals into digital quantities, and then the control unit frames and sends the signals to the ground computer through a gigabit Ethernet isolation bus. The application has the advantages of high resolution, high precision, wide dynamic range, adjustable sampling rate, application to various types of sensors and the like.

This invention relates to the field of artificial intelligence security technology, specifically disclosing an AI security flaw detection system based on deep analysis and adversarial testing. The system includes a data preprocessing module, a deep analysis module, an adversarial testing module, a result evaluation module, a report generation module, and a central control module. The data preprocessing module communicates with the deep analysis module via a high-speed data bus. The deep analysis module communicates bidirectionally with the adversarial testing module via dual gigabit Ethernet. The adversarial testing module is connected to the result evaluation module via an InfiniBand network. The result evaluation module communicates with the report generation module via an HTTPS secure connection. The central control module is connected to each module via a CANFD control bus and a TSN time-sensitive data bus. Therefore, this invention, through the collaborative approach of deep analysis and targeted adversarial testing, can improve the accuracy of detecting security flaws in AI models and reduce the false negative rate. It is applicable to fields such as finance and healthcare, providing strong assurance for the reliable operation of AI systems.