91 results about "Gigabit Ethernet" patented technology

The invention relates to a forwarding control method and device, equipment and a medium, and relates to the technical field of communication. The method comprises the following steps: receiving a target data packet sent by a target terminal through a first gigabit Ethernet media access controller GMAC; wherein the first GMAC corresponds to a local area network side; under the condition that the target data packet is a first type of data packet, forwarding the target data packet through a second GMAC based on the forwarding table; wherein the first type of data packets are data packets which do not need to be processed by an application program and are forwarded based on a basic network protocol; the second GMAC corresponds to a wide area network side; under the condition that the target data packet is the second type of data packet, processing the target data packet through the application program, and forwarding the target data packet through the second GMAC after processing; wherein the second type of data packets are data packets which need to be forwarded after being processed by the application program. By adopting the method, intelligent forwarding control of the data packet can be realized.

The invention discloses a data network interaction system for rail transit data transmission, which relates to the technical field of data transmission and comprises a data acquisition module, an intelligent exchange scheduling module, a real-time processing module and a high-reliability transmission guarantee module. And high-speed and reliable transmission is ensured through a 10-gigabit point-to-point direct connection channel, and meanwhile, continuity is ensured by adopting a redundant link, so that efficient, stable and real-time processing of rail transit data is realized. According to the invention, a high-speed dedicated channel is constructed through direct connection of the 10-gigabit Ethernet, and hierarchical transmission of multi-source data is realized in combination with an intelligent scheduling strategy; meanwhile, hardware-level heartbeat detection and redundant links are deployed, and millisecond-level fault switching is guaranteed; and a dynamic threshold adjustment mechanism is introduced, the reliability and robustness of the system are adaptively optimized, and the high-real-time and high-reliability transmission requirements of rail transit are met.

The invention discloses an automatic test-oriented communication protocol and sequential logic cooperative control system, and relates to the technical field of nuclear field instrument and control system test, and the system comprises a 7-slot computer cage, a controller, a function card, a dual-path full duplex communication link, and a power supply monitoring module. The controller is fixed at the slot 0 of the 7-slot cage, and the function card is inserted in the slot 1 to the slot 6 in a mixed manner. And the controller is connected with each function card through a double-path full duplex communication link, is linked with the power supply monitoring module through a GPIO (General Purpose Input / Output) signal so as to monitor and control the power supply of the function card, and is also connected with the HMI through a gigabit Ethernet. The controller receives a test case of the HMI based on a first preset communication protocol, generates a test instruction, packages the test instruction into a control frame through a second preset communication protocol, issues the control frame according to three time sequence regulation and control modes, receives the state and test data returned by the function card, and intervenes the abnormal function card through the power supply monitoring module. And the function card analyzes the instruction, executes a test, collects and returns data, and reports the operation state at the same time.

The invention relates to the technical field of industrial control, and discloses a data analysis processing controller. The controller comprises a cabinet, an aviation plug front panel and a cabinet VPX backboard. External 24V direct current is connected with a cabinet VPX backboard through the power supply filtering module and is reduced to 12V direct current through the power supply module. A main control module, a digital quantity input / output module, an analog quantity input / output module and two reserved slot positions are integrated on a VPX backboard of the case, and all the modules are inserted into the standard slot positions through VPX connectors. The main control module is communicated with the function module through an RS232 bus and is integrated with a gigabit Ethernet, an RS485 interface and a CAN (Controller Area Network) interface; the digital quantity module adopts a dual-channel optical coupler isolation and self-checking technology, and the analog quantity module realizes dynamic fault switching through redundant output and controllable voltage superposition. Internal cable connection is eliminated through a VPX framework, the reliability, expansibility and real-time response capability of the system are remarkably improved by combining multi-stage power supply filtering and cold conduction and heat dissipation design, and the system is suitable for ship distance adjusting devices and other complex industrial environments.

The invention relates to a 16-port CPEX gigabit Ethernet switching module, and belongs to the technical field of gigabit Ethernet switching modules. The module adopts a three-layer switching mode, a user can change the working mode of the switching module through a debugging interface, and the state of each network port can be monitored online or configuration parameters of the network port can be changed. Gigabit network signals are output to the CPEX connector after being isolated by the transformer, and a hardware interface is stable and reliable. The switching module is provided with a single-chip microcomputer management module, so that reliable management of power-on and reset of the switching module can be realized.

The application provides a vehicle-mounted Ethernet communication plug-in. The plug-in comprises an MCU unit, a switching chip, a PHY chip, a high-speed signal connector and a power connector. The MCU unit is configured to configure and manage the switching chip. The switching chip is connected with the PHY chip, the high-speed signal connector and the power connector, and is configured to provide at least two gigabit Ethernet interfaces and at least nine first hundred megabit Ethernet interfaces. One of the two gigabit Ethernet interfaces provides DC48V standard POE power supply externally through the power connector, and the other one of the two gigabit Ethernet interfaces is connected with a vehicle-mounted main control unit through the high-speed signal connector. The at least nine first hundred megabit Ethernet interfaces are respectively connected with one service unit through the high-speed signal connector.

The application provides a numerical control EtherCAT master station bandwidth adaptive scheduling and link fault bypass control system and method, belongs to the numerical control system industrial Ethernet bus control technical field, and the system comprises a heterogeneous multi-core processor, a field programmable gate array, a local bus, a gigabit Ethernet physical layer unit and a storage unit; the heterogeneous multi-core processor contains a high-performance computing core and a low-power control core, is interconnected with the field programmable gate array through the local bus, and executes physically isolated task scheduling; the field programmable gate array solidifies message preprocessing filtering, message hardware shunting, bandwidth clipping and a multi-channel hardware bypass switch array module, each module is cascaded in cooperation according to a data flow direction, message hardware unloading, bandwidth dynamic adjustment and fault bypass topology reconstruction are realized. The application reduces bus cycle jitter, improves bandwidth utilization efficiency and link fault tolerance capability, and is suitable for high-end numerical control machine tool multi-axis linkage control scenes.

The invention provides a cluster system comprising a computing unit and a switching unit and a task processing method and device, and relates to the technical field of computers. The cluster system comprises N computing platforms, and each computing platform comprises a switching unit, a computing unit, a power supply unit, a monitoring management unit and a controller. The computing unit comprises at least one of a PC, a CPU, a GPU and a neural network computing module; the switching unit comprises a first type switching module which is used for connecting a hardware or software interface of a network, is responsible for sending, receiving and processing data, and comprises but is not limited to a gigabit Ethernet interface; the second type of switching module provides support for high-speed serial data transmission, adopts high-speed data interfaces, and comprises but is not limited to a Serdes interface and an LVDS (Low Voltage Differential Signaling) interface; the third type of switching module is a high-bandwidth and low-delay data interface which comprises but is not limited to an MCIO interface and a PCIe interface; and the fourth type of switching module is a high-bandwidth and high-density data transmission interface which comprises but is not limited to a QSFP interface and an OSFP interface.

The invention discloses a manufacturing process of a 10-gigabit Ethernet cable for a vehicle, and belongs to the technical field of cable manufacturing, and the manufacturing process comprises the following steps: 1, processing an oxygen-free copper wire by using a high-strength polycrystalline stranding wire-drawing die to realize surface treatment and outer diameter processing of the oxygen-free copper wire to obtain a conductive wire core; step 2, performing coating processing on the conductive wire core obtained in the step 1 by adopting a foaming PP formula and matching with a nitrogen injection mode, and uniformly forming an insulating protection layer on the surface of the conductive wire core to obtain a high-conductivity wire core; 3, pouring a high polymer material into an extruder, and carrying out coating processing of an insulating layer on the high-conductivity wire core obtained in the step 2 by using the extruder through a special mold to obtain a high-insulation wire; through the mutual cooperation of the twisted pair structure and the plurality of shielding layers, the electromagnetic compatibility of the cable is higher, and through the use of the oxygen-free copper wires, the internal resistance of the cable is reduced, and the twisted pair balance is improved.

The invention discloses a teenager education-oriented multi-mode interactive experience platform, and relates to the technical field of teenager education, interaction with a 5G intranet is carried out through a gigabit Ethernet, and user interaction comprises a 4KVR head display, a touch screen and a voiceprint recognition voice unit; the resource library is divided into four types of historical scenes and historical events and is updated quarterly; the generation module outputs multi-format content by using a GPT-4 lightweight model and verifies the multi-format content by an expert; intelligent adaptation is based on age, cognition and other portrait adaptation contents; a distributed architecture is adopted for storage, and a learning report is analyzed and output; safety comprises double content auditing and data desensitization; operation and maintenance are monitored for 7 * 24 hours, and remote operation and maintenance and automatic updating are supported; the problems that traditional education is single in form, poor in adaptation and insufficient in immersion are solved. Through multi-modal interaction, intelligent cognitive adaptation, safety control and closed-loop optimization, the interest and emotion resonance of teenagers are stimulated, and the attraction and effectiveness of cultural education are improved.

The application relates to a ZYNQ-based fiber grating demodulation device and a gigabit Ethernet data transmission method thereof, and relates to the fields of optical fiber communication and sensing. The device takes a ZYNQ control module as a core, and is matched with a laser driver board, a laser, a beam splitter, an FBG sensor, a filter, a balanced photoelectric detector, a signal amplification module and an AD conversion module. The process is as follows: a terminal writes a filter characteristic curve into a PL end BRAM; the ZYNQ drives a laser, and the generated optical signal is reflected to the balanced photoelectric detector after passing through the beam splitter and the FBG sensor, is input into the PL end after photoelectric conversion, amplification and AD conversion; the PL end calculates and looks up a table to obtain a center wavelength; data is stored in a DDR3 through AXI and FIFO, and is uploaded to the terminal through a network port. Compared with a traditional MCU scheme, the application has the characteristics of fast operation speed, high integration degree and low transmission delay, and can be widely used in the fields of optical fiber communication and sensing measurement.

The invention discloses a baseband data transmission method, device and system based on a collaborative cache architecture, and the method comprises the steps: constructing an FIFO-RAM collaborative cache architecture, enabling FIFO to be used for matching a data generation rate, and enabling an RAM to persistently store a data copy as a data pool for sending and retransmission; sending data packets in batches through a gigabit Ethernet UDP protocol; a batch response and double trigger retransmission mechanism is established between an upper computer and a lower computer, the upper computer returns a batch response signal to indicate a lost packet, and the lower computer actively triggers retransmission based on the signal and an internal timeout timer and directly reads data from an RAM for retransmission. According to the invention, high-speed reliable transmission of gigabit UDP data is realized on a pure FPGA platform, and the method has the advantages of high bandwidth utilization rate, low retransmission delay and low system complexity, and is especially suitable for continuous high-speed data stream scenes such as ionosphere detection and the like.

The utility model relates to the technical field of integrated circuits, in particular to a multi-interface integrated circuit of a point sale mainboard, a device connector is electrically connected with a USB 2.0 joint and a USB PD quick charge connector, and the USB 2.0 joint is in communication connection with a port concentrator SL2.1 S chip; the port concentrator SL2.1 S chip is provided with a 100M network card chip and a USB two-port concentrator in parallel, and the 100M network card chip is electrically connected with an RJ45 100M network port. According to the utility model, the USB two-port concentrator and the RJ45 100M network port interface are used, so that better anti-interference and anti-aging performance is achieved, compatibility and connection of various peripheral equipment are supported, the USB PD fast charging connector supports PD protocol fast charging and can support more peripheral equipment needing electric power, and a plurality of safety protection mechanisms are adopted, so that the safety of the USB PD fast charging connector is greatly improved. And the phenomenon of overvoltage overload damage caused by incorrect use of the adapter and equipment of the traditional AC power supply is avoided.

The utility model relates to communication technical field, concretely is a kind of gigabit ethernet port protection circuit.The protection circuit includes: difference signal positive electrode circuit and difference signal negative electrode circuit, for forming signal transmission path;Difference impedance matching circuit is used to suppress signal reflection;Power filter network circuit is used to filter high-frequency noise and suppress common-mode interference.The circuit architecture design of the utility model systematically solves the core technical problem in the high-speed transmission of gigabit ethernet port.In the signal transmission level, two-stage resistance-capacitance isolation and dynamic impedance matching mechanism construct the parameter self-adaptive signal transmission path, through the impedance buffer of series resistance, the direct current isolation of coupling capacitor and the dynamic adjustment of difference pair network, effectively suppress signal reflection and direct current bias interference, ensure the integrity of 10Gbps high-frequency signal in long-distance transmission.

The utility model belongs to the technical field of AI edge computing, and particularly relates to a high-performance AI box, which comprises a casing, an HDMI (High Definition Multimedia Interface) data input interface, an HDMI data output interface and a power supply interface are arranged on the surface of the casing, and a circuit board is arranged in the casing. The circuit board is provided with a central processor, a data storage module, an HDMI data decoding module, a data transmission module, an FPGA module and a power supply module, and the box is based on an RK3588 processor, is strong in operational capability, supports the efficient operation of a complex AI algorithm, is better in speed and precision of processing algorithms such as face detection, and accords with a high-real-time scene. The communication interface of the high-performance AI box integrates network peripherals such as a gigabit Ethernet, a Wi-Fi module and a 4G module and CAN, RS485 and UART local interfaces, the network adaptability is high, industrial equipment connection is facilitated, and the application range is widened. In the aspect of interaction, the HDMI OUT, the HDMI IN and the audio interface provide multi-element man-machine interaction, video display and audio playing can be realized by accessing the display and audio equipment, and the system is suitable for scenes such as security monitoring and the like.

The invention belongs to the technical field of engineering machinery electronics and electrical, and discloses an electric loader domain centralized electronic and electrical architecture based on vibration self-adaption and a control method, comprising a vehicle control domain, an intelligent driving domain, an intelligent cabin domain and an intelligent operation domain which are connected through a gigabit Ethernet to form an annular topological structure, and the MRP protocol is supported to realize less than or equal to 50ms fault switching. According to the invention, wire harnesses are greatly reduced, high reliability and low delay communication performance under high vibration, strong EMI anti-interference capability, high precision intelligent operation control and low cost are realized, and L4-level automatic driving related functions and new energy expansion are supported.

This invention belongs to the field of central control screen performance testing technology, specifically a performance testing device for central control screens in new energy vehicles. It includes a dynamic extreme environment reproduction chamber, a bionic human-computer interaction simulator, a multimodal parameter synchronous acquisition array, an intelligent decision-level analysis and evaluation engine, and a holographic visualization decision support terminal. The invention provides physical environment support through the dynamic extreme environment reproduction chamber, whose environmental parameters are synchronized in real-time to the multimodal parameter synchronous acquisition array via a CAN bus. The operation data generated by the bionic human-computer interaction simulator and the performance indicators acquired by the multimodal parameter synchronous acquisition array are preprocessed by edge computing nodes and then transmitted to the intelligent decision-level analysis and evaluation engine via gigabit Ethernet. The evaluation report generated by the intelligent decision-level analysis and evaluation engine drives the holographic visualization decision support terminal to display the results, thus realizing the construction of a closed-loop testing system. This significantly improves testing efficiency and performance evaluation accuracy, and demonstrates a high level of automation and intelligence.

The invention discloses a high-dynamic-range imaging CMOS camera based on a K7 gigabit network. The high-dynamic-range imaging CMOS camera comprises a camera shell 9, and a high-dynamic-range imaging CMOS camera body is installed in the camera shell 9. The CMOS camera body comprises a CMOS sensor chip 1, an FPGA (Field Programmable Gate Array) programmable logic device 2, a DDR3 (Double Data Rate 3) high-speed memory 3, a FLASH memory chip 4, a gigabit Ethernet interface 5, a GPIO (General Purpose Input / Output) isolation interface 6 and a power supply module 7. The FPGA chip receives high-gain and low-gain 2048 * 2048 resolution image data from the CMOS sensor chip at the same time, data caching is carried out through the DDR3 high-speed memory, high-dynamic-range image synthesis is completed in real time, images with 46 frames per second (the resolution is 2048 * 2048) and the dynamic range reaching 70.3 dB are output through the gigabit Ethernet interface, and working parameters of the camera can be configured through a computer.

The invention provides a data transceiving and high-speed storage system based on a domestic PSOC (programmable system on chip), which comprises a PSOC control layer which takes a Feidan micro PSOC as a core arithmetic unit and provides bottom computing power support for efficient operation of the system by means of excellent hardware acceleration capability and flexible programmable characteristics; the high-speed data interaction layer carries a multi-protocol receiving and transmitting module composed of RS422, CANFD, 4M 1553B, a gigabit Ethernet and an optical module, can be compatible with multi-scene data transmission requirements, realizes high-speed stable receiving and transmitting of multi-type data, and breaks the bandwidth bottleneck; according to the high-speed data storage layer, EMMC, SATA and NVMe SSD multi-element media are creatively integrated, a hierarchical high-capacity high-speed storage architecture is constructed, the requirement for real-time storage of mass data is met, data calling instantaneity is guaranteed, and guarantee is provided for high-throughput scene data processing and storage. Through various communication protocols and various high-speed storage devices, the compatibility and universality of the control system are improved.

This utility model relates to the field of computer equipment technology, and in particular to an integrated multi-USB remote access server chassis based on ARM architecture. It includes a casing and a heat dissipation assembly installed inside the casing. The casing includes a PCB board, power supply, USB port group, indicator light board, gigabit Ethernet port, and power socket. The heat dissipation assembly includes small heat dissipation vents on the back of the outer wall of the casing and large heat dissipation vents on both sides of the outer wall. Small cooling fans are bolted to the inside of the small heat dissipation vents, and water-cooling components are installed inside the large heat dissipation vents. This utility model, through the dual heat dissipation design of "small heat dissipation vents + small cooling fans" and "large heat dissipation vents + water-cooling components," forms a three-dimensional and efficient heat dissipation system, ensuring that the overall temperature of the chassis remains within a reasonable range, significantly improving the stability of server operation, and extending the service life of the equipment.

The invention provides an airborne photoelectric pod image and communication network conversion device based on heterogeneous calculation, and belongs to the technical field of networked transmission of video and communication data. The FPGA preprocessing unit is connected with the 3G-SDI video input unit; the RK3588 encoding unit is connected with the FPGA preprocessing unit, and an H.265 hardware encoder and a dynamic code rate control module are arranged in the RK3588 encoding unit; the RS422 / UDP protocol conversion unit is connected with the RK3588 coding unit and an external RS422 interface; and a gigabit Ethernet physical interface. According to the device, the FPGA preprocessing unit and the RK3588 coding unit are integrated, so that efficient video coding and communication protocol lossless conversion are realized, and dynamic code rate control and low-delay transmission are supported.

The invention discloses a high-speed redundant optical fiber communication device and method. The device comprises a first device and a second device which are respectively deployed locally and remotely; a redundant communication link is constructed between the first equipment and the second equipment through the main optical fiber and the slave optical fiber; data communicated between the first equipment and the second equipment is asynchronous data and / or high-speed Ethernet data; each of the first equipment and the second equipment comprises a power supply, a main control unit, a two-way RS422 interface, an asynchronous data processing module, a six-way gigabit Ethernet interface, an Ethernet processing module, an Ethernet switching module, a data multiplexing module and a photoelectric conversion module; one of the first equipment and the second equipment is data sending equipment; when the optical power of the main optical fiber is smaller than a preset threshold, the slave optical fiber is used; otherwise, using the main optical fiber. According to the invention, the problem of communication interruption caused by single link fault is solved, and high-reliability scene requirements are met.

The invention discloses a multichannel signal timestamp recording and transmitting device based on an FPGA (Field Programmable Gate Array), and belongs to the technical field of data acquisition and transmission. The device takes an FPGA (Field Programmable Gate Array) as a core processing unit, and integrates a gigabit Ethernet MAC (Media Access Control) module, a UDP (User Datagram Protocol) processing module, a control module and a timestamp acquisition and data encapsulation module; a 48-bit high-precision timestamp is generated through a 125MHz clock, independent detection and timestamp processing of rising edges / falling edges of eight paths of signals are achieved through a two-stage pipeline structure, timestamp real-time recording is completed through a first-stage pipeline, timestamp data load packaging is completed through a second-stage pipeline, and the recording period is 1 microsecond. Only when the change of the signal edge is detected, the packaged UDP data frame is sent through a GMII interface via a gigabit Ethernet; meanwhile, UDP command frame receiving and control word analyzing are supported, so that collection starting / stopping and edge detection type configuration are achieved. The system has the characteristics of strong real-time performance, high transmission rate and flexible configuration, and can be widely applied to scenes such as industrial automation, communication test, data acquisition of the Internet of Things and the like.

The utility model relates to control management module technical field, concretely relates to a 3UVPX control management module based on Feiteng E2000S, this module takes Feiteng tenglong E2000S CPU as the core, adopts specific package form, possesses advanced characteristic and rich integration function. Network design adopts WX1860AL4 and XPHY0111QFIGR combination, realizes gigabit ethernet interface function. Through leading out two way I2C as IPMB, combine chassis management unit ChMC and board card management unit IPMC, follow IPMI2.0 agreement, realize the collection and control to each module state information in chassis. The module high integration, the performance is superior, can effectively satisfy the multiple needs of rugged chassis management.

The utility model discloses a PCB mainboard based on Ethernet signal connection, which relates to the field of hardware circuit design and comprises an Ethernet chip, a main connector and an Ethernet connector. A signal output pin of the Ethernet chip is connected with an idle pin of the main connector so as to output a 100M Ethernet signal to the idle pin through the signal output pin; and a signal output pin of the Ethernet chip is connected with a target pin of the Ethernet connector, so that a gigabit Ethernet signal is output to the target pin through the signal output pin. Namely, the idle pin of the main connector is multiplexed to output the 100M Ethernet signal, an extra Ethernet connector is not needed to output the 100M Ethernet signal, and the gigabit Ethernet connector only needs to output the gigabit Ethernet signal, so that the cost of the gigabit Ethernet connector is saved.

The invention relates to a computer for a low-orbit satellite internet, and the computer comprises a graphic processing unit (GPU) which is configured to execute an operation task in a satellite-borne scene; a field programmable gate array (FPGA) which is configured to expand a plurality of satellite load interfaces and perform data preprocessing; the data transmission module is configured to realize bidirectional data transmission between the GPU and the FPGA; and the networking expansion module is configured to improve the computing power of a computer, the networking expansion module comprises two paths of Ethernet physical layers PHY, the two paths of Ethernet physical layers PHY are configured to output gigabit Ethernet signals, and the two paths of Ethernet physical layers PHY are connected with the GPU. According to the computer, the computing power can be expanded, the total computing power is improved, meanwhile, various loads are compatible, the compatibility is improved, and the secondary development cost is reduced.

The application belongs to the field of coherent synthesis, and discloses a multi-channel laser coherent synthesis SPGD algorithm verification platform based on FPGA, which is used for solving the problem that the MATALAB software simulation SPGD algorithm is not accurate, and the simulation system of the application combines software and hardware, first, the SPGD algorithm and related simulation modules are deployed into the FPGA board card; then, the software simulation light path is established in the computer; subsequently, the FPGA is connected with the computer through the gigabit Ethernet interface to establish the data interaction channel; then, the internal parameters of the SPGD algorithm are set by sending instructions from the computer to the FPGA, and the SPGD algorithm simulation is started; after that, the positive and negative voltage values calculated by the SPGD algorithm are sent to the computer, and after the positive and negative voltage data are received by the computer software simulation light path, the ADC data are calculated and sent to the FPGA; finally, the simulation of the SPGD algorithm is realized through the cyclic data interaction between the FPGA and the computer. The method of the application can simulate the simulation of the SPGD algorithm under complex experimental environment, improve the accuracy of the simulation, and increase the success rate of the experiment.

This invention relates to a VPX management and control arbitration device and method based on the Loongson 2K chip, belonging to the field of intelligent management and control and its localization technology. This invention, through a multi-bus, multi-redundancy mechanism, can achieve real-time decoding output of B-code timing information, multi-channel switching output of video and control functions, and interconnection of gigabit Ethernet networks. The core chip adopts an independently controllable domestic design, unaffected by bans. In unattended operation, the arbitration device can monitor the heartbeat of external host modules in real time, performing real-time monitoring, management, and control, achieving hot backup from modules to applications and rapid response intelligent management and control. All external display and control outputs are implemented by the arbitration device; the external host module only needs to focus on control calculations, while the management tasks are centralized in the arbitration device, and tasks are distributed among modules, reducing the failure rate.

The invention belongs to the field of virtual reality (VR) technology, and particularly relates to a VR virtual classroom teaching system which is characterized in that a 1-N synchronous teaching path is formed by a teacher VR head-mounted display, a teacher video card, a teacher notebook computer, a gigabit Ethernet switch, a student VR terminal network card and a student VR head-mounted display. The beneficial effects of the invention are that: 1) the structure is extremely simple, a 1-to-N one-way visual angle broadcast type VR classroom teaching system is established, and the system is used for synchronously pushing the real-time visual angle of the VR head-mounted display at the teacher end to the VR head-mounted displays at all student ends in a frame-level precision manner, so that students can watch the same teaching content in an immersive manner at the position and angle of the eyes of the teacher, and the teaching efficiency is improved; respective operation or mutual interference is not needed; any external hardware is not added, repeated rendering is not carried out, only the head of a teacher is utilized to display a rendered left eye (or right eye) frame, a student end synchronously sees a picture which is watched by the teacher in the lt, 80 ms, and the student end receives data streams in the local area network, and the bandwidth occupation of the local area network streaming media broadcasting mode is extremely small.

The invention discloses an Ethernet circuit and a design method. The circuit comprises an Ethernet PHY chip, an Ethernet connector, a 100M Ethernet communication branch and a gigabit Ethernet communication branch. The 100M branch circuit is connected in series with a first common mode choke coil, a first common mode terminal circuit and a first vehicle-mounted connector and is distributed at the bottom layer of the PCB; the gigabit branch is connected in series with a second common-mode choke coil, a second common-mode terminal circuit and a second vehicle-mounted connector and is distributed on the top layer of the PCB, the line of the gigabit branch extends to the bottom layer through a water drop type connecting line and a punched hole, symmetrical through holes are formed in the two sides of the punched hole, the two branches share the PHY chip and the same pair of pins of the connector, and an independent reference ground and a same-layer shielding ground are configured. According to the invention, independent and exclusive common-mode chokes and common-mode terminal circuits are respectively configured for 100M and gigabit Ethernet communication branches, so that filter devices do not need to be forcibly shared, the problem that filter devices with different rates cannot be universally used due to large frequency characteristic and packaging difference is fundamentally avoided, and the stable communication performance of each rate is ensured.