651 results about "Gigabit Ethernet" patented technology

A system and method is disclosed for increasing the efficiency of a cellular communication network, reduce ongoing operating costs and increase revenue. According to one aspect, a method is disclosed for increasing the efficiency of a cellular communication network whereby network capacity in the radio access network (RAN) and baseband processing for wireless connections are dynamically adjusted to automatically provision sufficient bandwidth and baseband processing capacity in response to changes in the network. The method is further extended by implementing policy management which allows wireless carriers to develop and implement network based policies to automatically increase or decrease the amount of processing resources and network bandwidth required from any cell site, hub or mobile switching office. According to another aspect, network efficiency is enhanced by utilizing a novel cellular network infrastructure. RF signals from cell site antennas of various technology types are demodulated, digital bit information is extracted from the RF signals, processed, and groomed into Gigabit Ethernet/Resilient Packet Ring (GigE/RPR) or Ethernet over copper traffic flows using specific Quality of Service (QoS) priorities. The GigE/RPR traffic flows are routed to hub sites or mobile switching offices, at which point the packetized information is extracted and converted to RF signals that are equivalent to the signals that were received at the antenna. The RF signals are sent over coaxial cable to a network hub including a pool of Base Transceiver Stations (BTSs) (or Node Bs). The hub is coupled to one or more mobile switching offices via a second fiber optic ring.

A system and method providing virtual channels with credit-based flow control on links between network switches. A network switch may include multiple input ports, multiple output ports, and a shared random access memory coupled to the input ports and output ports by data transport logic. Two network switches may go through a login procedure to determine if virtual channels may be established on a link. A credit initialization procedure may be performed to establish the number of credits available to the virtual channels. Credit-based packet flow may then begin on the link. A credit synchronization procedure may be performed to prevent the loss of credits due to errors. On detecting certain error conditions, a virtual channel may be deactivated. In one embodiment, the link is a Gigabit Ethernet link, and the packets are Gigabit Ethernet packets. The packets may encapsulate storage format (e.g. Fiber Channel) frames.

Cellular signals or other wireless signals/messages are introduced into a building or to an outside location by transmitting packets corresponding to those signals over a data network and low cost cables to designated locations within the data network. Once the designated packets containing the signals reach the destination, they are then broadcast over the air to a terminal capable of receiving the wireless message. In a first embodiment, an in-building gigabit Ethernet network, such as that currently existing presently in many buildings, is used to distribute radio signals indoors. Instead of transmitting the radio signals over the air from a repeater connected to a base station, coded baseband signals generated by the coding processor (e.g., a CDMA Modem Unit) in the base station are packetized and sent over the Ethernet network to radio processing equipment and antennas distributed throughout the building. The radio processing equipment strips the packet headers from the baseband signal packets so those signals can be broadcast via the antennas to one or more mobile terminals.

Cellular signals or other wireless signals/messages are introduced into a building or to an outside location by transmitting packets corresponding to those signals over a data network and low cost cables to designated locations within the data network. Once the designated packets containing the signals reach the destination, they are then broadcast over the air to a terminal capable of receiving the wireless message. In a first embodiment, an in-building gigabit Ethernet network, such as that currently existing presently in many buildings, is used to distribute radio signals indoors. Instead of transmitting the radio signals over the air from a repeater connected to a base station, coded baseband signals generated by the coding processor (e.g., a CDMA Modem Unit) in the base station are packetized and sent over the Ethernet network to radio processing equipment and antennas distributed throughout the building. The radio processing equipment strips the packet headers from the baseband signal packets so those signals can be broadcast via the antennas to one or more mobile terminals. Additionally, hard handoff is employable upon entering a building using specifically configured pilot signals.

A network tap device that is configured for operation in a copper Gigabit Ethernet communications network using a power-over-Ethernet (“POE”) electrical supply is disclosed. In one embodiment, a network tap device powered by a POE supply is disclosed, comprising first and second network ports that are configured with receptacles for receiving communication cables. The communication cables are configured to carry both data signals and the POE supply to and from the network tap device. The network tap device further includes first and second tap ports that connect with additional communication cables to a monitoring device. The network tap device also includes control and regulation circuitry that is configured to receive the POE supply from the communication cables via the network ports and to enable components of the network tap device to be operated by the POE supply.

A method for analyzing Gigabit Ethernet (GBE) and fiber channel protocol communications is provided which provides a more detailed understanding of the errors, than that provided under the IEEE 802.3z standard. The method creates an additional parity error signal which is not specified under the IEEE 802.3z standard. The parity error signals and IEEE 802.3z invalid code word signals are used to provide an analysis of whether the underlying communication errors are a result of 8B/10B coding word errors or running disparity errors. A system and apparatus to monitor performance in accordance with the above-mentioned method is also provided.

Aspects of the invention for managing power in a single chip device may comprise, an internal finite state machine that, while in a communicating state, determines from within the single chip device whether a power management status is set and/or whether a first power management event is received. If the power management status is set, the finite state machine may transition from the communicating state to a power management event sent state. If the first power management event is received, the finite state machine may transition from the communicating state to a non-communicating state. The first power management event may be a turn off power management event. Furthermore, in instances where the power management status is set, it may be cleared, thereby causing the finite state machine to transition back to the communicating state. One or more power management control registers may be utilized for indicating power management status.

A gigabit Ethernet adapter provides a provides a low-cost, low-power, easily manufacturable, small form-factor network access module which has a low memory demand and provides a highly efficient protocol decode. The invention comprises a hardware-integrated system that both decodes multiple network protocols byte-streaming manner concurrently and processes packet data in one pass, thereby reducing system memory and form factor requirements, while also eliminating software CPU overhead. A preferred embodiment of the invention comprises a plurality of protocol state machines that decode network protocols such as TCP, IP, User Datagram Protocol (UDP), PPP, Raw Socket, RARP, ICMP, IGMP, iSCSI, RDMA, and FCIP concurrently as each byte is received. Each protocol handler parses, interprets, and strips header information immediately from the packet, requiring no intermediate memory. The invention provides an internet tuner core, peripherals, and external interfaces. A network stack processes, generates and receives network packets. An internal programmable processor controls the network stack and handles any other types of ICMP packets, IGMP packets, or packets corresponding to other protocols not supported directly by dedicated hardware. A virtual memory manager is implemented in optimized, hardwired logic. The virtual memory manager allows the use of a virtual number of network connections which is limited only by the amount of internal and external memory available.

An Ethernet architecture is provided for connecting a computer system or other network entity to a dedicated Ethernet network medium. The network interface enables the transmission and receipt of data by striping individual Ethernet frames across a plurality of logical channels and may thus operate at substantially the sum of the individual channel rates. Each channel may be conveyed by a separate conductor (e.g., in a bundle) or the channels may be carried simultaneously on a shared medium (e.g., an electrical or optical conductor that employs a form of multiplexing). On a sending station, a distributor within the sender's network interface receives Ethernet frames (e.g., from a MAC) and distributes frame bytes in a round-robin fashion on the plurality of channels. Each “mini-frame” is separately framed and encoded for transmission across its channel. On a receiving station, the receiver's network interface includes a collector for collecting the multiple mini-frames (e.g., after decoding) and reconstructing the frame's byte stream (e.g., for transfer to the receiver's MAC). The first and last bytes of each frame and mini-frame are marked for ease of recognition. Multiple unique idle symbols may be employed for transmission during inter-packet gaps to facilitate the collector's synchronization of the multiple channels and/or enhance error detection. A maximum channel skew is specified, and each received channel may be buffered with an elasticity that is proportional to the maximum skew so that significant propagation delay may be encountered between channels without disrupting communications.

The present invention provides for a method and protocol for high bandwidth, low-latency and reliable transfer of variable length FC Frames over the Gigabit Ethernet.

A method and apparatus for transferring data between IP devices (including, but not limited to, Gigabit Ethernet devices) and SCSI or Fibre Channel devices. The device interfaces may be either SCSI, Fibre Channel or IP interfaces such as Gigabit Ethernet. Data is switched between SCSI and IP, Fibre Channel and IP, or between SCSI and Fibre Channel. Data can also be switched from SCSI to SCSI, IP to IP and FC to FC. The port interfaces provide the conversion from the input frame format to an internal frame format, which can be routed within the apparatus. The amount of processing performed by each port interface is dependent on the interface type. The processing capabilities of the present invention permit rapid transfer of information packets between multiple interfaces at latency levels meeting the stringent requirements for storage protocols. The configuration control can be applied to each port on a switch and, in turn, each switch on the network, via an SNMP or Web-based interface, providing a flexible, programmable control for the apparatus.

The invention discloses a satellite-borne electronic equipment comprehensive management and control system and aims to provides the satellite-borne electronic equipment comprehensive management and control system which is high in integration, stable and reliable and capable of reducing a device number and redundant remote measurement and remote control interfaces. According to the technical field, each module in a comprehensive management and control unite and a comprehensive service unit is connected to a 1553B bus through a board-level management controller in the module so as to carry out data monitoring and instruction data transmission; by means of a J599 type connector, the comprehensive service unit realizes external gigabit Ethernet data communication among units and management and control data isolation and interaction; the comprehensive management and control unite receives platform remote control, time and attitude information and sends remote measurement and data transmission data through a management and control duty module; and the comprehensive management and control unite is configured to X1 or X4 mode through a Rapid IO management module, and a Rapid IO network topological structure in the unit is configured to a single satellite or double mode through the Rapid IO management module.

Gang migration refers to the simultaneous live migration of multiple Virtual Machines (VMs) from one set of physical machines to another in response to events such as load spikes and imminent failures. Gang migration generates a large volume of network traffic and can overload the core network links and switches in a datacenter. In this paper, we present an approach to reduce the network overhead of gang migration using global deduplication (GMGD). GMGD identifies and eliminates the retransmission of duplicate memory pages among VMs running on multiple physical machines in the cluster. The design, implementation and evaluation of a GMGD prototype is described using QEMU/KVM VMs. Evaluations on a 30-node Gigabit Ethernet cluster having 10 GigE core links shows that GMGD can reduce the network traffic on core links by up to 65% and the total migration time of VMs by up to 42% when compared to the default migration technique in QEMU/KVM. Furthermore, GMGD has a smaller adverse performance impact on network-bound applications.

A data processing system includes compute nodes, at least one metadata server, iSCSI storage access servers, and data storage devices. The metadata server services requests from the compute nodes for file mapping information identifying iSCSI LUNs and logical blocks of file data. The storage access servers service iSCSI I/O requests from the compute nodes, and report server loading to the metadata server. A Gigabit Ethernet IP network transfers read and write data between the compute nodes and the storage access servers. The storage access servers are linked to the data storage devices for parallel access to iSCSI LUNs of the file data in the data storage devices. The metadata server is programmed for server load balancing by indicating to the compute nodes respective ones of the storage access servers that should be used for access to the iSCSI LUNs.

The invention discloses a VPX parallel DSP (Digital Signal Processing) board card based on SoC (System on a Chip) online reconstruction. An FPGA (Field Programmable Gate Array) chip is used as a board stage SoC controller; and two DSP chips are used as core operation chips of a DSP board card. During the practical configuration of the DSP chips, the FPGA chip used as the SoC controller can complete the dynamic re-configuration of work code by GE (Gigabit Ethernet) through the hardware resetting on the DSP and the switching on the starting mode; and the flexibility and the real-time performance during the DSP are greatly improved. The DSP chips receive two kinds of high-speed serial bus signals of SRIO (Serial Rapid Input Output) X4 and the GE transmitted through a VPX interface, repacking the transferred PCIE (Peripheral Component Interface Express) X2 high-speed serial bus signal through a PCIE exchange chip, and receives a data signal to be processed and a control instruction; or the DSP chips receive the GE protocol signal of a peripheral component through an RJ45 net port.

A transmission apparatus is disclosed, which performs positive/negative stuffing with 8-bit/10-bit (8B/10B) codes being kept intact while retaining the normality of 8B/10B codes and the continuity of running disparity (RD) without termination of 8B/10B codes of a plurality of Gigabit Ethernet (GbE) signals received. The apparatus then executes multiplexing and separation after synchronization of the plurality of signals, thereby achieving the “transparent” transport of management information which is contained in the 8B10B codes between user devices.

A community network system with broadband integrated services includes video servers, video storages, video conference servers, satellite digital television receiver servers, a network accounting server, a network management server, Gigabit Ethernet Switches, Fast Ethernet switches, home gateways, wireless gateways, digital television sets, analogue television sets, computers, PCs with wireless interface, stationary IP telephones, and wireless IP mobile phones. The IP stationary phone can be connected between the Fast Ethernet switch and the home gateway, and also can be connected between the home gateway and the computer. The wireless gateway is connected to the mobile phone and a mobile device. The satellite digital television receiver server is connected to a satellite signal receiver antenna. The backbone Gigabit Ethernet Switch is connected to a Metropolitan Area Network via a 1000 Mbps or 100 Mbps port. The system simultaneously provides the services of digital television, Internet access of the computer and IP telephone. The present invention achieves the service integration of television network, telephone network and computer network, and the integration of wired and wireless networks, and ensures the qualities of various services, information security and reasonable accounting.

A mateable pair of Ethernet connector assemblies for propagating data at Gigabit rates is disclosed. The pair of electrical connector assemblies includes a male Ethernet plug and a female Ethernet receptacle. The male Ethernet plug includes a substantially cylindrical hollow-body shell, an insulator body positioned within the shell, and a plurality of cylindrical pins positioned within respective apertures formed in the insulator body. One end of each pin extends beyond the mating surface of the insulator body for insertion into a respective socket of the female receptacle. The female Ethernet receptacle includes a substantially cylindrical hollow-body shell, an insulator body positioned within the receptacle shell, and a plurality of hollow-body cylindrical sockets positioned within respective apertures formed in the receptacle insulator body. One end of each socket is substantially flush with a mating surface of the receptacle insulator body for receiving a pin of the male Ethernet plug.

A computer system comprises host processor and a network interface, wherein the host processor includes resources supporting a full power mode, a lower power mode and a power down mode, as seen in standard system bus specifications such as PCI and InfiniBand. The network interface includes a medium interface unit coupled to network media supporting a least high speed protocol, such as a Gigabit Ethernet or high-speed InfiniBand, and a lower speed protocol, such as one of 10 Mb and 100 Mb Ethernet or a lower speed InfiniBand. Power management circuitry forces the medium interface unit to the lower speed protocol in response to an event signaling entry of the lower power mode. In the lower power mode, the network interface consumes less than the specified power when executing the lower speed protocol, and consumes greater than the specified power when executing the high speed protocol. Logic in the network interface operates in the lower power mode, and uses the lower speed protocol to detect a pattern in incoming packets. In response to the detection of said pattern, the logic issues a reset signal to the host processor. Thus, the network interface operates as a wake-up device in the lower power mode, using the lower speed protocol.

A single-usage network tap monitors network information flow over a particular connection. Instead of requiring a tap for each analytical device, by incorporating elements that regenerate, spread, and coordinate the timing of the signal, multiple, simultaneous, and parallel analytical devices can monitor a particular network connection through one tap, It incorporates four amplifiers preferably manufactured on the same IC die with high-impedance input terminals connected directly to the two conductors of a gigabit Ethernet local area network digital transmission line so as not to load or otherwise upset its impedance or other parameters. The output terminals of the operational amplifiers are connected to and match the input impedance of the digital transmission protocol Gigabit analyzer. The gain of the operational amplifiers is arranged so as to replicate at the input of the analyzer the signals appearing on the Gigabit local area network transmission line with uninterruptible power supply.

A gigabit ethernet line driver includes a transmitter having both transmitter and active hybrid outputs. The transmitter consists of a plurality of transmitter clusters each connected to both the transmitter and active hybrid outputs. Each transmitter cluster includes a plurality of transmitter cells consisting of a driver cell and digital to analog converter connected to driver cell. A hybrid circuit connects between the transmitter outputs and receiver inputs for separating a receiver signal from the transmitter signal responsive to a tuning signal.