514results about "Digital-analogue convertors" patented technology

Wireless circuitry may include a transmission line that carries a signal and a power detector that measures the signal. The detector may include a rectifier coupled to a comparator over a differential path. An offset calibrating digital-to-analog converter (OSDAC), a reference generator, and a multiplexer may be disposed on a negative line of the differential path. The OSDAC may produce an offset-compensated voltage by adding different offset voltages to a voltage on the second line over time. The reference generator may generate a set of threshold voltages by adding different reference voltages to the offset-compensated voltage. A temperature sensor may adjust the reference voltages used to generate the threshold voltages based on a temperature of the power detector. The multiplexer may route different threshold voltages to a negative input of the comparator.

The current-mode end-to-end signal path includes a digital-to-analog converter (DAC) operating in current mode and an upconverting mixer operating in current mode and operably coupled to the DAC, where analog inputs and analog outputs of the DAC and the upconverting mixer are represented as currents, and the DAC generates a baseband signal.

To provide a filter stage system.SOLUTION: A filter stage system includes a continuous time baseband filter comprising a feedback loop that employs at least one first impedance node and at least one second impedance node. The at least one first impedance node has a higher impedance than the at least one second impedance node. The at least one first impedance node provides a dominant pole, and the at least one second impedance node provides a non-dominant pole. The continuous time baseband filter generates a filtered current. The filter stage system also includes a mirroring component that mirrors the filtered current to an output.SELECTED DRAWING: Figure 2

The invention provides a digital-to-analog converter which comprises a first reference voltage node, a second reference voltage node, a plurality of change-over switches, a plurality of resistor units and a plurality of capacitor units, the resistor units and the capacitor units are sequentially connected in series to form a series circuit, and the plurality of change-over switches respectively receive multi-digit digital code values in digital signals and output first reference voltage or second reference voltage. And finally, an analog voltage signal is output through an output node of the digital-to-analog converter to realize digital-to-analog conversion, and meanwhile, capacitors in the capacitor units are connected in parallel between the two corresponding resistor network nodes and carry out rapid charging and discharging on the two resistor network nodes, so that the voltage switching efficiency of the resistor network nodes is improved, and the reliability of the digital-to-analog converter is improved. The delay in the digital signal transmission process is reduced, so that the purpose of reducing burrs is achieved, the digital-to-analog converter does not need to be additionally provided with a preprocessing module and a filter, the design cost is reduced, and the conversion efficiency is improved.

A filter stage system comprising a continuous-time baseband filter comprising a feedback loop employing at least one first impedance node and at least one second impedance node, wherein the at least one first impedance node has a higher impedance than the at least one second impedance node, and wherein the at least one first impedance node provides a dominant pole and the at least one second impedance node provides a non-dominant pole, and wherein the continuous-time baseband filter generates a filtered current, and a mirror component mirrors the filtered current to an output.

Systems and methods are related to a successive approximation analog to digital converter (SAR ADC). The SAR ADC includes a sample and digital to analog conversion (DAC) circuit configured to sample an input voltage, a comparator circuit coupled to the sample and DAC circuit and having an output, a first set of storage circuits, and a comparator driver. The comparator driver is disposed between the output and the first set of storage circuits. The first set of storage circuits are coupled to the comparator circuit and the sample and DAC circuit. The comparator driver can include a first driver and second driver. The first driver is coupled to a first input of a first storage circuit of the first set of storage circuits, and the second driver is coupled to first inputs of a second set of storage circuits within the first set of storage circuits.

The invention discloses a high-reliability three-dimensional integrated direct sampling software radio architecture radio frequency microsystem, which is based on a direct sampling software radio system architecture and a multi-layer glass-based TGV adapter plate wafer-level bonded POP three-dimensional stacked packaging architecture. A high-performance glass antenna, silicon-based single core particle Fan-in and Fan-out packaging, mixed multi-core particle integration of an embedded glass-based TGV adapter plate, mixed bonding integration of a silicon-based digital TSV adapter plate and the glass-based TGV adapter plate are combined, and a glass antenna, a direct sampling core particle, a silicon-based computing power circuit, a silicon-based storage circuit and a silicon-based interface circuit are integrated. And the three-dimensional heterogeneous integration of the microsystem is realized. According to the micro-system, a glass substrate is used as a main body packaging material, a radio frequency circuit and a digital-analog hybrid circuit are fused, three-dimensional heterogeneous integration from a glass antenna to a baseband storage and calculation integrated processing circuit is realized, and a complete integrated airtight packaging micro-system is formed and can cover a DC-20GHz frequency band.

The invention provides a vector signal source and a design method thereof, which can be applied to the technical field of communication. The vector signal source comprises: a generation module comprising a plurality of parallel direct digital synthesizers, the generation module being configured to generate a plurality of target digital signals based on drive clock signals corresponding to the plurality of direct digital synthesizers, the driving clock signals respectively corresponding to the plurality of direct digital synthesizers have phase differences relative to each other and are equal in frequency; the conversion module comprises a plurality of digital-to-analog converters electrically connected with the plurality of direct digital synthesizers respectively, and the conversion module is configured to convert the received multiple paths of target digital signals into multiple paths of target analog signals respectively based on sampling clock signals corresponding to the multiple digital-to-analog converters respectively, the sampling clock signals corresponding to the plurality of digital-to-analog converters are synchronized relative to each other; and the synthesis module is configured to integrate the multiple paths of target analog signals according to a time sequence to obtain a target vector signal source.

Embodiments disclosed herein relate to digital-to-analog converters (DACs), and more particularly, to architecture thereof for improving bit resolution of the DACs. In an embodiment, a circuit is provided that includes a first DAC sub-circuit, a second DAC sub-circuit, and a control circuit coupled to control the first and second DAC sub-circuits. The first DAC sub-circuit includes a first set of transistors and a first set of switches coupled to the first set of transistors and to output nodes. The second DAC sub-circuit includes a second set of transistors coupled to the first set of transistors and a second set of switches coupled to the second set of transistors and to the output nodes.

Novel solutions for calibration of a digital-to-analog converter (DAC). Some solutions allow for the calibration of a DAC without an isolation switch and / or calibration based on signal measurements taken at the output stage of a device comprising the DAC.

A nicotine delivery device (200) for generating a mist containing nicotine for inhalation by a user. The device comprises a mist generator device (201) and a driver device (202). The driver device (202) is configured to drive the mist generator device (201) at an optimum frequency to maximise the efficiency of mist generation by the mist generator device (201).

An interactive communication apparatus, which connects to a computer, comprises an interactive communication device, having a tag, that is removably placed on or adjacent to an interactive communication device holder, having a sensor, wherein the tag communicates information to the sensor. The interactive communication system enables a user to transfer, store or retrieve information about and / or to a person that is identified with that interactive communication device. Once the interactive communication device is placed on or adjacent to the interactive communication device holder, certain communication applications, which include, photo slideshow, chat, e-mails, music, videos, and RSS feed, launch. The user can terminate the applications by removing the interactive communication device from the interactive communication device holder. The user can access content related to a new person by placing another interactive communication device, that corresponds to the new person, on or adjacent to the interactive communication device holder.

A comparator circuit includes a matching capacitor in series with a first switching device and a second switching device. The first and second switching devices are in parallel between the matching capacitor and a reference voltage. The comparator circuit further includes a sampling capacitor in series with a third switching device and a fourth switching device. The third switching device is in series between the sampling capacitor and a DAC, and the fourth switching device is in series between the sampling capacitor an input voltage. The comparator circuit further includes a comparator having an inverting input terminal and a non-inverting input terminal. The inverting input terminal is capacitively coupled to the matching capacitor and the non-inverting input terminal is capacitively coupled to the sampling capacitor. The comparator circuit further includes a fifth switching device and a sixth switching device in series between the matching capacitor and the sampling capacitor.

The invention discloses a digital-to-analog converter interface circuit supporting LVDS / CMOS dual-mode input. The digital-to-analog converter interface circuit comprises an ESD protection circuit, a DEMUX multiplexer, an MUX multiplexer, an LVDS receiver, an inverter chain and a digital logic circuit. The output end of the ESD protection circuit is connected with the DEMUX demultiplexer; the digital logic circuit is used for generating a synchronous control signal according to an external mode switching signal and coordinating the working state of each module; the DEMUX demultiplexer distributes an input signal output by the ESD protection circuit to a corresponding signal processing path under the action of a control signal output by the digital logic circuit; the LVDS receiver receives the LVDS signal, converts the LVDS signal into a single-ended CMOS signal, and outputs the single-ended CMOS signal to the MUX multiplexer; the inverter chain is used for receiving a CMOS signal; and the MUX multiplexer outputs a control signal according to the digital logic circuit, so that one of the two paths of input signals is selected to be output to the DAC core circuit. According to the invention, LVDS / CMOS dual-mode input is efficiently supported in a single chip, and meanwhile, the requirements of high speed, low power consumption and time sequence consistency are met.

In one example, a method comprises determining a bias voltage in response to a change in operating temperature of an array of non-volatile memory cells, each of the non-volatile memory cells in the array of memory cells comprising a control gate terminal and an erase gate terminal; and applying the bias voltage to a control gate terminal and an erase gate terminal of a selected memory cell in the array of memory cells while reading the selected memory cell.

Provided are a time-interleaved digital-to-analog converter and an electronic device. The time-interleaved digital-to-analog converter comprises: a multi-channel sub-digital-to-analog converter, configured to provide outputs of multiple initial sampling rates; a mode control encoder, configured to generate a mode control code and send the mode control code to a multiplexer, so as to control a configuration mode of the multiplexer by means of the mode control code; and the multiplexer, connected to the multi-channel sub-digital-to-analog converter, and configured to determine, on the basis of the mode control code and the outputs of the multiple initial sampling rates, an output of a target sampling rate corresponding to the digital-to-analog converter, and determine an output path corresponding to the output of the target sampling rate, wherein the target sampling rate is greater than or equal to the initial sampling rates.

This application provides a voltage conversion circuit and electronic device, including: a controller, a terminating resistor, a plurality of first resistors, a plurality of second resistors, and a plurality of control switches. The first end of the terminating resistor is grounded; the first resistors are connected in series, and the first end of the first first resistor is connected to the second end of the terminating resistor; the first end of one second resistor is connected to the first end of the first first resistor, and the first end of each of the other second resistors is connected to the second end of the first resistor respectively; the first end of each control switch is connected to the second end of one of the second resistors respectively, and the second end of the control switch is connected to or grounded to a preset reference voltage according to a control signal sent by the controller; one of the plurality of control switches is set as a modulation switch, which is used to receive a modulation signal sent by the controller, and both the modulation switch and the modulation signal are determined based on nonlinear error.

Embodiments of the present application relate to analog-to-digital converter decision control. An analog-to-digital converter (ADC) (100) includes a capacitive digital-to-analog converter (CDAC) (102), a comparator (106), and a successive approximation register (SAR) control circuit (108). The comparator (106) is coupled to an output of the CDAC (102). The SAR control circuit (108) is coupled to an output of the comparator (106) and an input of the CDAC. The SAR control circuit (108) includes a flip-flop. The flip-flop includes a clock input terminal, a data input terminal, and an output. The clock input terminal is coupled to the output of the comparator. The data input terminal is coupled to a constant voltage source. The flip-flop can include an enable input terminal coupled to a SAR state circuit. The output is coupled to the CDAC (102).

The present invention relates to a data driver and a display apparatus including the same. The data driver includes a digital-to-analog converter, a buffer, and a buffer controller. The digital-to-analog converter is configured to receive a data signal having a digital type and convert the data signal into a data voltage having an analog type. The buffer is configured to buffer the data voltage and output the data voltage. The buffer controller is configured to determine a parameter of the buffer based on previous line data of the data signal and current line data of the data signal.

The application discloses a kind of synchronization methods of multi-channel high-speed digital-analog conversion module, comprising: reference clock source generates reference clock;Trigger controller generates trigger signal, trigger signal is used to inform each DAC board to start the digital quantity transmission of new waveform;Master chip PLL is multiplied to preset operating frequency by reference clock, and the feedback path of master chip PLL is removed to DAC board, and the delay of voltage-controlled oscillator output master chip IO's wiring is consistent and position is close;DAC PLL is multiplied to the sampling clock frequency of DAC by reference clock, and the output phase of DAC PLL can be adjusted, to ensure the timing margin when DAC reads digital quantity;Master chip is triggered under trigger signal, and at preset time, the digital quantity of several waveforms to be converted is sent to DAC by isochronous transmission path, and DAC converts digital quantity into analog waveform, realizes that all DAC completes digital quantity to analog quantity conversion at the same time, and realizes the high-precision synchronous conversion of DAC.

The utility model discloses a DAC signal conversion circuit of a DC motor, and belongs to the technical field of motor driving. The circuit comprises a power supply voltage conversion module, an integration unit, a voltage follower module and an analog voltage output module. The output end of the power supply voltage conversion module is connected with the input end of the integration unit, the output end of the integration unit is connected with the input end of the voltage follower module, and the output end of the voltage follower module is connected with the input end of the analog voltage output module; and the voltage follower module is used for isolating the output end of the integration unit from the input end of the analog voltage output module. The DAC signal conversion circuit of the DC motor provided by the utility model realizes an efficient and accurate conversion process from a PWM signal to an analog voltage signal, significantly improves the level conversion and response speed, can flexibly control the output amplitude and stability of the analog voltage signal, has the advantages of simple structure, low cost, high reliability, etc. The method can be widely applied to various fields.

The present disclosure relates to a circuit and method for calibrating a digital-to-analog converter. A digital-to-analog converter (DAC) calibration system includes a DAC configured to convert a digital input to an analog input, a detector configured to measure analog outputs of the plurality of DAC unit cells and combine the analog outputs to generate a total analog output signal, and a calibration engine. The calibration engine is configured to calibrate the DAC.

A semiconductor device comprising at least one transmit path is provided. The transmit path comprises an input node for receiving a digital baseband signal. Further, the transmit path comprises digital mixer circuitry coupled to the input node and configured to generate an upconverted digital baseband signal by upconverting a frequency of the digital baseband signal. Additionally, the transmit path comprises Digital-to-Analog Converter (DAC) circuitry coupled to the digital mixer circuitry and configured to generate an analog radio frequency signal based on the upconverted digital baseband signal. The transmit path comprises first analog mixer circuitry coupleable to an output of the DAC circuitry, and second analog mixer circuitry coupleable to the output of the DAC circuitry. Further, the transmit path comprises a first output node coupleable to an output of the first analog mixer circuitry, and a second output node coupleable to an output of the second analog mixer circuitry.

A neural network circuit is described that includes a first sample-and-hold circuit, a reference voltage generation circuit, a first comparator circuit, and a first output circuit. The first sample-and-hold circuit generates a first analog voltage based on a first output current output by a first neural network computation array. The reference voltage generation circuit generates a reference voltage based on a first control signal. The first comparator circuit is connected to the first sample-and-hold circuit and the reference voltage generation circuit, and outputs a first level signal based on the first analog voltage and the reference voltage. The first output circuit samples the first level signal based on a second control signal, and outputs a first computation result that meets the first computation precision.

The present disclosure relates to a digital-to-analog conversion device and method with signal calibration mechanism. A digital-to-analog conversion device with signal calibration mechanism. A first conversion circuit generates a first analog signal to an echo path according to an input digital signal. A second conversion circuit generates a second analog signal to the echo path according to the input digital signal and a pseudo noise digital signal. An echo transmission circuit processes the signals of the echo path to generate an echo signal. First and second calibration circuits generate first and second calibration signals. A calibration parameter operation circuit operates according to a difference between the echo signal and the first and second calibration signals and related path information to generate first and second offset values. The first and second calibration circuits make the first and second response coefficients converge according to the echo signal, and update first and second code word offset tables according to the first and second offset values.

The invention belongs to the technical field of EMI (Electro-Magnetic Interference) suppression, and relates to an EMI filtering method based on dual-frequency spread spectrum and dual-frequency recombination common-mode noise cancellation waveform, which comprises the following steps of: selecting a frequency as a composition frequency; enabling the EUT to work normally by taking a selected frequency as a switching PWM frequency, and obtaining common-mode noise amplitude data of multiple times of the frequency; acquiring a common-mode voltage amplitude, and calculating an amplitude transformation ratio and an amplitude of an injected offset waveform; acquiring a common-mode voltage amplitude, and calculating the phase of the injected offset waveform; injection offset waveform data is obtained through calculation, and the common-mode voltage is offset; according to the invention, common-mode noise is taken as a main scene, and common-mode suppression can be realized while the size is reduced.

A self-calibration digital-to-analog converter (DAC) and a calibration method for DAC are provided. The circuit includes a resistor circuit, a buffer amplifier, a fine-tuning circuit, and a correction switching circuit. In normal operation mode, the resistor circuit receives the common voltage for conversion. In correction mode, the circuit performs self-correction in a sampling time and a comparison time. During the sampling time, the resistor circuit receives the reference voltage and first correction data, and the buffer amplifier input samples the voltage. During the comparison time, the resistor circuit receives the common connection voltage and second correction data, and the fine-tuning circuit adjusts the correction data until the buffer amplifier output voltage flips and records the correction value corresponding to the second correction data. With this self-correction mechanism, the circuit can output theoretically correct digital-to-analog conversion results under the reference voltage and common connection voltage.

An example digital-to-analog converter (DAC) circuit may comprise a plurality of single-bit DAC elements, an encoder circuit, and a multiplexer circuit. The encoder circuit may be configured to generate a control signal, where a number of asserted bits in the control signal is based at least in part on a digital input signal and an asserted bit pattern of the control signal is based at least in part on a random signal. The multiplexer circuit may be configured to modify the control signal to generate a noise-corrected control signal having a noise-corrected bit pattern. The noise-corrected bit pattern may direct a first asserted bit of the noise-corrected control signal to activate a first single-bit DAC element and a second asserted bit of the noise-corrected control signal to activate a second single-bit DAC element, where the first single-bit DAC element and the second single-bit DAC element having respective errors that at least partially cancel.

A delta sigma type ADC (1) is provided with a quantizer (30) operating at a prescribed sampling frequency (fs), an FIR filter (40) connected to the quantizer (30), and a DAC (50). A feedback path for the quantizer (30) is structured by the FIR filter (40) and the DAC (50). A reference signal for the DAC (50) is supplied from a reference signal source (60) chopping at a frequency lower than the prescribed sampling frequency (fs).