1219results about "Digital-analogue convertors" patented technology

Certain aspects of the present disclosure provide a digital-to-analog converter (DAC) circuit. The DAC circuit generally includes: a decoder coupled to an input of the DAC circuit and current-steering cells coupled to an output of the decoder. Outputs of the current-steering cells may be coupled to a positive output node and a negative output node of the DAC circuit. The DAC circuit may also include an offset detection circuit including: a comparator having a first input and a second input selectively coupled to the positive output node and the negative output node; and a digital controller having an input coupled to an output of the comparator and an output coupled to the decoder. In some aspects, the DAC circuit includes one or more calibration DACs coupled to the offset detection circuit.

The invention relates to a method and a system for cyclically generating a high-speed waveform signal. The method comprises the following steps of: cyclically splicing waveform data by a waveform circulation module; the control module transmits a variable related to the waveform length to the waveform circulation module; the data storage module stores waveform data information; the waveform circulation module comprises an address circulation module which is responsible for data addressing and outputting a data address to a data storage module; the data circulation module receives the waveform data sent by the data storage module, completes circulation splicing of the data and sends the data to the data transmission interface, and the data transmission interface sends the waveform circulation data to the DAC. The waveform data length can be effectively reduced, and the requirement for the storage space is lowered; the method is suitable for any high-speed DAC (Digital-to-Analog Converter) using a JESD204 protocol interface, and can run most FPGA models of Xilinx JESD204 IP; the device can be adapted to an FPGA on-chip storage resource BRAM, and can also be adapted to an off-chip storage resource DDR and other devices; waveform circulation can be achieved according to needs, waveform infinite circulation can be completed, and circulation of specific times can also be completed.

The invention discloses a multi-channel analog-to-digital converter for multi-channel frequency division multiplexing and a conversion circuit and method thereof, and the frequency division multiplexing multi-channel analog-to-digital conversion circuit comprises an analog frequency conversion module which is used for receiving N paths of modulation clock signals, and generating N paths of modulation clock signals according to the modulation clock signals, n paths of input signals are modulated to preset frequencies of the input signals respectively, and N paths of modulation signals are obtained; wherein N is greater than or equal to 2, and N is a positive integer; the frequency bands where the N paths of modulation signals are located are not overlapped; the analog adder is used for combining the N paths of modulation signals to obtain one path of analog signal; the input end of the analog-digital conversion module is connected with the analog-digital conversion module; the digital logic control module is used for receiving the N paths of modulation clock signals and separating the digital signals into N paths of digital signals which are output in parallel. Multi-channel analog-to-digital conversion can be realized by adopting one analog-to-digital converter, the hardware volume, cost and power consumption can be reduced, and the analog-to-digital conversion rate and precision can be improved.

Methods and apparatus for sharing digital-to-analog (DAC) converters in a reconfigurable DAC circuit to support two or more transmit chains of a wireless transmitter configured for different radio access technologies (RATs) and / or different transmitter architectures. One example DAC circuit generally includes at least four DACs and a plurality of switches coupled to outputs of the at least four DACs such that the DAC circuit is configured as a multi-channel DAC circuit with at least four channels for a first set of one or more frequency bands and as an interleaved DAC circuit with at least two channels for a second set of one or more frequency bands different from the first set of frequency bands.

The invention provides an arbitrary waveform generator multi-chip DAC synchronization system, a delay adjustment module comprises an FPGA chip, an integrated clock management chip and a plurality of DAC chips, and the FPGA chip provides digital signals needing to be converted into analog waveforms for the DAC chips and sends parameter configuration signals to the integrated clock management chip and the DAC chips; the integrated clock management chip generates a reference clock, generates a sampling clock based on the reference clock, distributes the sampling clock to the DAC chip and the FPGA chip, and distributes a synchronization signal to the DAC chip; the multiple DAC chips are all configured to be slave chips to form multiple paths of arbitrary waveform generator output channels, digital signals are synchronously converted into analog signals, the analog signals are processed by a conditioning circuit and then output, the circuit structure of the system is remarkably simplified, synchronization of the multiple DAC chips can be achieved only through one integrated clock management chip, and the system is simple in structure, convenient to use and high in practicability. In addition, delay adjustment between DAC chips can be flexibly achieved, calibration or alignment of circuits and devices is not needed, and good application effects are achieved.

A high-speed transmitter system is disclosed that uses a supply-controlled serialization stage embedded in a PMOS output stage. In some embodiments, the transmitter includes a serialization circuit configured to convert parallel data to serial data by one or more serialization stages, a logic circuit configured to connect each input of the last stage of the one or more serialization stages of the serialization circuit to a respective dedicated output stage of an output circuit via respective logic functions, and an output circuit configured to implement an output stage to generate a signal using PMOS transistors based on the received input. Also, the logic circuit is connected to a low-voltage power supply, whereby its output can be adjusted to be close to the switching point of a PMOS-based gm stage so as to accelerate the operation of the transmitter.

The invention provides a current steering DAC circuit and electronic equipment, a current source array of the circuit sends differential current signals to a normal phase input end and an inverted phase input end of a fully differential transimpedance amplification module based on digital code control signals, and a common mode voltage adjusting end of the fully differential transimpedance amplification module receives set voltage. A normal phase input end and an inverted phase input end of the current translation module are respectively coupled to a normal phase output end and an inverted phase output end through a first resistor and a second resistor, and a first end and a second end of the current translation module are respectively coupled to the normal phase input end and the inverted phase input end. According to the invention, the first current and the second current received by the normal-phase input end and the inverted-phase input end are controlled to take 0 as the center, so that the minimum value of the voltage of the differential voltage signal output by the current-steering DAC is reduced; a differential voltage signal is output based on the voltage generated when the current of the differential current signal flows through the first resistor and the second resistor, and the maximum value of the voltage of the differential voltage signal output by the current steering DAC is increased.

A sensor including at least one sensor element configured for measuring an external parameter and outputting one or more results representative for the external parameter, an output buffer configured for receiving the one or more results or a processed version thereof and for applying an analog signal representative for the result or a time multiplexed sequence of analog signals representative for the results on a sensor terminal, and a control circuit configured for obtaining an ID of the sensor, and for receiving a trigger signal, and for determining whether the trigger signal matches the ID of the sensor, and for enabling the output buffer during a predefined period when the trigger signal matches the ID of the sensor.

Some embodiments of the present disclosure include a digital-to-analog conversion system configured to reduce inter-symbol interference (ISI) in high-speed continuous-time DACs. The system can include a main DAC with multiple sub-DACs, each configured to process a portion of a digital input sequence and generate part of an output waveform. To address ISI errors introduced by the sub-DACs, the system can include an ISI mitigation feedback loop. The ISI mitigation feedback loop can include an analog-to-digital converter (ADC) that generates a digital sequence from the output waveform and an analog correction signal generated by a correction DAC. A fractional decimation filter can be used to adjust a sampling rate and attenuate high-frequency components. A digital error estimator can generate an error cancellation sequence by correlating encoder information with the input sequence. The correction DAC can use the error cancellation sequence to generate the analog correction signal.

Methods and apparatus for filtering a signal using a current mode filter circuit that enables source degradation. An example filter circuit generally includes an input node; an output node; a power supply node; a first transistor including a drain coupled with the input node; a second transistor including a drain coupled with the output node and including a gate coupled with a gate of the first transistor; a capacitive element coupled between a drain of the first transistor and the power supply node; a first resistive element coupled between the drain electrode and the gate electrode of the first transistor; a first source degeneration element coupled between a source of the first transistor and the power supply node; and a second source degeneration element coupled between a source of the second transistor and the power supply node.

The invention discloses a communication method for an optical chip high-precision voltage source matrix and an MCU control loop. The communication method comprises the following steps that S1, an MCU module establishes communication connection with an I2C expander through an I2C bus; s2, the MCU sends a chip selection control instruction to the I2C expander, and a plurality of chip selection signals are activated; s3, the MCU sends voltage setting data through the SPI bus; s4, converting the digital signal into an analog voltage signal by adopting an error compensation algorithm based on fractional order Kalman filtering; s5, optimizing the voltage balance based on a jellyfish search optimization algorithm; s6, adjusting the internal working state of the optical chip, and feeding back the running state information to the MCU module; s7, dynamically adjusting a chip selection signal of the I2C expander by the MCU module; and S8, the MCU module monitors abnormal signal interference possibly occurring in the communication process of the I2C and the SPI in real time. According to the invention, a digital-to-analog conversion technology, a communication interface technology and a communication error monitoring and correction technology are combined, so that communication between the high-precision voltage source matrix and the MCU control loop is realized.

A device includes a plurality of digital-to-analog converters (DACs), a multiplexer, a plurality of electrodes including a first electrode, and a plurality of direct current (DC) offset circuits including a first DC offset circuit. At least one of the plurality of electrodes is located along a lane for movement of an ion. The multiplexer has multiple inputs coupled to the plurality of DACs and multiple outputs including a first output. The first output is configured to provide a first voltage. The first DC offset circuit is coupled between the first output and the first electrode. The first DC offset circuit is configured to add a first DC offset voltage to either the first voltage or the first voltage amplified by a first gain. The first DC offset voltage is configurable.

A DC electronic load circuit relates to the technical field of electronic load control. The utility model provides a direct current electronic load circuit which integrates a dissipation MOS tube array, an analog PID loop, a digital integrated control module, a bus electrical parameter sampling and processing module and a WiFi communication module, and realizes a plurality of working modes such as constant current, constant voltage, constant resistance and constant power by accurately controlling the conduction degree of the MOS tube array. The system has the advantages of real-time monitoring, remote control, overvoltage and overcurrent protection, low power consumption design and the like, and an electronic load solution which is high in precision, high in stability and flexible to operate is provided, so that diversified test requirements are met, and the power supply test efficiency and safety are improved.

A high-speed transmitter system using a common mode controlled serialization stage embedded in an output stage is disclosed. In some embodiments, the transmitter includes a serialization circuit that is configured to convert parallel data into serial data with one or more serialization stages; a logic circuit that is configured to connect each input of a last stage of the one or more serialization stages of the serialization circuit, via a respective logic function, to a respective dedicated output stage of an output circuit; and the output circuit that is configured to implement output stages to generate a signal based on the received input using NMOS transistors. In addition, the logic circuit is configured to be a desired voltage value (e.g., the output circuit's common mode) such that a switching point of the NMOS gm stage can be decreased and the gm stage can be activated within a reduced time.

The invention belongs to the field of analog integrated circuit design, and particularly relates to a miniaturized high-precision non-binary R-2R DAC with digital correction. Non-binary characteristics are introduced by setting resistance values of bridge resistors RBm and RBm + 1, so that an LSB section is a binary weight section, and ISB and MSB are non-binary weight sections; therefore, the width-to-length ratios of the MOS tubes of the switches SWm + 1-SWm + i + j and SW1 are equal and do not need to be increased proportionally, the non-binary characteristic is further introduced by setting the switch on-resistance, the selection of the unit resistance R only needs to meet the matching precision of the LSB section, and the area of the switch resistor array is greatly reduced. Static errors in the ISB segment and the MSB segment are respectively corrected by using an OEM correction technology, only digital code redundancy between adjacent segments of the LSB segment, the ISB segment and the MSB segment needs to be obtained through measurement, redundant digital codes are removed by adjusting digital input codes of corresponding segments, and the m + n + k-1 bit binary DAC is obtained through calibration, so that the memory of a digital calibration algorithm is efficient, and the algorithm complexity is effectively reduced. According to the invention, the area of the DAC is obviously reduced while high precision is realized.

A circuit for driving digital-to-analog converter (DAC) comprising a serializer (110, 210) configured to combine multiple signals to one input signal to drive a forward inverter (311) coupled to a first node (A) with a first impedance in serial configuration and a first capacitance (C1) in shunt configuration. The circuit includes a chain of inverters (321, 322) coupled in series to transfer the input signal from the first node (A) to the fifth node based on a signal transfer function. The circuit further includes a feedback inverter (425) between the third node and the first node (A) to form a feedback loop with two inverters in the chain, adding peaking in the signal transfer function at the first node (A). A second feedback inverter (425) can be added between the fifth node and the third node to add peaking in the signal transfer function at the third node. The feedback inverter (425) is designed as a current-starved inverter in order to alleviate hot-carrier injection (HCI) aging of the transistors and add programmability in the peaking. The circuit includes a DAC switch coupled to the fifth node.

Apparatus, systems, and methods for systems and methods for data signal multiplexing may be provided. According to an aspect a method for data signal multiplexing may be provided. The method includes interleaving, by a first 4-to-1 (4:1) multiplexer (MUX), a first set of four analog signals received from a first group of 4 Digital-to-Analog Converters (DACs) to generate a first interleaved analog output. The method may further include interleaving, by a second 4:1 MUX, a second set of four analog signals received from a second group of 4 DACs to generate a second interleaved analog output. Each of the first and the second interleaved analog output may be based on a first 8-unit interval (UI) window including four consecutive 2 UI windows. The method may further include interleaving, by a 2:1 MUX, the first interleaved analog output and the second interleaved analog output to generate a combined interleaved analog output.

Disclosed is a high-speed transmitter system that uses a serialization stage embedded in an output stage and controlled in a common mode. In some of the plurality of embodiments, the transmitter includes a serialization circuit configured to convert parallel data into serial data using one or more serialization stages, a logic circuit configured to connect each of the inputs of the final stage of one or more serialization stages of the serialization circuit to respective dedicated output stages of an output circuit via respective logic functions, and an output circuit configured to implement an output stage to generate a signal based on a received input using NMOS transistors. Additionally, the logic circuit is configured to achieve a desired voltage value (such as the common mode of the output circuit), thereby making it possible to reduce the switching point of the gm stage of the NMOS and activate the gm stage within the reduced time.

The invention discloses a gain-dependent rapid hybrid direct current offset correction circuit, which comprises a direct current correction controller, a hybrid direct current offset corrector and a digital domain direct current offset corrector, the direct current offset correction controller is used for outputting a first control signal enable mix according to state information rxstate sent by a state controller of the zero intermediate frequency receiver so as to start the hybrid direct current offset corrector; the hybrid direct-current offset corrector is used for operating a hybrid direct-current offset correction algorithm to perform hybrid direct-current offset correction to obtain a correction code word when the first control signal enable signal is a first value; and the digital domain direct current offset corrector is used for operating a digital domain direct current offset correction algorithm when the first control signal enable mix signal is a second value, and performing digital domain direct current correction according to the correction code word. Compared with a traditional direct current offset correction method, the method provided by the invention has the characteristics that the correction speed is high, the correction precision is high, and the correction precision and the correction speed are not sensitive to the gain change of a receiver.

The invention provides a computing device and a computing chip, and belongs to the technical field of computers. The computing device can comprise a digital-to-analog conversion module, an analog computing module and an analog-to-digital conversion module. The digital-to-analog conversion module can be used for converting the mantissa part of the input floating-point number into an initial analog signal, and performing gain adjustment on the initial analog signal based on the exponent part of the input floating-point number to obtain an input analog signal; the analog calculation module can be used for performing analog calculation based on the input analog signal to obtain a calculation result analog signal; the analog-to-digital conversion module can be used for converting the calculation result analog signal into a result floating-point number. According to the calculation device, the input floating-point number is converted into the input analog signal, floating-point number calculation is carried out in an analog domain, and compared with floating-point number calculation in a digital domain, the calculation efficiency of floating-point calculation can be improved.

A high-speed transmitter system using a supply controlled serialization stage embedded in a PMOS output stage is disclosed. In some embodiments, the transmitter includes a serialization circuit that is configured to convert parallel data into serial data with one or more serialization stages; a logic circuit that is configured to connect each input of a last stage of the one or more serialization stages of the serialization circuit, via a respective logic function, to a respective dedicated output stage of an output circuit; and the output circuit that is configured to implement output stages to generate a signal based on the received input using PMOS transistors. In addition, the logic circuit is connected to a low voltage supply such that its output can be adjusted to be close to a switching point of the PMOS based gm stage to speed up transmitter operations.

The present disclosure provides DFE-based peaking techniques for high speed transmitters. A circuit for driving a digital-to-analog converter (DAC) includes a serializer configured to combine a plurality of signals into one input signal to drive a forward inverter coupled to a first node having a first impedance in a series configuration and a first capacitance in a shunt configuration. The circuit includes inverter chains coupled in series to transfer the input signal from the first node to a fifth node based on a signal transfer function. The circuit further includes a feedback inverter between a third node and the first node at which a peak in the signal transfer function is added to form a feedback loop having two inverters in the chain. A second feedback inverter may be added between the fifth node and the third node to add a peak in the signal transfer function at the third node.

The invention relates to a high-speed serial interface circuit, and discloses a linearity calibration and precision expansion method of a numerical control phase interpolator. According to the method, a digital delay converter (DDC) is cascaded behind a digital control phase interpolator (DPI), and delay compensation is carried out on an interpolated clock signal; sampling the compensated clock signal by using an analog-to-digital converter (ADC) to obtain a phase sampling value; the calibration control module calculates a phase error and generates a delay control word; when the numerical control phase interpolator DPI works, phase control words and delay control words are synchronously provided for corresponding modules, and linearity calibration and precision expansion are achieved. According to the method, a special detection circuit does not need to be added, hardware resources existing in a high-speed serial interface are utilized, the method can be achieved through simple digital control logic, the phase integral linearity is improved to be within 25 fs from 250 fs, meanwhile, the precision of an 8-bit phase interpolator is improved to be close to the 11-bit level, and the method is suitable for large-scale popularization and application. And the clock recovery performance and the data transmission reliability of the high-speed communication system are obviously improved.

Wireless circuitry may include a transmission line that carries a signal and a power detector that measures the signal. The detector may include a rectifier coupled to a comparator over a differential path. An offset calibrating digital-to-analog converter (OSDAC), a reference generator, and a multiplexer may be disposed on a negative line of the differential path. The OSDAC may produce an offset-compensated voltage by adding different offset voltages to a voltage on the second line over time. The reference generator may generate a set of threshold voltages by adding different reference voltages to the offset-compensated voltage. A temperature sensor may adjust the reference voltages used to generate the threshold voltages based on a temperature of the power detector. The multiplexer may route different threshold voltages to a negative input of the comparator.

A digital to analog converter (DAC) maps a digital word to an analog output. The DAC bits may have amplitude and timing errors. These errors (or sometimes referred herein as "non-idealities") result in distortion and degradation of the dynamic range in DACs. To reduce these negative effects, delta-sigma patterns can be provided to two bit cells, a reference bit cell and a bit cell under calibration, to perform, e.g., amplitude calibration and timing skew calibration. Delta-sigma patterns are particularly advantageous over square wave signals, which cannot be scaled to perform amplitude calibration between bit cells having different bit weights and are limited in frequency to integer fractions of the sampling clock.

A time-interleaved current-based digital-to-analog converter (current DAC) cell includes first input circuitry configured to receive a digital input signal, a first biasing voltage, a first clock, and a second clock. The first clock and the second clock having a phase offset from one another and having a common period. The current DAC also includes a first gate configured to, responsive to an ‘ON’ state of the first clock, pass the digital input signal to a second gate, the second gate being configured to, responsive to an ‘OFF’ state of the second clock, output a first DAC cell activation signal. The current DAC further includes first output circuitry configured to, responsive to the first DAC cell activation signal, output a first analog current signal based on (i) the digital input signal and (ii) the first biasing voltage.

The invention discloses an offset cancellation circuit, which comprises a signal conditioning unit used for processing an input signal and outputting a first current signal, an offset cancellation unit used for removing offset current in the first current signal and outputting a second current signal, and a signal processing unit used for processing the second current signal and eliminating offset voltage, the detuning elimination unit specifically comprises a chopper, a digital analog converter, a successive approximation register logic module and a comparator which are connected in sequence, and through multi-level detuning elimination, the precision of the whole circuit is improved, the processing capacity for weak signals is enhanced, the anti-interference capacity is improved, and noise is reduced; the method ensures the stability of long-time operation, and has a wide application prospect in the field of high-precision signal processing.

The current-mode end-to-end signal path includes a digital-to-analog converter (DAC) operating in current mode and an upconverting mixer operating in current mode and operably coupled to the DAC, where analog inputs and analog outputs of the DAC and the upconverting mixer are represented as currents, and the DAC generates a baseband signal.

To provide a filter stage system.SOLUTION: A filter stage system includes a continuous time baseband filter comprising a feedback loop that employs at least one first impedance node and at least one second impedance node. The at least one first impedance node has a higher impedance than the at least one second impedance node. The at least one first impedance node provides a dominant pole, and the at least one second impedance node provides a non-dominant pole. The continuous time baseband filter generates a filtered current. The filter stage system also includes a mirroring component that mirrors the filtered current to an output.SELECTED DRAWING: Figure 2

The invention provides a satellite-borne detection load data acquisition system. The satellite-borne detection load data acquisition system comprises an ADC conversion module, a DAC conversion module, a data processing module and a clock generation module, the ADC conversion module samples and converts the front-end radio frequency signal to be acquired into a high-speed digital signal, and outputs the high-speed digital signal to the rear-end FPGA unit in the form of 204B high-speed serial digital data; the DAC conversion module is used for converting the multiple paths of 204B high-speed serial digital signals into radio frequency modulation signals and outputting the radio frequency modulation signals to the outside; the clock generation module comprises a clock signal input unit, a clock jitter attenuator unit and a high-frequency PLL generation unit; and the matching circuit is arranged on an output link of the clock generation module so as to be compatible with various clock input interfaces. High-precision data signal acquisition can be carried out, the satellite-borne detection load data transmission requirement can be better met, and the system has the advantages that the size of a basic circuit board is smaller, the number of layout and wiring is smaller, and the system cost is low.