1721results about "Digital-analogue convertors" patented technology

The invention discloses a waveform synchronization method and device, and the method comprises the steps: firstly generating a dot frequency signal which has the same frequency with a low-frequency reference clock and is synchronous with the low-frequency reference clock after a system is started, feeding back the dot frequency signal in the form of a clock after passing through a signal link, carrying out the digital phase discrimination with the low-speed reference clock, and adjusting the delay of the signal link. And the feedback clock and the reference clock are aligned in phase, so that the certainty of signal link delay is realized. By adopting the thought similar to a phase-locked loop, the problems of uncertain time delay and non-synchronization between channels between the DAC and the FPGA interface can be solved under the condition that an ADC is not used for collecting a feedback waveform and carrying out complex correction calculation, the hardware complexity and cost of the system are remarkably reduced, and the digital phase discrimination speed and the calibration speed are high. In addition, the precision of delay calibration mainly depends on the establishment and retention time of the D trigger, and very high precision can be achieved. The invention also discloses synchronous waveform generation equipment.

A capacitor-less linear Low Drop Out (LDO) Voltage Regulating (VR) system and method with enhanced Power Supply Rejection (PSR), line transient response, and load transient response is disclosed. The system includes a current-summing amplifier to refine input voltage and error signals from an error amplifier circuit, improving regulation accuracy. Further, the system includes a Dynamic Current Bleeder (DCB) circuit to manage current flow, optimizing efficiency. Furthermore, a strategically placed compensation capacitor ensures stable voltage delivery despite load or input changes. To further enhance performance, a boost and reduce amplifier circuit continuously monitors and adjusts current of the error amplifier circuit, minimizing output voltage variations. The system effectively manages applications demanding highly regulated and stable voltage supplies.

Certain aspects of the present disclosure provide a digital-to-analog converter (DAC) circuit. The DAC circuit generally includes: a decoder coupled to an input of the DAC circuit and current-steering cells coupled to an output of the decoder. Outputs of the current-steering cells may be coupled to a positive output node and a negative output node of the DAC circuit. The DAC circuit may also include an offset detection circuit including: a comparator having a first input and a second input selectively coupled to the positive output node and the negative output node; and a digital controller having an input coupled to an output of the comparator and an output coupled to the decoder. In some aspects, the DAC circuit includes one or more calibration DACs coupled to the offset detection circuit.

Certain aspects of the present disclosure provide a digital-to-analog converter (DAC) circuit. The DAC circuit generally includes: a decoder coupled to an input of the DAC circuit and current-steering cells coupled to an output of the decoder. Outputs of the current-steering cells may be coupled to a positive output node and a negative output node of the DAC circuit. The DAC circuit may also include an offset detection circuit including: a comparator having a first input and a second input selectively coupled to the positive output node and the negative output node; and a digital controller having an input coupled to an output of the comparator and an output coupled to the decoder. In some aspects, the DAC circuit includes one or more calibration DACs coupled to the offset detection circuit.

The invention relates to a method and a system for cyclically generating a high-speed waveform signal. The method comprises the following steps of: cyclically splicing waveform data by a waveform circulation module; the control module transmits a variable related to the waveform length to the waveform circulation module; the data storage module stores waveform data information; the waveform circulation module comprises an address circulation module which is responsible for data addressing and outputting a data address to a data storage module; the data circulation module receives the waveform data sent by the data storage module, completes circulation splicing of the data and sends the data to the data transmission interface, and the data transmission interface sends the waveform circulation data to the DAC. The waveform data length can be effectively reduced, and the requirement for the storage space is lowered; the method is suitable for any high-speed DAC (Digital-to-Analog Converter) using a JESD204 protocol interface, and can run most FPGA models of Xilinx JESD204 IP; the device can be adapted to an FPGA on-chip storage resource BRAM, and can also be adapted to an off-chip storage resource DDR and other devices; waveform circulation can be achieved according to needs, waveform infinite circulation can be completed, and circulation of specific times can also be completed.

The invention discloses a multi-channel analog-to-digital converter for multi-channel frequency division multiplexing and a conversion circuit and method thereof, and the frequency division multiplexing multi-channel analog-to-digital conversion circuit comprises an analog frequency conversion module which is used for receiving N paths of modulation clock signals, and generating N paths of modulation clock signals according to the modulation clock signals, n paths of input signals are modulated to preset frequencies of the input signals respectively, and N paths of modulation signals are obtained; wherein N is greater than or equal to 2, and N is a positive integer; the frequency bands where the N paths of modulation signals are located are not overlapped; the analog adder is used for combining the N paths of modulation signals to obtain one path of analog signal; the input end of the analog-digital conversion module is connected with the analog-digital conversion module; the digital logic control module is used for receiving the N paths of modulation clock signals and separating the digital signals into N paths of digital signals which are output in parallel. Multi-channel analog-to-digital conversion can be realized by adopting one analog-to-digital converter, the hardware volume, cost and power consumption can be reduced, and the analog-to-digital conversion rate and precision can be improved.

Certain aspects of the present disclosure are directed to a radio frequency digital-to-analog converter (RFDAC). The RFDAC generally includes a plurality of digital-to-analog (DAC) unit cells. At least one DAC unit cell is capable of being configured in an active state or in a sleep state. For the at least one DAC unit cell, an output impedance of the DAC unit cell in the active state is equal to an output impedance of the DAC unit cell in the sleep state.

Systems and methods are related to a successive approximation analog to digital converter (SAR ADC). In one aspect, a method includes sampling, by a sample and digital to analog conversion (DAC) circuit, an input voltage to obtain a sampled voltage. The method also includes determining, by a comparator coupled to a set of storage circuits, a state of a plurality of bits corresponding to the sampled voltage. The comparator has a current parameter or voltage parameter adjusted based upon a conversion margin. Adjustment of the current parameter or the voltage parameter affects speed of determining the state of the bits. The method also includes storing the bits in the set of storage circuits. In some aspects, an SAR ADC is configured to perform the method.

Methods and apparatus for sharing digital-to-analog (DAC) converters in a reconfigurable DAC circuit to support two or more transmit chains of a wireless transmitter configured for different radio access technologies (RATs) and / or different transmitter architectures. One example DAC circuit generally includes at least four DACs and a plurality of switches coupled to outputs of the at least four DACs such that the DAC circuit is configured as a multi-channel DAC circuit with at least four channels for a first set of one or more frequency bands and as an interleaved DAC circuit with at least two channels for a second set of one or more frequency bands different from the first set of frequency bands.

The invention provides an arbitrary waveform generator multi-chip DAC synchronization system, a delay adjustment module comprises an FPGA chip, an integrated clock management chip and a plurality of DAC chips, and the FPGA chip provides digital signals needing to be converted into analog waveforms for the DAC chips and sends parameter configuration signals to the integrated clock management chip and the DAC chips; the integrated clock management chip generates a reference clock, generates a sampling clock based on the reference clock, distributes the sampling clock to the DAC chip and the FPGA chip, and distributes a synchronization signal to the DAC chip; the multiple DAC chips are all configured to be slave chips to form multiple paths of arbitrary waveform generator output channels, digital signals are synchronously converted into analog signals, the analog signals are processed by a conditioning circuit and then output, the circuit structure of the system is remarkably simplified, synchronization of the multiple DAC chips can be achieved only through one integrated clock management chip, and the system is simple in structure, convenient to use and high in practicability. In addition, delay adjustment between DAC chips can be flexibly achieved, calibration or alignment of circuits and devices is not needed, and good application effects are achieved.

A high-speed transmitter system is disclosed that uses a supply-controlled serialization stage embedded in a PMOS output stage. In some embodiments, the transmitter includes a serialization circuit configured to convert parallel data to serial data by one or more serialization stages, a logic circuit configured to connect each input of the last stage of the one or more serialization stages of the serialization circuit to a respective dedicated output stage of an output circuit via respective logic functions, and an output circuit configured to implement an output stage to generate a signal using PMOS transistors based on the received input. Also, the logic circuit is connected to a low-voltage power supply, whereby its output can be adjusted to be close to the switching point of a PMOS-based gm stage so as to accelerate the operation of the transmitter.

An analog-to-digital converter is provided. An analog-to-digital converter includes a comparator including a first input node receiving an output of a plurality of first unit capacitors and a second input node receiving an output of a plurality of second unit capacitors, a control logic configured to output first and second control signals on the basis of an output signal of the comparator, and a reference voltage adjustment circuit configured to adjust an output voltage provided to the comparator on the basis of the first and second control signals. The reference voltage adjustment circuit comprises a first pull-up circuit configured to apply a first reference voltage to each of the plurality of first unit capacitors and a first pull-down circuit configured to apply a second reference voltage to each of the plurality of second unit capacitors, based on v.

The invention provides a current steering DAC circuit and electronic equipment, a current source array of the circuit sends differential current signals to a normal phase input end and an inverted phase input end of a fully differential transimpedance amplification module based on digital code control signals, and a common mode voltage adjusting end of the fully differential transimpedance amplification module receives set voltage. A normal phase input end and an inverted phase input end of the current translation module are respectively coupled to a normal phase output end and an inverted phase output end through a first resistor and a second resistor, and a first end and a second end of the current translation module are respectively coupled to the normal phase input end and the inverted phase input end. According to the invention, the first current and the second current received by the normal-phase input end and the inverted-phase input end are controlled to take 0 as the center, so that the minimum value of the voltage of the differential voltage signal output by the current-steering DAC is reduced; a differential voltage signal is output based on the voltage generated when the current of the differential current signal flows through the first resistor and the second resistor, and the maximum value of the voltage of the differential voltage signal output by the current steering DAC is increased.

A high-speed transmitter system is disclosed that controls a serialization stage using a power supply embedded in a PMOS output stage. In some embodiments, a transmitter comprises: a serialization circuit configured to convert parallel data into serial data using one or more serialization stages; a logic circuit configured to connect each input of a last one of the one or more serialization stages of the serialization circuit to a respective dedicated output stage of the output circuit via a respective logic function; and an output circuit configured to implement an output stage using a PMOS transistor to generate a signal based on the received input. Further, the logic circuit is connected to the low voltage power supply such that its output can be adjusted to approach the switching point of the PMOS-based gm stage to accelerate transmitter operation.

The invention relates to a high-precision calibration method and system for a digital sinusoidal signal generator. According to the method, an ideal sine array is generated through a script program to serve as DAC input; the Raspberry Pi 4B and the DA-AD board form a sinusoidal signal error extraction module, a DA-AD conversion process is executed, and an actual output array is obtained at an ADC output position and used for extracting errors; calculating to obtain a DAC error curve according to the actual output array and the ideal input array, and performing polynomial type fitting and trigonometric function type fitting on the error curve by adopting a least square method and a particle swarm algorithm respectively; and compensating an error fitting result to DAC input, running DA-AD conversion again to obtain an output array, and calculating a compensated DAC output error to represent the precision of the sinusoidal signal. According to the method, the error curve in the sine function form can be accurately fitted, the consumed time is short, and the error fitting in the sine function form better conforms to the theoretical error rule when the DAC is used for generating the sine signal.

A sensor including at least one sensor element configured for measuring an external parameter and outputting one or more results representative for the external parameter, an output buffer configured for receiving the one or more results or a processed version thereof and for applying an analog signal representative for the result or a time multiplexed sequence of analog signals representative for the results on a sensor terminal, and a control circuit configured for obtaining an ID of the sensor, and for receiving a trigger signal, and for determining whether the trigger signal matches the ID of the sensor, and for enabling the output buffer during a predefined period when the trigger signal matches the ID of the sensor.

Some embodiments of the present disclosure include a digital-to-analog conversion system configured to reduce inter-symbol interference (ISI) in high-speed continuous-time DACs. The system can include a main DAC with multiple sub-DACs, each configured to process a portion of a digital input sequence and generate part of an output waveform. To address ISI errors introduced by the sub-DACs, the system can include an ISI mitigation feedback loop. The ISI mitigation feedback loop can include an analog-to-digital converter (ADC) that generates a digital sequence from the output waveform and an analog correction signal generated by a correction DAC. A fractional decimation filter can be used to adjust a sampling rate and attenuate high-frequency components. A digital error estimator can generate an error cancellation sequence by correlating encoder information with the input sequence. The correction DAC can use the error cancellation sequence to generate the analog correction signal.

Methods and apparatus for filtering a signal using a current mode filter circuit that enables source degradation. An example filter circuit generally includes an input node; an output node; a power supply node; a first transistor including a drain coupled with the input node; a second transistor including a drain coupled with the output node and including a gate coupled with a gate of the first transistor; a capacitive element coupled between a drain of the first transistor and the power supply node; a first resistive element coupled between the drain electrode and the gate electrode of the first transistor; a first source degeneration element coupled between a source of the first transistor and the power supply node; and a second source degeneration element coupled between a source of the second transistor and the power supply node.

The invention discloses a communication method for an optical chip high-precision voltage source matrix and an MCU control loop. The communication method comprises the following steps that S1, an MCU module establishes communication connection with an I2C expander through an I2C bus; s2, the MCU sends a chip selection control instruction to the I2C expander, and a plurality of chip selection signals are activated; s3, the MCU sends voltage setting data through the SPI bus; s4, converting the digital signal into an analog voltage signal by adopting an error compensation algorithm based on fractional order Kalman filtering; s5, optimizing the voltage balance based on a jellyfish search optimization algorithm; s6, adjusting the internal working state of the optical chip, and feeding back the running state information to the MCU module; s7, dynamically adjusting a chip selection signal of the I2C expander by the MCU module; and S8, the MCU module monitors abnormal signal interference possibly occurring in the communication process of the I2C and the SPI in real time. According to the invention, a digital-to-analog conversion technology, a communication interface technology and a communication error monitoring and correction technology are combined, so that communication between the high-precision voltage source matrix and the MCU control loop is realized.

A signal processing apparatus includes a plurality of time-interleaving digital-to-analog converters each configured to sample a digital input signal at a preset sub-DAC sample frequency, and to generate an analog sub-DAC output signal. The signal processing apparatus includes analog multiplexer that samples the plurality of sub-DAC output signals at a preset multiplexer clock frequency and generates a multiplexer output signal. The signal processing apparatus further includes a local ADC that receives the multiplexer output signal and generate a digital feedback signal. The signal processing apparatus further includes a digital compensation engine that receives the digital feedback signal from the local ADC and determine one or more distortion compensation parameters. The signal processing apparatus further includes a digital pre-processing stage that receives the one or more distortion compensation parameters from the digital compensation engine and performs distortion compensation pre-processing on the digital input signal.

A device includes a plurality of digital-to-analog converters (DACs), a multiplexer, a plurality of electrodes including a first electrode, and a plurality of direct current (DC) offset circuits including a first DC offset circuit. At least one of the plurality of electrodes is located along a lane for movement of an ion. The multiplexer has multiple inputs coupled to the plurality of DACs and multiple outputs including a first output. The first output is configured to provide a first voltage. The first DC offset circuit is coupled between the first output and the first electrode. The first DC offset circuit is configured to add a first DC offset voltage to either the first voltage or the first voltage amplified by a first gain. The first DC offset voltage is configurable.

Mixer circuitry can include a first pair of transistors coupled to a first tail node and configured to receive a local oscillator signal, a second pair of transistors coupled to a second tail node and configured to receive the local oscillator signal, a first digital-to-analog converter, a second DAC coupled between the first DAC and of the first pair of transistors, and a third DAC coupled between the first DAC and the second pair of transistors. During a first phase, control circuitry can sweep the first DAC to trim a first and / or other odd order local oscillator feedthrough. During a second phase, the control circuitry can sweep the second DAC to trim a second and / or other even order local oscillator feedthrough. During a third phase, the control circuitry can sweep the second and third DACs to reject signals associated with a second harmonic conversion gain of the mixer circuitry.

A DC electronic load circuit relates to the technical field of electronic load control. The utility model provides a direct current electronic load circuit which integrates a dissipation MOS tube array, an analog PID loop, a digital integrated control module, a bus electrical parameter sampling and processing module and a WiFi communication module, and realizes a plurality of working modes such as constant current, constant voltage, constant resistance and constant power by accurately controlling the conduction degree of the MOS tube array. The system has the advantages of real-time monitoring, remote control, overvoltage and overcurrent protection, low power consumption design and the like, and an electronic load solution which is high in precision, high in stability and flexible to operate is provided, so that diversified test requirements are met, and the power supply test efficiency and safety are improved.

Superconducting integrated circuits may advantageously employ superconducting resonators coupled to a microwave transmission line to efficiently address superconducting flux storage devices. In an XY-addressing scheme, a global flux bias may be applied to a number of superconducting flux storage devices via a low-frequency address line, and individual superconducting flux storage devices addressed via application of high-frequency pulses via resonators driven by the microwave transmission line. Frequency multiplexing can be employed to provide signals to two or more resonators. A low-frequency current bias may be combined with a high-frequency current in one or more superconducting resonators to provide Z-addressing. A low-frequency current bias may be combined with a high-frequency current in one or more superconducting resonators to eliminate a flux bias line. A low-frequency current bias may be used at room temperature to identify the presence of a DC short, an open, and / or an unexpected resistance in a superconducting resonator.

The invention relates to the technical field of signal processing, in particular to a large-bandwidth signal source bandwidth flatness compensation method and device based on an FPGA (Field Programmable Gate Array), and the method comprises the steps: playing signal data with required bandwidth through an analog front end based on the FPGA, and measuring an original amplitude-frequency response curve of the signal data through a frequency spectrograph; calculating the amplitude-frequency response of the compensation filter, obtaining a compensation filter coefficient, and quantifying the compensation filter coefficient; sending the quantized compensation filter coefficient to an FPGA to compensate the signal data, playing the signal data through an analog front end, and measuring a first pre-compensation amplitude-frequency response curve in a Nyquist frequency range through a frequency spectrograph; and determining a frequency range exceeding the set bandwidth flatness according to the first pre-compensation amplitude-frequency response curve, and performing independent compensation. Therefore, the influence caused by nonlinearity of a DAC device and related circuits is overcome, the amplitude-frequency response of a large-bandwidth signal source is effectively compensated, the signal flatness in the bandwidth is improved, and the stability and reliability of the system are enhanced.

A high-speed transmitter system using a common mode controlled serialization stage embedded in an output stage is disclosed. In some embodiments, the transmitter includes a serialization circuit that is configured to convert parallel data into serial data with one or more serialization stages; a logic circuit that is configured to connect each input of a last stage of the one or more serialization stages of the serialization circuit, via a respective logic function, to a respective dedicated output stage of an output circuit; and the output circuit that is configured to implement output stages to generate a signal based on the received input using NMOS transistors. In addition, the logic circuit is configured to be a desired voltage value (e.g., the output circuit's common mode) such that a switching point of the NMOS gm stage can be decreased and the gm stage can be activated within a reduced time.

The invention belongs to the field of analog integrated circuit design, and particularly relates to a miniaturized high-precision non-binary R-2R DAC with digital correction. Non-binary characteristics are introduced by setting resistance values of bridge resistors RBm and RBm + 1, so that an LSB section is a binary weight section, and ISB and MSB are non-binary weight sections; therefore, the width-to-length ratios of the MOS tubes of the switches SWm + 1-SWm + i + j and SW1 are equal and do not need to be increased proportionally, the non-binary characteristic is further introduced by setting the switch on-resistance, the selection of the unit resistance R only needs to meet the matching precision of the LSB section, and the area of the switch resistor array is greatly reduced. Static errors in the ISB segment and the MSB segment are respectively corrected by using an OEM correction technology, only digital code redundancy between adjacent segments of the LSB segment, the ISB segment and the MSB segment needs to be obtained through measurement, redundant digital codes are removed by adjusting digital input codes of corresponding segments, and the m + n + k-1 bit binary DAC is obtained through calibration, so that the memory of a digital calibration algorithm is efficient, and the algorithm complexity is effectively reduced. According to the invention, the area of the DAC is obviously reduced while high precision is realized.

A circuit for driving digital-to-analog converter (DAC) comprising a serializer (110, 210) configured to combine multiple signals to one input signal to drive a forward inverter (311) coupled to a first node (A) with a first impedance in serial configuration and a first capacitance (C1) in shunt configuration. The circuit includes a chain of inverters (321, 322) coupled in series to transfer the input signal from the first node (A) to the fifth node based on a signal transfer function. The circuit further includes a feedback inverter (425) between the third node and the first node (A) to form a feedback loop with two inverters in the chain, adding peaking in the signal transfer function at the first node (A). A second feedback inverter (425) can be added between the fifth node and the third node to add peaking in the signal transfer function at the third node. The feedback inverter (425) is designed as a current-starved inverter in order to alleviate hot-carrier injection (HCI) aging of the transistors and add programmability in the peaking. The circuit includes a DAC switch coupled to the fifth node.

A high speed transmitter system using a common mode controlled serialization stage embedded in an output stage is disclosed. In some embodiments, a transmitter comprises: a serialization circuit configured to convert parallel data into serial data using one or more serialization stages; a logic circuit configured to connect each input of a last one of the one or more serialization stages of the serialization circuit to a respective dedicated output stage of the output circuit via a respective logic function; and an output circuit configured to implement an output stage using an NMOS transistor to generate a signal based on the received input. Furthermore, the logic circuit is configured to a desired voltage value (e.g., a common mode of the output circuit) such that the switching point of the NMOS gm stage can be reduced and the gm stage can be activated for a reduced time.

A device comprises a control circuit configured to control a plurality of quantum bits. The control circuit comprises a digital-to-analog converter circuit and switching circuitry coupled to an output of the digital-to-analog converter circuit. The switching circuitry is responsive to switch control signals to selectively connect the output of the digital-to-analog converter circuit to one or more of a plurality of signal paths to generate control signals to control the plurality of quantum bits.