845results about "Digital-analogue convertors" patented technology

Certain aspects of the present disclosure provide a digital-to-analog converter (DAC) circuit. The DAC circuit generally includes: a decoder coupled to an input of the DAC circuit and current-steering cells coupled to an output of the decoder. Outputs of the current-steering cells may be coupled to a positive output node and a negative output node of the DAC circuit. The DAC circuit may also include an offset detection circuit including: a comparator having a first input and a second input selectively coupled to the positive output node and the negative output node; and a digital controller having an input coupled to an output of the comparator and an output coupled to the decoder. In some aspects, the DAC circuit includes one or more calibration DACs coupled to the offset detection circuit.

Methods and apparatus for sharing digital-to-analog (DAC) converters in a reconfigurable DAC circuit to support two or more transmit chains of a wireless transmitter configured for different radio access technologies (RATs) and / or different transmitter architectures. One example DAC circuit generally includes at least four DACs and a plurality of switches coupled to outputs of the at least four DACs such that the DAC circuit is configured as a multi-channel DAC circuit with at least four channels for a first set of one or more frequency bands and as an interleaved DAC circuit with at least two channels for a second set of one or more frequency bands different from the first set of frequency bands.

The invention provides an arbitrary waveform generator multi-chip DAC synchronization system, a delay adjustment module comprises an FPGA chip, an integrated clock management chip and a plurality of DAC chips, and the FPGA chip provides digital signals needing to be converted into analog waveforms for the DAC chips and sends parameter configuration signals to the integrated clock management chip and the DAC chips; the integrated clock management chip generates a reference clock, generates a sampling clock based on the reference clock, distributes the sampling clock to the DAC chip and the FPGA chip, and distributes a synchronization signal to the DAC chip; the multiple DAC chips are all configured to be slave chips to form multiple paths of arbitrary waveform generator output channels, digital signals are synchronously converted into analog signals, the analog signals are processed by a conditioning circuit and then output, the circuit structure of the system is remarkably simplified, synchronization of the multiple DAC chips can be achieved only through one integrated clock management chip, and the system is simple in structure, convenient to use and high in practicability. In addition, delay adjustment between DAC chips can be flexibly achieved, calibration or alignment of circuits and devices is not needed, and good application effects are achieved.

A sensor including at least one sensor element configured for measuring an external parameter and outputting one or more results representative for the external parameter, an output buffer configured for receiving the one or more results or a processed version thereof and for applying an analog signal representative for the result or a time multiplexed sequence of analog signals representative for the results on a sensor terminal, and a control circuit configured for obtaining an ID of the sensor, and for receiving a trigger signal, and for determining whether the trigger signal matches the ID of the sensor, and for enabling the output buffer during a predefined period when the trigger signal matches the ID of the sensor.

A DC electronic load circuit relates to the technical field of electronic load control. The utility model provides a direct current electronic load circuit which integrates a dissipation MOS tube array, an analog PID loop, a digital integrated control module, a bus electrical parameter sampling and processing module and a WiFi communication module, and realizes a plurality of working modes such as constant current, constant voltage, constant resistance and constant power by accurately controlling the conduction degree of the MOS tube array. The system has the advantages of real-time monitoring, remote control, overvoltage and overcurrent protection, low power consumption design and the like, and an electronic load solution which is high in precision, high in stability and flexible to operate is provided, so that diversified test requirements are met, and the power supply test efficiency and safety are improved.

A high-speed transmitter system using a common mode controlled serialization stage embedded in an output stage is disclosed. In some embodiments, the transmitter includes a serialization circuit that is configured to convert parallel data into serial data with one or more serialization stages; a logic circuit that is configured to connect each input of a last stage of the one or more serialization stages of the serialization circuit, via a respective logic function, to a respective dedicated output stage of an output circuit; and the output circuit that is configured to implement output stages to generate a signal based on the received input using NMOS transistors. In addition, the logic circuit is configured to be a desired voltage value (e.g., the output circuit's common mode) such that a switching point of the NMOS gm stage can be decreased and the gm stage can be activated within a reduced time.

The invention belongs to the field of analog integrated circuit design, and particularly relates to a miniaturized high-precision non-binary R-2R DAC with digital correction. Non-binary characteristics are introduced by setting resistance values of bridge resistors RBm and RBm + 1, so that an LSB section is a binary weight section, and ISB and MSB are non-binary weight sections; therefore, the width-to-length ratios of the MOS tubes of the switches SWm + 1-SWm + i + j and SW1 are equal and do not need to be increased proportionally, the non-binary characteristic is further introduced by setting the switch on-resistance, the selection of the unit resistance R only needs to meet the matching precision of the LSB section, and the area of the switch resistor array is greatly reduced. Static errors in the ISB segment and the MSB segment are respectively corrected by using an OEM correction technology, only digital code redundancy between adjacent segments of the LSB segment, the ISB segment and the MSB segment needs to be obtained through measurement, redundant digital codes are removed by adjusting digital input codes of corresponding segments, and the m + n + k-1 bit binary DAC is obtained through calibration, so that the memory of a digital calibration algorithm is efficient, and the algorithm complexity is effectively reduced. According to the invention, the area of the DAC is obviously reduced while high precision is realized.

Apparatus, systems, and methods for systems and methods for data signal multiplexing may be provided. According to an aspect a method for data signal multiplexing may be provided. The method includes interleaving, by a first 4-to-1 (4:1) multiplexer (MUX), a first set of four analog signals received from a first group of 4 Digital-to-Analog Converters (DACs) to generate a first interleaved analog output. The method may further include interleaving, by a second 4:1 MUX, a second set of four analog signals received from a second group of 4 DACs to generate a second interleaved analog output. Each of the first and the second interleaved analog output may be based on a first 8-unit interval (UI) window including four consecutive 2 UI windows. The method may further include interleaving, by a 2:1 MUX, the first interleaved analog output and the second interleaved analog output to generate a combined interleaved analog output.

A high-speed transmitter system using a supply controlled serialization stage embedded in a PMOS output stage is disclosed. In some embodiments, the transmitter includes a serialization circuit that is configured to convert parallel data into serial data with one or more serialization stages; a logic circuit that is configured to connect each input of a last stage of the one or more serialization stages of the serialization circuit, via a respective logic function, to a respective dedicated output stage of an output circuit; and the output circuit that is configured to implement output stages to generate a signal based on the received input using PMOS transistors. In addition, the logic circuit is connected to a low voltage supply such that its output can be adjusted to be close to a switching point of the PMOS based gm stage to speed up transmitter operations.

The invention relates to a high-speed serial interface circuit, and discloses a linearity calibration and precision expansion method of a numerical control phase interpolator. According to the method, a digital delay converter (DDC) is cascaded behind a digital control phase interpolator (DPI), and delay compensation is carried out on an interpolated clock signal; sampling the compensated clock signal by using an analog-to-digital converter (ADC) to obtain a phase sampling value; the calibration control module calculates a phase error and generates a delay control word; when the numerical control phase interpolator DPI works, phase control words and delay control words are synchronously provided for corresponding modules, and linearity calibration and precision expansion are achieved. According to the method, a special detection circuit does not need to be added, hardware resources existing in a high-speed serial interface are utilized, the method can be achieved through simple digital control logic, the phase integral linearity is improved to be within 25 fs from 250 fs, meanwhile, the precision of an 8-bit phase interpolator is improved to be close to the 11-bit level, and the method is suitable for large-scale popularization and application. And the clock recovery performance and the data transmission reliability of the high-speed communication system are obviously improved.

Wireless circuitry may include a transmission line that carries a signal and a power detector that measures the signal. The detector may include a rectifier coupled to a comparator over a differential path. An offset calibrating digital-to-analog converter (OSDAC), a reference generator, and a multiplexer may be disposed on a negative line of the differential path. The OSDAC may produce an offset-compensated voltage by adding different offset voltages to a voltage on the second line over time. The reference generator may generate a set of threshold voltages by adding different reference voltages to the offset-compensated voltage. A temperature sensor may adjust the reference voltages used to generate the threshold voltages based on a temperature of the power detector. The multiplexer may route different threshold voltages to a negative input of the comparator.

A time-interleaved current-based digital-to-analog converter (current DAC) cell includes first input circuitry configured to receive a digital input signal, a first biasing voltage, a first clock, and a second clock. The first clock and the second clock having a phase offset from one another and having a common period. The current DAC also includes a first gate configured to, responsive to an ‘ON’ state of the first clock, pass the digital input signal to a second gate, the second gate being configured to, responsive to an ‘OFF’ state of the second clock, output a first DAC cell activation signal. The current DAC further includes first output circuitry configured to, responsive to the first DAC cell activation signal, output a first analog current signal based on (i) the digital input signal and (ii) the first biasing voltage.

The current-mode end-to-end signal path includes a digital-to-analog converter (DAC) operating in current mode and an upconverting mixer operating in current mode and operably coupled to the DAC, where analog inputs and analog outputs of the DAC and the upconverting mixer are represented as currents, and the DAC generates a baseband signal.

To provide a filter stage system.SOLUTION: A filter stage system includes a continuous time baseband filter comprising a feedback loop that employs at least one first impedance node and at least one second impedance node. The at least one first impedance node has a higher impedance than the at least one second impedance node. The at least one first impedance node provides a dominant pole, and the at least one second impedance node provides a non-dominant pole. The continuous time baseband filter generates a filtered current. The filter stage system also includes a mirroring component that mirrors the filtered current to an output.SELECTED DRAWING: Figure 2

The invention provides a digital-to-analog converter which comprises a first reference voltage node, a second reference voltage node, a plurality of change-over switches, a plurality of resistor units and a plurality of capacitor units, the resistor units and the capacitor units are sequentially connected in series to form a series circuit, and the plurality of change-over switches respectively receive multi-digit digital code values in digital signals and output first reference voltage or second reference voltage. And finally, an analog voltage signal is output through an output node of the digital-to-analog converter to realize digital-to-analog conversion, and meanwhile, capacitors in the capacitor units are connected in parallel between the two corresponding resistor network nodes and carry out rapid charging and discharging on the two resistor network nodes, so that the voltage switching efficiency of the resistor network nodes is improved, and the reliability of the digital-to-analog converter is improved. The delay in the digital signal transmission process is reduced, so that the purpose of reducing burrs is achieved, the digital-to-analog converter does not need to be additionally provided with a preprocessing module and a filter, the design cost is reduced, and the conversion efficiency is improved.

Provided is a potentiostat-based electrochemical sensor detection device. The device comprises: a digital-to-analog converter (DAC) configured to receive a digital signal from a waveform generator and digital logic and output an analog signal corresponding to a reference voltage; a control amplifier (CA) configured to receive the analog signal corresponding to the reference voltage and apply the reference voltage to a reference electrode (RE); a gain-boosting current mirror configured to copy a sensor current of an electrochemical sensor and output a copied sensor current; a transimpedance amplifier configured to convert the copied sensor current into a voltage signal; a low-pass filter configured to block a high-frequency band signal component of the voltage signal; and an analog-to-digital converter (ADC) configured to perform digital signal processing on a signal having passed through the low-pass filter, wherein at least one of the gain-boosting current mirror and the transimpedance amplifier employs a dynamic element matching (DEM) technique using a plurality of choppers and a plurality of DEM clock signals.

The invention provides a differential signal generator and a calibration method thereof, and the differential signal generator comprises a control processing unit which is used for obtaining a common-mode bias voltage set value and a differential-mode bias voltage set value, determining a common-mode bias voltage code word according to a first mapping relation, determining a differential-mode bias voltage code word according to a second mapping relation, and setting the common-mode bias voltage set value and the differential-mode bias voltage set value; the common-mode bias voltage code word and the differential-mode bias voltage code word are output to the output amplification unit; the waveform generation unit is connected with the output amplification unit and is used for providing a positive-end alternating-current signal and a negative-end alternating-current signal for the output amplification unit under the control of the control processing unit; the output amplification unit is used for obtaining a positive-end bias intermediate voltage and a negative-end bias intermediate voltage according to the common-mode bias voltage code word and the differential-mode bias voltage code word so as to output a positive-end output signal and a negative-end output signal; the differential signal generator solves the problem that an existing differential signal generator cannot adjust common-mode bias output voltage and differential-mode bias output voltage.

The techniques and circuits, described herein, include solutions for error compensation in source measurement units (SMUs). An example SMU is capable of both sourcing current to a device under test (DUT) and measuring current through the DUT. An SMU may include a sensing resistor coupled in series with the DUT. A voltage across the sensing resistor may be measured by a current sensing amplifier in order to determine the output current through the DUT. In practice, the resistance of the sensing resistor may vary depending on manufacturing tolerances, etc. A gain of the current sensing amplifier may be calibrated in order to compensate for sensing resistor variance, which increases the accuracy with which current to the DUT can be sourced and measured.

A filter stage system comprising a continuous-time baseband filter comprising a feedback loop employing at least one first impedance node and at least one second impedance node, wherein the at least one first impedance node has a higher impedance than the at least one second impedance node, and wherein the at least one first impedance node provides a dominant pole and the at least one second impedance node provides a non-dominant pole, and wherein the continuous-time baseband filter generates a filtered current, and a mirror component mirrors the filtered current to an output.

The invention relates to the technical field of integrated circuits, and provides a digital-to-analog conversion circuit and a control chip. The circuit comprises a digital decoder, a nonlinear digital-to-analog converter and a linear digital-to-analog converter, the digital decoder is used for decoding the first M bits of the N-bit digital code and outputting a decoding result; the nonlinear digital-to-analog converter is connected with the linear digital-to-analog converter, and the nonlinear digital-to-analog converter is used for processing a voltage range formed by the received first input voltage and second input voltage according to a decoding result and outputting corresponding voltages respectively; the linear digital-to-analog converter receives the last N-M digital codes of the N digital codes, quantizes a voltage range formed by voltages received by the two input ends of the linear digital-to-analog converter according to the last N-M digital codes of the N digital codes, and outputs a reference voltage. According to the digital-to-analog conversion circuit provided by the embodiment of the invention, the consumption of parts and the layout area of the digital-to-analog conversion circuit can be reduced.

An analog signal generation device according to the present invention includes a DA converter that adjusts a signal level of a digital signal according to a DAC correction amount and then converts the digital signal into an analog signal, a detector that detects the analog signal and outputs a detection signal, a storage unit that stores a characteristic equation for calculating the DAC correction amount, and a control unit, in which in a case where the differential voltage when the digital signal having a signal level of a predetermined value is input to the DA converter is larger than a threshold value, the control unit calculates a new DAC correction amount based on the differential voltage by using the characteristic equation, and in a case where the differential voltage does not fall within the threshold value, the control unit corrects the characteristic equation.

The invention relates to a buffer and an integrated circuit. The buffer includes: an operational amplifier; the first end of the voltage-voltage feedback network is coupled to the positive phase / negative phase input end of the operational amplifier; the first end of the isolation resistor is coupled to the output end of the buffer; the first group of switches and the second group of switches are controlled to be closed when the first capacitive load is driven, the second group of switches are disconnected when the second capacitive load is driven, and the first group of switches are disconnected and the second group of switches are closed when the second capacitive load is driven; in the first load, the output end of the operational amplifier is coupled to the output end of the buffer through at least one switch in the first group of switches, and the second end of the voltage-voltage feedback network is coupled to the output end of the buffer through at least one switch in the first group of switches. In the second load, the output end of the operational amplifier is coupled to the second end of the isolation resistor through at least one switch in the second group of switches, and the second end of the voltage-voltage feedback network is coupled to the output end of the operational amplifier through at least one switch in the second group of switches.

Techniques that enable calibration of digital-to-analog Converters (DACs) with minimal processing overhead. A single frequency bin can be used to calibrate errors between bits. A low frequency feedback path can be included into a low frequency low power ADC to determine the error signal that exists in the calibration bin. The bits are calibrated when this error signal is minimized. The calibration techniques described provide an extremely efficient and optimal calibration at the DAC output of both static and dynamic errors.

Certain aspects of the present disclosure are directed towards a digital-to-analog converter (DAC) system. The DAC system generally includes a first driver and a plurality of current-steering cells. A first current-steering cell of the plurality of current-steering cells includes: a first current source coupled to a first current-steering transistor and a second current-steering transistor, wherein a gate of the first current-steering transistor and a gate of the second current-steering transistor are coupled to a first output and a second output of the first driver, respectively; a first transistor having a source coupled to a current source path and a drain coupled to a reference potential node; and a second transistor having a source coupled to the current source path and a drain coupled to the reference potential node.

Systems and methods are related to a successive approximation analog to digital converter (SAR ADC). The SAR ADC includes a sample and digital to analog conversion (DAC) circuit configured to sample an input voltage, a comparator circuit coupled to the sample and DAC circuit and having an output, a first set of storage circuits, and a comparator driver. The comparator driver is disposed between the output and the first set of storage circuits. The first set of storage circuits are coupled to the comparator circuit and the sample and DAC circuit. The comparator driver can include a first driver and second driver. The first driver is coupled to a first input of a first storage circuit of the first set of storage circuits, and the second driver is coupled to first inputs of a second set of storage circuits within the first set of storage circuits.

In accordance with some embodiments of the present disclosure, an analog-to-digital-converter (ADC) is provided. The ADC may include a capacitive DAC (CDAC), a comparator, and a successive approximation register (SAR) logic configured to control the CDAC and the comparator to perform a successive approximation conversion of an analog input into a digital output signal. The CDAC includes a plurality of unary-weighted capacitors having the same capacitor value and a plurality of binary-weighted capacitors. In some embodiments, the CDAC includes a first capacitor array and a second capacitor array. Each of the first capacitor array and the second capacitor array may include a plurality of unary-weighted capacitors and a plurality of binary-weighted capacitors.

A method of an optical sensor device includes: providing an optical sensor for receiving reflected light associated with a light emission unit to generate at least one sensed image; using a first exposure setting to make the optical sensor generate a first frame data during a first frame time period of a frame; when performing an exposure adjustment operation, using a second exposure setting to make the optical sensor generate a second frame data during a second time period of the frame neighbor to the first frame time period of the frame; and, generating a normalized digital signal corresponding to the first frame data based on the relation between the first frame data and the second frame data.

The invention discloses a high-reliability three-dimensional integrated direct sampling software radio architecture radio frequency microsystem, which is based on a direct sampling software radio system architecture and a multi-layer glass-based TGV adapter plate wafer-level bonded POP three-dimensional stacked packaging architecture. A high-performance glass antenna, silicon-based single core particle Fan-in and Fan-out packaging, mixed multi-core particle integration of an embedded glass-based TGV adapter plate, mixed bonding integration of a silicon-based digital TSV adapter plate and the glass-based TGV adapter plate are combined, and a glass antenna, a direct sampling core particle, a silicon-based computing power circuit, a silicon-based storage circuit and a silicon-based interface circuit are integrated. And the three-dimensional heterogeneous integration of the microsystem is realized. According to the micro-system, a glass substrate is used as a main body packaging material, a radio frequency circuit and a digital-analog hybrid circuit are fused, three-dimensional heterogeneous integration from a glass antenna to a baseband storage and calculation integrated processing circuit is realized, and a complete integrated airtight packaging micro-system is formed and can cover a DC-20GHz frequency band.

The invention provides a vector signal source and a design method thereof, which can be applied to the technical field of communication. The vector signal source comprises: a generation module comprising a plurality of parallel direct digital synthesizers, the generation module being configured to generate a plurality of target digital signals based on drive clock signals corresponding to the plurality of direct digital synthesizers, the driving clock signals respectively corresponding to the plurality of direct digital synthesizers have phase differences relative to each other and are equal in frequency; the conversion module comprises a plurality of digital-to-analog converters electrically connected with the plurality of direct digital synthesizers respectively, and the conversion module is configured to convert the received multiple paths of target digital signals into multiple paths of target analog signals respectively based on sampling clock signals corresponding to the multiple digital-to-analog converters respectively, the sampling clock signals corresponding to the plurality of digital-to-analog converters are synchronized relative to each other; and the synthesis module is configured to integrate the multiple paths of target analog signals according to a time sequence to obtain a target vector signal source.

Embodiments disclosed herein relate to digital-to-analog converters (DACs), and more particularly, to architecture thereof for improving bit resolution of the DACs. In an embodiment, a circuit is provided that includes a first DAC sub-circuit, a second DAC sub-circuit, and a control circuit coupled to control the first and second DAC sub-circuits. The first DAC sub-circuit includes a first set of transistors and a first set of switches coupled to the first set of transistors and to output nodes. The second DAC sub-circuit includes a second set of transistors coupled to the first set of transistors and a second set of switches coupled to the second set of transistors and to the output nodes.