438 results about "Gigabit" patented technology

The invention provides a satellite-borne computing center system, in particular to a satellite-borne computing center system with high performance and high computing power, which comprises a data interaction module, a task management module, an artificial intelligence AI module M1 and an artificial intelligence AI module M2. The data interaction module is an input and output interface for high-speed data processing; the task management module serves as a task scheduling center and distributes calculation tasks to the AI module; the artificial intelligence AI module M1 and the artificial intelligence AI module M2 adopt domestic and imported AI chips, and the artificial intelligence AI module can work in an RC mode and an EP mode, provides computing power guarantee for satellite-borne high-computing-power computing tasks, and has the characteristics of flexible expansion and agile deployment. All the modules are interconnected through a serial port management plane, a gigabit network control plane, a PCIE data plane and a power supply plane, and control and data interaction between processors are achieved.

The invention belongs to the technical field of Ethernet high-speed interconnection, and provides a high-speed low-delay 10-gigabit switching method and system based on an FPGA, and the method comprises the steps: receiving Ethernet data frames, storing effective data frames in a data caching module, and generating a caching write-in address and a control signal; reading a destination address, a source address and a type field of the analyzed data frame from the data caching module, and updating a forwarding address table through a dynamic learning mode or a preset mode; based on the updated forwarding address table, a three-level assembly line framework is adopted to complete address searching; reading the data frame from the cache according to the forwarding decision, repackaging the Ethernet header information and the check code, and controlling the sending standard rate; and meanwhile, the sending rate is dynamically adjusted, and VLAN division, port rate and queue scheduling parameters are optimized in combination with an external configuration command. According to the invention, the onboard processor is utilized to cooperate with the FGPA to realize the fast search of the forwarding table, the residence time of the data packet in the switching unit is reduced, and the operation efficiency of the side application is improved.

The invention relates to a video acquisition and transmission method and device for converting a 10-gigabit network into a PCIe (Peripheral Component Interconnect Express) interface. The method comprises the following steps: receiving a video stream through a double 10-gigabit network optical module, carrying out protocol analysis and preprocessing through an FPGA (Field Programmable Gate Array), realizing multi-path alternate reading and writing by utilizing DDR3 ping-pong cache, dynamically distributing the video stream to multiple devices through a three-path PCIe 3.0 * 4 interface and an XDMA (Extensible Direct Memory Access), and optimizing the transmission priority in combination with a load state. The device comprises two paths of SFP + optical modules, a Xilinx Virtex7 series FPGA chip (integrated with a 10-gigabit network MAC, a PCIe XDMA IP core and a DDR3 controller), three paths of PCIe 3.0 * 4 interfaces and an external DDR3 memory. The system has the advantages that the double 10-gigabit network input and multi-PCIe channel collaborative architecture breaks through the single-channel bandwidth bottleneck; the intelligent ping-pong cache and the AXI arbitration strategy reduce the data conflict risk; and dynamic bandwidth allocation optimizes real-time performance.

The utility model discloses an impedance matcher, a radio frequency assembly and plasma processing equipment. Each impedance matcher comprises an impedance matching network and a control unit, at least one impedance matcher is electrically connected between the radio frequency source and the load end through a radio frequency link, and the impedance matching network is electrically connected with the control unit through a high-speed communication bus, the radio frequency source is electrically connected with the control unit through a high-speed communication bus, and the load end is electrically connected with the control unit through a high-speed communication bus. The impedance matching network, the control unit, the radio frequency source and the load end are provided with industrial Ethernet control automation technology ports and / or gigabit transmit-receive interfaces, so that the high-speed communication bus carries out high-speed signal transmission, and the delay is obviously reduced.

The invention discloses an uplink subsystem complexity reduction method based on a PCMA technology, and relates to the technical field of high-capacity wireless transmission system design and complexity control, and the method comprises the following steps: collecting uplink signal parameters through spectrum analysis, bit error rate test and MIMO detection, obtaining channel characteristics through a pilot frequency and a Gray sequence, and obtaining the complexity of a high-capacity wireless transmission system; baseband data are generated, scene features are extracted, Wiener filtering and iterative soft decision feedback algorithms are adopted to optimize filtering and coding, channel and coding performance is evaluated, transmission strategies are dynamically adjusted through a gigabit network interface, clocks are unified, synchronization is optimized, and the complexity of a PCMA uplink system is reduced. The complexity of an uplink subsystem is effectively reduced through the PCMA technology, the efficiency and the stability of a high-capacity wireless transmission system are improved, efficient utilization of resources and improvement of synchronization precision are achieved by accurately collecting signal parameters, optimizing filtering and coding and dynamically adjusting a transmission strategy, and the method is suitable for large-scale popularization and application. And powerful support is provided for the development of a wireless communication system.

The invention relates to a 10-gigabit photoelectric composite cable for communication. The 10-gigabit photoelectric composite cable comprises a first coating station, a second coating station and a performance testing station which are sequentially arranged in the cable transmission direction. The first coating station is provided with a first protection mechanism used for installing the armor on the inner layer of the composite cable. The second coating station is provided with a second protection mechanism used for installing and fixing water absorption particles. The performance test station is provided with a detection mechanism used for cooling the cable and detecting the integrity of the outer layer of the composite cable. By arranging the first protection mechanism and the second protection mechanism, the technical problems that the cable armor layer is prone to dislocation and the damaged position cannot be quickly found after the cable is damaged are solved.

The invention discloses a rail transit multi-system fusion platform, and relates to the technical field of intelligent operation and maintenance of rail transit vehicles, and the platform comprises a fusion platform host, a communication switch, an application system and terminal equipment thereof. The core of the system is that logic functions of all application systems are packaged in an SDK mode, interaction with a fusion platform host is achieved through a unified API interface, computing power sharing of hardware resources such as an AI module and an MPU module in the host is achieved through a 10-gigabit PCIE bus, a SWITCH switch module dispatches data transmission in a unified mode, the independent computing capacity of a subsystem is reserved, and the data transmission efficiency is improved. By means of the framework, the newly-added system does not need to additionally deploy a host, the function can be expanded only by accessing terminal equipment meeting the standard, the limitation that in a distributed framework, hardware needs to be added to the newly-added system is effectively solved, and elastic reuse of the hardware resources is achieved.

The invention discloses a large-scale vector approximate nearest neighbor search heterogeneous system based on a GPU-NVMe framework, which is characterized in that the system is based on a direct GPU-NVMe framework, and a hybrid index combining a clustering algorithm and a graph algorithm is designed. According to the hybrid index, vectors with good clustering are efficiently processed by utilizing the parallel processing capacity of the GPU, and meanwhile, the search accuracy of noise vectors is improved by taking a graph index as a compensation mechanism. According to the method, collaborative optimization of hardware and software is fully considered, vector index data deployment is implemented at an NVMe driving level, meanwhile, CPU and GPU hardware are cooperatively utilized to carry out a gigabit-level vector retrieval calculation process, and an extensible large-scale retrieval system on a direct GPU-NVMe architecture is constructed. Compared with the prior art, the method has the advantages that the performance bottleneck in the gigabit-level vector data search is effectively solved, the search throughput and accuracy are remarkably improved, and the search delay is reduced.

The invention provides a method for testing the communication bandwidth of a 10-gigabit network between an FPGA (Field Programmable Gate Array) and a CPU (Central Processing Unit), which is applied to a radar system. The FPGA completes a function of regularly generating data and a function of downlink transmission of the data; the 10-gigabit network exchange board card completes data transmission and sends data to the CPU board card through a 10-gigabit network; and the CPU board card receives the data and calculates the communication bandwidth and the network quality. According to the invention, the limitation of traditional single-port point-to-point transmission or simple multi-port parallel transmission on synchronization, load balancing or protocol overhead is solved, and a solution is provided for how to effectively utilize multiple ports, enable the multiple ports to simultaneously and efficiently work and ensure parallel transmission of data without mutual interference.

The invention relates to a data synchronization charging bin for a wireless sensor network, which comprises a data synchronization bin body structure and a data synchronization control system, the data synchronization bin body structure is provided with a plurality of grooves in a data synchronization bin body, and each groove is used for placing a wireless sensor. A charging and communication interface of the wireless sensor adopts a magnetic suction connector form, a shell of the data synchronization bin body is provided with a display screen, a control key and an indicator lamp, and the data synchronization bin is externally provided with a gigabit network communication interface; the data synchronization control module comprises an ARM main control module, a storage module, a communication module, a Beidou time service module and a power management module. According to the data synchronization charging bin for the wireless sensor network, rapid data collection and centralized charging of nodes of the wireless sensor network can be achieved, and meanwhile system time correction and synchronization of all the nodes in the wireless sensor network are completed.

1. The name of the product of this design: Gigabit network cable splitter (TXE273). 2. Purpose of this design product: a splitter used to expand the network cable interface. 3. The design key point of this appearance design product lies in the combination of shape and pattern. 4. The picture or photo that best illustrates the design points: Stereoscopic diagram 1.

The invention discloses a data processing method and device and belongs to the technical field of communication. The method is applied to the flexible Ethernet (FlexE), and the method is applied to the flexible Ethernet (FlexE). The method comprises: receiving an initial data stream sent by a FlexE instance, periodically inserting a filling sequence in the initial data stream to obtain a first data stream, the first data stream comprising the periodically appearing filling sequence, the filling sequence comprising continuous n filling code blocks, and n being an integer greater than or equal to 4. The invention provides a FlexE (FlexE)-oriented method capable of inserting more filling code blocks into a data stream, which can be suitable for PHY (Physical Layer) interfaces with higher rate, such as a 800 gigabit Ethernet (GE) PHY interface, a 1.6 TE PHY interface and the like, and can adapt to the evolution of the Ethernet standard.

The utility model provides a mainboard circuit for updating a CPLD (Complex Programmable Logic Device), which relates to the technical field of computer mainboards, and is characterized in that a signal sent by a BMC (Baseboard Management Controller) management module daughter card is transmitted to a signal switching chip and a gigabit management network port through the connection of a memory connector and the BMC management module daughter card; the gigabit management network port receives signals and provides high-speed network transmission for remote online updating of the CPLD unit module; the signal switching chip receives a signal and switches a debugging mode of the CPLD unit module based on the signal, the CPLD unit module is connected with the firmware burning connector to carry out local offline debugging when the debugging mode is local offline debugging, and the CPLD unit module is connected with the BMC management module daughter card to carry out remote online debugging when the debugging mode is remote online debugging. Two debugging modes of local off-line debugging and remote on-line debugging are realized, and the coupling degree of each part in a mainboard circuit is reduced.

The utility model discloses a DMD-based high-frame-frequency and high-gray-scale scene simulator, which belongs to the technical field of scene simulators, adopts double DMD devices to work cooperatively, adopts a first-stage DMD device to control light source energy level modulation, adopts a second-stage DMD device to control scene bitmap playing, can greatly reduce playing time when high-gray-scale images are played, and improves the playing efficiency of the high-frame-frequency and high-gray-scale scene simulator. High-frame-frequency image playing is achieved, a scene simulator circuit system adopts double DMD devices for synchronous playing, and 12-bit grayscale images are played based on the DMD device with the model of DLP7000. During 10-gigabit network transmission, an image data frame comprises auxiliary information such as an image data frame header, an image sequence number and an image line number, and two adjacent pixel data of an image are 24-bit data in total and are spliced into 3 bytes for transmission; after the DMD control circuit receives and analyzes the image data frames, the image data frames are split into bitmap data according to bits, and the bitmap data are respectively stored in a DDR memory. According to the scene simulator circuit system designed by the invention, 12-bit grayscale images can be played, and the playing frame frequency reaches 100fps.

The invention provides a satellite-borne basic mirror image and customized mirror image containerization deployment operation system and method, and the method comprises the steps: packaging a fixed basic service to form a basic mirror image, such as a satellite-borne hardware drive program, an AI resource interface program, a storage resource interface program, a telemetering and remote control bus interface program, and a PCIE / 10-gigabit network interface high-speed bus interface program; and subscribing to a distribution interface program among satellites and the like. The customized mirror image uses the basic mirror image through a docker FROM command; the customized mirror image comprises a remote sensing intelligent interpretation AI model mirror image, an inter-satellite cooperative task planning mirror image, a user data issuing broadcast mirror image and the like; the basic mirror image serves as factory software firmware of satellite development, the customized mirror image can be tested without binding during batch production of satellites, the basic mirror image is printed on the sky, and the customized mirror image is subjected to on-orbit programming according to user requirements, or a service operation mirror image is pulled from a space-based private mirror image warehouse.

The invention relates to the technical field of optical network transmission, in particular to a twenty-five gigabit symmetric passive optical network transmission quality improvement method and a related device. The method comprises the steps that PCB routing layout optimization is conducted on an LD + / LD-differential signal line in a transmission link, impedance control over the differential signal line is achieved by adjusting the wiring gap and the wiring width of the LD + / LD-differential signal line and the integrity of a reference layer area, the consistency difference in PCB production is improved, and loss and interference in the signal transmission process are reduced. The PCB layout parameters of the LD + / LD-differential signal line are specifically optimized, the wiring gap is adjusted from 11.49 mi of a reference golden finger bonding pad to 5.75 mi of a reference chip BGA bonding pad, the wiring width is reduced from 20 mi to 10 mi, the integrity of a reference layer area is synchronously optimized, the differential impedance is accurately controlled from original 30 ohms to 60 ohms, and the reliability of the circuit is improved. And the parasitic parameter influence in signal transmission is effectively suppressed.

The invention relates to a remote sensing satellite data automatic distribution method and system, and the method comprises the following steps: S1, receiving and analyzing a data transmission plan issued by a superior, completing the legality detection, and extracting and storing the task parameters of a legal plan; s2, matching corresponding satellite parameter information from pre-stored satellite attribute parameters according to task requirements; s3, state information, including a task execution state, a load state, a hardware operation state and a network flow state, of the distribution equipment is collected, and available equipment resources are dynamically distributed based on the multi-dimensional state data; and S4, a scheduling task is completed by using a satellite ground transmission model, and one-to-one or one-to-multiple target center distribution task automation is realized based on data driving. According to the invention, automatic resource scheduling can be realized according to task information, in-station equipment resources and satellite information to complete a one-to-many data distribution task, and reliable and efficient 10-gigabit network transmission is realized.

The invention relates to the technical field of clock source sharing, and particularly discloses a system and a method for sharing a clock source by a platform, which are used for sampling LVPECL clock signals distributed to a Feiteng processor and a 10-gigabit network card by a clock buffer so as to obtain a first LVPECL clock sampling signal and a second LVPECL clock sampling signal; and a signal processing algorithm based on artificial intelligence and deep learning is introduced at a rear end to analyze LVPECL clock sampling signals of the two, so that fine-grained optimal matching interaction characteristics of the LVPECL clock sampling signals of the two are learned and captured, and signal waveform semantic joint representation and clock buffer performance monitoring are carried out. Therefore, the monitoring result of whether the working state of the clock buffer is abnormal or not is obtained. Therefore, the quality of the clock signal can be continuously checked and monitored in an intelligent automatic monitoring mode, and the working condition of the clock buffer can be fed back in time.

The invention discloses a method for applying a gigahertz bulk acoustic wave resonator to active drug loading of lipidosome, and belongs to the technical field of drug loading. The present invention is a universal method for efficiently, quantitatively loading one or more drug molecules having different solubilities into liposomal vesicles. On the basis of a high-speed vortex-shaped acoustic streaming effect generated by a kilomegahertz bulk acoustic wave resonator, the permeability of the liposome with the flowable phospholipid bilayer membrane is changed, so that drugs with different solubilities can be loaded into the liposome at the same time; and the loading capacity of the medicine can be quantitatively controlled by regulating and controlling the working power and time of the GHz bulk acoustic wave resonator. The application range of the method is not limited to specific phospholipid molecules assembled by lipidosome types, and the method is effective for vesicle cavities with phospholipid bilayer structures. The loading method used in the invention can improve the preparation efficiency of the drug carrier, is not limited by the hydrophilic and hydrophobic properties of the drug, and can realize the preparation of the drug carrier with quantitative concentration.

The invention discloses a data network interaction system for rail transit data transmission, which relates to the technical field of data transmission and comprises a data acquisition module, an intelligent exchange scheduling module, a real-time processing module and a high-reliability transmission guarantee module. And high-speed and reliable transmission is ensured through a 10-gigabit point-to-point direct connection channel, and meanwhile, continuity is ensured by adopting a redundant link, so that efficient, stable and real-time processing of rail transit data is realized. According to the invention, a high-speed dedicated channel is constructed through direct connection of the 10-gigabit Ethernet, and hierarchical transmission of multi-source data is realized in combination with an intelligent scheduling strategy; meanwhile, hardware-level heartbeat detection and redundant links are deployed, and millisecond-level fault switching is guaranteed; and a dynamic threshold adjustment mechanism is introduced, the reliability and robustness of the system are adaptively optimized, and the high-real-time and high-reliability transmission requirements of rail transit are met.

The invention belongs to the technical field of information security application, and particularly relates to a message unloading intelligent network card based on ARM + ASIC heterogeneity, the message unloading intelligent network card comprises a message analysis module, an ARM + ASIC heterogeneity module, a flow filtering module and a label adding module, the ARM + ASIC heterogeneity module comprises a GIGABIT MAC module, a rule setting module, a rule searching module, a DDR3 SDRAM controller, a QDR SRAM controller and a PCI-E interface. The intelligent network card based on ARM + ASIC isomerism utilizes the advantages of low cost and low time delay of a domestic chip, realizes high efficiency and high performance of message classification and processing, realizes message classification and filtering in hardware, effectively unloads the overhead of application software for underlying network message processing, and effectively improves the network security application software on a high-speed network. Message capture and data acquisition functions are developed based on an intelligent network card, and the overall performance of the system is effectively improved.

The invention relates to the technical field of computer secrecy, and discloses a secrecy-related computer secrecy self-supervision detection method based on a gigabit network, which comprises the following steps of: firstly, acquiring communication data and equipment characteristic data through a network flow analysis module, and determining monitoring node division; constructing a detection index set according to the communication data, and determining an abnormal data acquisition strategy by combining monitoring node division; then, acquiring real-time communication data by using an abnormal data acquisition terminal according to a strategy, and identifying a confidentiality risk level and a violation item to obtain detection result data; and finally, the detection result data is transmitted to the supervision control platform according to a self-supervision feedback mechanism for index updating. According to the method, accurate detection and self-supervision of the confidentiality risk of the confidential computer in the gigabit network environment are realized, the confidentiality security is improved, and the method is suitable for the field of confidentiality detection of the confidential computer.

The invention discloses a multiprocessor architecture intelligent adaptive base plate of a nuclear power DCS controller, and relates to the field of nuclear power control, and the base plate comprises a signal processing module which is used for collecting and preprocessing each path of signal and then realizing bidirectional data communication with a core board card main processor; the PCIE network controller expansion module is used for realizing gigabit network interface expansion; the storage module is used for storing data; the redundancy synchronization module is used for realizing redundancy switching and network synchronization of the main controller and the standby controller; the bottom plate power supply system is used for providing voltage; the bottom plate clock system is used for providing time information; the connector is used for connecting the core board card and the backboard; and each peripheral module. Each peripheral module comprises a USB module, a serial port module, a network module, an output driving module, an isolation communication module and a B code circuit module. According to the method, the compatibility can be improved, the complexity and cost of system upgrading are reduced, and the flexibility of technical iteration is improved.

The invention discloses an optical interconnection simulation method and system based on full-link parameter optimization, and the method comprises the steps: processing an original signal based on a coding module, a first feed-forward equalizer and a continuous-time linear equalizer, and obtaining a to-be-processed electric signal; modulating and converting the to-be-processed electric signal into a to-be-sent optical signal through a driving circuit, and sending the to-be-sent optical signal through an optical channel; sensing a to-be-sent optical signal through a photodiode to obtain a to-be-received electric signal, and processing the to-be-received electric signal through a trans-impedance amplifier to obtain a to-be-recovered electric signal; and processing the electric signal to be recovered through an automatic gain control continuous time linear equalizer, a decision feedback equalizer and a second feed-forward equalizer to obtain a target receiving signal corresponding to the original signal. The problem of collaborative optimization of electric-optical-electric link distortion compensation and noise suppression in the high-speed optical interconnection system is solved, and the simulation precision is improved to the transmission scene verification requirement of single wave 200Gbps (the data rate of transmitting 200gigabit bit per second) or above.

The invention provides a data stream processing method for binding a kernel and a network card queue, and relates to the technical field of data stream processing, and the method comprises the following steps: setting the number of queues of each gigabit network card and each 10-gigabit network card as the maximum number of queues supported by each network card and the minimum number of idle CPU (Central Processing Unit) cores; binding each queue of each gigabit network card and each 10-gigabit network card to an idle CPU core; the number of queues of each gigabit network card is set to be the minimum value of the maximum number of queues supported by each gigabit network card and the number of idle CPU cores, and the number of queues of each 10-gigabit network card is set to be the minimum value of the maximum number of queues supported by each 10-gigabit network card and the number of idle CPU cores; enabling each queue to process a corresponding data stream through an idle CPU; according to the invention, the problems of non-intelligent and unbalanced resource allocation and possible configuration failure in a mixed rate network card environment are effectively solved.

The invention discloses an ASIC chip for high-performance AOIP network audio stream transmission, and the interior of the chip comprises a function simulation circuit subsystem, a sensor controller, a clock, and a reset control module. The high-speed peripheral interface subsystem is arranged on the first bus, the hardware acceleration subsystem is arranged on the second bus, the low-speed peripheral interface subsystem is arranged on the third bus, the second bus is connected with the first bus and the third bus, and the function simulation circuit subsystem is connected with the third bus through the sensor controller; the hardware acceleration subsystem comprises a plurality of processor cores, two gigabit or 100M bit medium independent interfaces and a real-time transport protocol RTP transceiving engine; the two gigabit or 100M bit medium independent interfaces are compatible with the simplified medium independent interface, one of the two gigabit or 100M bit medium independent interfaces is used as a main network interface, and the other one is used as a standby network interface. The reliability problem of AOIP network audio stream transmission is solved.

The invention provides a sensor array data transmission method which is applied to an FPGA, the FPGA is provided with a PDM digital interface and a DVP digital interface, multichannel PDM signal streams output by a digital sensor array are received through the PDM digital interface, the multichannel PDM signal streams are converted into multichannel PCM data streams in a synchronous digital modulation mode, and the multichannel PCM data streams are transmitted to the FPGA through the DVP digital interface. Dynamic fragmentation compression processing is carried out on the multi-channel PCM data flow through an equal probability sampling method; the method comprises the following steps: receiving a video data stream output by an image sensor through a DVP digital interface, and compressing the video data stream through a H264-like video data compression method; the multi-channel PCM data stream is subjected to combined coding, the coded PCM data stream is interspersed in the compressed video data stream through an interpolation method, and the coded PCM data stream and the compressed video data stream keep time synchronization; and packaging and uploading the interspersed and mixed data flow to a cloud server through a gigabit network communication protocol.

In various embodiments, the present disclosure includes a system for sending 50 gigabits per second (Gbps), 75 Gbps, and 100 Gbps at 50 gigabaud (GBaud) for passive optical networks (PON) downstream and upstream. The system allows for transmission of three data rates at a single baud-rate while only using 2-bits of information per sample. A motivation for sending three data rates at a single baud-rate is to allow for further granularity in the control of the data-rates for downstream and upstream traffic in a flexible PON system based on the link margin. For example, the system can use non-return-to-zero (NRZ) at 50 GBaud for 50 Gbps and can use four-level pulse-amplitude modulation (PAM-4) at 50 GBaud for 100 Gbps. In addition for 75 Gbps, a double square-8 (DSQ-8) constellation can be used at 50 GBaud.

The utility model discloses a network encryption control module with a protection structure, comprising an encryption control module which is internally provided with a hardware sub-module and a software sub-module. The hardware sub-module is internally provided with a ZYNQ7020 processor, an external interface, a debugging interface, a socket XS1, a socket XS2, a socket XS3, a reset key, a power supply, a power supply state indicating lamp, a conversion chip, a gigabit PHY and a gigabit transformer. According to the network encryption control module with the protection structure, the XC7Z020-3CLG484I processor realizes the functions of four paths of Ethernet and the like; by arranging the main control IP address module, the audio and video IP address module, the telephone IP address module, the unvarnished transmission mode module, the ad hoc network encryption mode and the access network encryption mode, the problem that in a specific environment, the network is encrypted by a large-capacity memory and abundant external interfaces and convenient debugging interfaces is solved. The network encryption control module selectively carries out encryption or unvarnished transmission on voice, data and other information transmitted by the wireless ad hoc network.

The present disclosure relates to a monolithically integrated dual-wavelength transmitter for a passive optical network (PON), which may be suitable for both a gigabit PON (GPON) and a 10-gigabit-PON (XG-PON). The integrated transmitter includes two distributed feedback (DFB) lasers, a first DFB laser to emit a continuous first laser beam at a first wavelength along an optical path, and a second DFB laser to emit a modulated second laser beam at a second wavelength along the optical path in the same direction as the first DFB laser. The transmitter also includes an electro-absorption modulator (EAM) after the first DFB laser in the optical path, which is configured to modulate the first laser beam, and a distributed Bragg reflector (DBR) between the EAM and the second DFB laser in the optical path, which is configured to transmit light at the first wavelength