26 results about "Protocol overhead" patented technology

The invention relates to the technical field of computers, discloses a heterogeneous computing low-delay communication method and system, and aims to solve the problem of high delay caused by high communication protocol overhead, lack of dynamic scheduling collaboration, memory migration redundancy and non-uniform cross-node communication abstraction in existing heterogeneous computing. The method comprises the following steps: receiving a task scheduling request and analyzing a task dependency graph; tasks are dynamically allocated based on node loads and link states; rDMA, NVLink or PCIe straight-through protocols are adaptively selected according to node types to establish communication channels; zero-copy data exchange is realized through a shared memory mapping buffer area; hardware timestamps are utilized to synchronize feedback delays with PTP to optimize scheduling. The system comprises a heterogeneous computing node cluster, a unified communication scheduling controller, a low-delay communication protocol stack, a shared memory mapping buffer area and a communication delay sensing task distributor. According to the scheme, the communication delay is remarkably reduced, and the throughput and the task execution efficiency are improved.

The invention provides a method for testing the communication bandwidth of a 10-gigabit network between an FPGA (Field Programmable Gate Array) and a CPU (Central Processing Unit), which is applied to a radar system. The FPGA completes a function of regularly generating data and a function of downlink transmission of the data; the 10-gigabit network exchange board card completes data transmission and sends data to the CPU board card through a 10-gigabit network; and the CPU board card receives the data and calculates the communication bandwidth and the network quality. According to the invention, the limitation of traditional single-port point-to-point transmission or simple multi-port parallel transmission on synchronization, load balancing or protocol overhead is solved, and a solution is provided for how to effectively utilize multiple ports, enable the multiple ports to simultaneously and efficiently work and ensure parallel transmission of data without mutual interference.

The invention belongs to the technical field of network communication, and discloses a service network message cross-domain transmission method and system based on SRv6SID function extension. According to the method, a service network identifier is embedded in an Args field of the SRv6SID, the service network identifier comprises a service network type (TYPE) and a service virtual group tag (VGT), and service awareness transmission of a cross-domain network is realized in combination with an intelligent routing decision driven by deep reinforcement learning. Compared with the prior art, the protocol compatibility can be ensured, the transmission delay and the protocol overhead can be remarkably reduced, the transmission flexibility, the high efficiency and the customizability of the service network message among different network domains can be improved, and the method and the device are suitable for scenes such as 5G, industrial internet and the like.

The invention relates to the technical field of network communication, and provides a real-time data pushing method for binary format transmission data, and the method comprises the steps: S1, judging whether to start server pushing or not through a pushing decision engine; s2, when the server receives sensor data, converting the structured data into HTTP / 2 frames with priority marks through a binary encoder; s3, scheduling an HTTP / 2 frame transmission sequence through a flow controller according to a current network state, wherein the current network state at least comprises a data volume which can be currently received by the client; and S4, after receiving the HTTP / 2 frame, the client sends a preset confirmation frame to confirm receiving according to the HTTP / 2 frame serial number, and if the server does not receive the preset confirmation frame within the preset timeout time, the server marks that the HTTP / 2 frame is lost and re-uploads the HTTP / 2 frame marked as lost. Compared with WebSocket, the method has the advantages that the protocol overhead is reduced, the transmission efficiency is improved, the average delay of key data is reduced, and the method is compatible with the existing HTTP / 2 client.

The invention discloses a load balancing-oriented airborne missile group multipath reliable routing method, which belongs to the technical field of air combat platform group network communication, and comprises multipath routing generation and multipath routing service forwarding of a QoS (Quality of Service)-based comprehensive state model, the route searching comprises the step of searching a first route between a given source node and a target node pair through an OLSR (Open Link Scheduling Route) protocol; all links on the known route are eliminated, and route searching is carried out again; and eliminating the link with the maximum load on the known route, and searching the route again. According to the airborne missile group multipath reliable routing method oriented to load balancing, multipath routing is realized by properly increasing protocol overhead, so that network load balancing is realized. Meanwhile, under the condition of enemy interference, a multi-path routing mode is adopted to replace an interfered link, and reliable transmission of core information of the backbone node is ensured.

The embodiment of the invention provides a data packet transmission method, system, equipment and device and a storage medium. The data packet forwarding equipment supports a CXL protocol, and the data packet transmission method applied to the data packet forwarding equipment comprises the following steps: in response to receiving a data packet from sending equipment, storing the data packet in a cache corresponding to the sending equipment, the cache being pre-allocated to the sending equipment; and in response to a received data packet reading request from receiving equipment, triggering the receiving equipment to read the data packet from the cache in a memory access manner. Visibly, by adopting the technical scheme, the data packet is transmitted on the basis of read-write operation of the sending device and the receiving device on the cache based on a CXL protocol shared memory mode, an interface between devices does not need to be called depending on a driving program, and the data packet does not need to be packaged into a network data packet format for transmission, so that the overhead of a communication protocol can be reduced, and the communication efficiency is improved. Transmission delay is reduced, and transmission performance is improved.

The application provides an IPv6 message encryption and decryption method based on a quantum key application mechanism, which is realized by a sending end and a receiving end in cooperation, and the sending end and the receiving end exchange roles when transmitting back to realize the encryption transmission of messages in the opposite direction by the same processing procedure; the messages are directly encrypted by using quantum keys, and the message encapsulation uses the extensible characteristics of the IPv6 protocol, and a new extension message header is added in the header of the IPv6 message to record the parameters used for message encryption. The combination of the quantum key encryption and the message of the IPv6 is the innovation point in the application, the quantum key is directly used for encryption when the message is encrypted and decrypted, other key negotiation methods are not needed, and other network protocol negotiation keys are not needed, so that the scheme is safer and simpler. The application encapsulates the encrypted message by using the extensible characteristics of the IPv6 protocol, so that the encrypted message is still a standard IPv6 message, and the messages of the whole scheme follow the IPv6 protocol without additional protocol overhead.

The invention discloses a master-slave mode dynamic channel assessment frequency hopping method based on SX1262, and belongs to the technical field of wireless communication. According to the method, communication connection is established through a master node and slave nodes, RSSI, SNR and CAD states of all candidate frequency points are obtained in real time through an SX1262 chip, 100 pieces of historical data serve as a cache, basic quality, RSSI stability, CAD interference and timeliness trend four-dimensional scoring is conducted on 13 candidate frequency points, an optimal frequency point pool is screened out, two non-adjacent high-quality frequency points are randomly selected, and the optimal frequency point pool is obtained. And synchronous frequency hopping communication of the master and slave nodes is realized. Meanwhile, a set of simplified self-defined communication protocol is designed, a master node sends 128 bytes of frames, slave nodes respond to 4 bytes of frames, and protocol overhead is remarkably reduced. Compared with the prior art, the optimal communication frequency point can be adaptively selected in a complex interference environment, the communication reliability is effectively improved, the power consumption is reduced, the spectrum utilization rate is improved, and the method is widely applied to a low-power-consumption wide-area Internet of Things scene.

This application relates to the field of computer technology and discloses a low-latency communication method and system for heterogeneous computing, aiming to solve the high latency problems caused by high communication protocol overhead, lack of dynamic scheduling coordination, redundant memory migration, and inconsistent cross-node communication abstractions in existing heterogeneous computing. The method includes: receiving task scheduling requests and parsing task dependency graphs; dynamically allocating tasks based on node load and link status; adaptively selecting RDMA, NVLink, or PCIe passthrough protocols to establish communication channels according to node type; achieving zero-copy data exchange through a shared memory mapping buffer; and utilizing hardware timestamps and PTP synchronization to provide latency feedback and optimize scheduling. The system includes a heterogeneous computing node cluster, a unified communication scheduling controller, a low-latency communication protocol stack, a shared memory mapping buffer, and a communication latency-aware task allocator. Through the above scheme, this application significantly reduces communication latency and improves throughput and task execution efficiency.

This invention relates to a method and system for implementing a DSMC communication interface between an RK3576 ARM and an FPGA. The system initiates DMA transfer and specifies the data read location on the ARM side, while the FPGA initializes the input port and bidirectional data bus. The ARM side sends the read address, and the FPGA performs clock conversion, chip select signal processing, and clock counting. It detects the read operation flag and switches the bus to output mode. The DRAM module reads data and returns it to the FPGA side, and the ARM side receives the data via DMA. The FPGA side dynamically identifies the transmitted data length and ensures clock synchronization to complete the data transmission. This invention solves the problems of high DSMC bus protocol overhead and low transmission bandwidth. By optimizing clock management and data transmission processes, it significantly improves bus bandwidth utilization, reduces transmission latency, and enhances system flexibility and data transmission efficiency, making it suitable for high-speed data transmission scenarios.

The invention discloses an equipment communication method and system based on a limited message transmission protocol, a terminal and a storage medium, and the method comprises the steps: obtaining an equipment communication task of a user, carrying out the analysis and processing, obtaining a task analysis result, and judging whether the equipment communication task is resource limited equipment communication or not; if the communication is the resource limited device communication, acquiring a limited message transmission protocol, and performing protocol stack construction according to the limited message transmission protocol to obtain a limited message transmission protocol stack architecture; and obtaining a to-be-communicated message of the first device, performing format processing on the to-be-communicated message according to the limited message transmission protocol stack architecture to obtain a target to-be-communicated message, and transmitting the target to-be-communicated message to the second device. According to the method and the device, the limited message transmission protocol is obtained by using the simplification processing to carry out communication between the devices, so that the protocol overhead and the analysis complexity are reduced, the resource consumption is reduced, the security is ensured, and the communication efficiency is improved.

The invention discloses a flow control method and device based on an AXI bus, a medium and a product, and the method comprises the steps: obtaining a first credit value needed by the calculation of a matched first data volume before a write address and write data are continuously sent to a first opposite-end chip in a multi-chip system; and querying a locally maintained target write operation counter matched with the first opposite-end chip, judging whether the current credit value is greater than or equal to the first credit value, if so, updating and storing a calculation result obtained by subtracting the first credit value from the current credit value in the target write operation counter, and continuously sending the write address and the write data to the first opposite-end chip. Whenever target write response information fed back by the first opposite-end chip is received, a first release credit value is obtained, and a result obtained by adding the current credit value and the first release credit value is updated and stored in the target write operation counter. According to the technical scheme, a special signaling packet can be avoided, the protocol overhead is reduced, and the link utilization rate and the system throughput are greatly improved.

A receiver receives a first message including a first PDCP SN. The receiver may receive a second message including a second PDCP SN. The receiver may derive a second RTP SN based on at least one of a first RTP SN of the first message, the first PDCP SN, the second PDCP SN, or an RTP SN field of a second PDCP header composing the second message.

The invention provides a data processing method, system and device, and belongs to the technical field of computer communication, the data processing system comprises: a terminal device used for recording and storing current operation data and a current timestamp generated by the terminal device as a piece of historical data when a network is in an offline state; if the network recovers to the online state, generating a historical data message based on the at least one historical data record; sending the historical data message to a platform; the platform is connected with the terminal equipment through a communication network and is used for receiving a data message sent by the terminal equipment; if the initial register address is a first initial register address, determining the number of historical data records according to the value of the register count field and the preset register length of a single historical data record; and analyzing the timestamps and the operation data of the number of historical data records from the data area and storing the timestamps and the operation data. On the premise of keeping an original simple protocol unchanged and not increasing protocol overhead, offline data tracing can be realized.

The invention discloses a Beidou global short message communication bidirectional authentication method, which enables a satellite and a user terminal to be mutually authenticated, ensures the legality of the satellite and the terminal participating in communication, and belongs to the technical field of navigation satellites. The method provided by the invention is divided into a first access authentication process and an authentication process after switching the visible relationship between the satellite and the user, the Beidou No.3 global short message service is fully utilized, the security is higher, and the authentication after switching is realized through cooperation among satellites, so that the problems of high protocol overhead and increased delay caused by visible switching are avoided.

Implementations for verifying integrity of encryption engines in a UALink-based network. A device comprising a port encryption engine calculates a CRC value over plaintext content of a message before encryption, encrypts the CRC value using a portion of an encryption keystream that follows the portion used for message encryption, producing an encrypted CRC, and computes an authentication tag over the encrypted content and the encrypted CRC. The encrypted CRC does not increase bandwidth consumed by the message. At a receiving device, a CRC is independently recalculated from decrypted content, encrypted using a corresponding keystream portion, and compared via authentication tag verification. A fault in either the encryption engine or a decryption engine at the receiving device causes an authentication tag mismatch, enabling detection of internal crypto engine faults without additional protocol overhead. Implementations may apply to accelerators, switches, integrated circuits, and active cables in the UALink-based network.

The invention relates to an implementation method and system based on a DSMC communication interface between an RK3576 ARM (Advanced RISC Machines) and an FPGA (Field Programmable Gate Array). According to the system, DMA transmission is started through an ARM end, a data reading position is specified, and an input port and a bidirectional data bus are initialized through an FPGA end. The ARM end sends a read address, the FPGA end performs clock conversion, chip selection signal processing and clock counting, detects a read operation mark and switches a bus into an output mode, the DRAM module reads data and returns the data to the FPGA end, and the ARM end receives the data through the DMA. And the FPGA end dynamically identifies the transmission data length and ensures clock synchronization to complete data transmission. According to the method, the problems of high protocol overhead and low transmission bandwidth of the DSMC bus are solved, the utilization rate of the bus bandwidth is remarkably improved, the transmission delay is reduced, the flexibility of the system and the data transmission efficiency are enhanced by optimizing the clock management and data transmission process, and the method is suitable for a high-speed data transmission scene.

The invention discloses a data processing method, device and equipment and a computer readable storage medium, and belongs to the technical field of computers. The method comprises the following steps: acquiring a plurality of sub-functions, wherein the plurality of sub-functions are obtained by decomposing a calculation function located in a modulo 2k ring; the multiple sub-functions are mapped to a Galois ring from a modulo 2k ring, first data and second data are calculated through the mapped sub-functions, ciphertext information corresponding to the second data is obtained based on a calculation result, at least two mapped sub-functions are located on the same Galois ring, and the first data and the second data are calculated in parallel; and sending the ciphertext information to the second equipment. As the calculation function is located in the modulo 2k ring, a calculation protocol defined on the modulo 2k ring can be used in the process of processing the first data and the second data by using the calculation function, and the calculation protocol overhead is low. According to the method, multiple sub-functions are mapped to the same Galois ring, and then the mapped sub-functions are calculated in parallel, so that the data processing efficiency is improved.

The present application belongs to the field of computer storage, and relates to an NVMe transmission optimization method and system. A PI buffer area with continuous physical addresses is set up at the host end, and PI metadata of protection information corresponding to multiple continuous I / O requests are continuously stored; a metadata prefetch indication field and a metadata prefetch depth field are added by extending the NVMe write command DWORD 12 reserved bit. When the NVMe device parses the write command, if the prefetch indication is prefetch enabled, the PI metadata of the current and subsequent multiple I / Os are read in batches according to the prefetch depth through a PCIe transaction and temporarily stored in the internal buffer area of the NVMe device; if it is a buffered read mode, the PI is directly obtained from the buffer area; if it is no prefetch, it is processed in a conventional manner. Through the metadata aggregation transmission and intelligent prefetch strategy, the present application reduces the number of PCIe transactions, reduces the protocol overhead, improves the bandwidth utilization, and is compatible with the existing NVMe protocol.

The invention provides a data transmission method and device and a storage medium, and the method is applied to ground terminal equipment, and comprises the steps: obtaining a plurality of protocol header fields in a protocol header structure according to the protocol header structure corresponding to a preset satellite communication protocol, obtaining the field parameter of each protocol header field according to a to-be-transmitted load message, and transmitting the to-be-transmitted load message to the ground terminal equipment; and generating a to-be-transmitted data packet according to the field parameter of each protocol header field and the to-be-transmitted load message, and sending the to-be-transmitted data packet to the high-orbit satellite, so that the high-orbit satellite forwards the to-be-transmitted data packet to a target application service platform corresponding to the ground terminal equipment through the equipment management platform. Therefore, a compact protocol head structure is adopted, the protocol overhead is reduced, and the bandwidth utilization rate and the effective data transmission rate are improved.

The invention discloses a link limit test system and method based on a PCIe straight-through loopback and a virtual driver, and the system comprises a user-defined PCIe device which is internally provided with an FPGA chip and is used for achieving PCIe physical layer communication and data packet primitive-level loopback without DDR cache; the virtual driving module runs in a kernel mode of an operating system at a PC (Personal Computer) end, and directly controls a BAR (Block Augmented Reality) space of the PCIe equipment through DMA And the user mode test tool is used for triggering a test process, collecting performance data, supporting a user-defined test script and generating a performance report. By bypassing disk I / O, the test error is reduced to be within + / -1.5% from + / -5%. According to the virtual drive, the I / O stack delay of the operating system is reduced from the millisecond level to the microsecond level, the protocol overhead brought by any packet length of 64B-1 MB can be independently evaluated, and a quantitative basis is provided for chip level optimization. Compared with an oscilloscope scheme, the hardware cost is reduced by 60%.

The invention discloses a high-performance packet transmission method, which comprises the following steps of: designing a physical layer, reducing the size of a processing unit LDU through the physical layer, reserving protocol overhead, and achieving the purpose of quick transmission without waiting for the transmission of a whole TB (Transport Block) block; a protocol layer is designed, the protocol layer is divided into an LDU layer and a UDU layer, the LDU layer is used for defining a 3-byte LDU head Type1 and reducing protocol overhead, the UDU layer is used for defining a 5-byte UDU head Type2, and a load is user data to be transmitted; fragmentation and recombination, including a fragmentation mechanism and a recombination mechanism; the transmission process comprises a sending mode and a receiving mode. According to the method, the physical layer and the protocol layer are combined, and the throughput and time delay requirements are met under the high throughput and small packet multi-scene.

The invention discloses a credit management method and system for cross-DIE data transmission flow control. The credit management method comprises the following steps: (1) establishing a double-credit pool structure; (2) a remote credit management process; and (3) a local credit management process. The credit management system comprises a cross-DIE interface module, a credit management module, a protocol processing module and a buffer queue management module. According to the invention, the bidirectional flow control of various types of data transmitted across DIE is realized, and the protocol overhead is reduced on the premise of ensuring the flow control effect.

The invention relates to the technical field of network communication, in particular to an ultra-low delay information transmission device and method based on an FPGA (Field Programmable Gate Array) network, and the device comprises a sending end physical layer which is used for constructing real-time information into a real-time data packet; the switch is connected with the sending end physical layer and is used for broadcasting the real-time data packet; and the receiving end physical layer is connected with the switch and is used for receiving and releasing the real-time data packet and issuing the released real-time data packet to the target link layer. Therefore, the problems that in the prior art, an FPGA network (including a time network, a data network and the like) and a private network need to be deployed in parallel, and complexity and cost are high; information is transmitted based on an Ethernet frame structure, so that logic processing delay is caused, and theoretical minimum delay cannot be approached; and an adopted standard frame structure contains a large amount of protocol overhead (such as MAC addresses and check fields), occupies bandwidth resources, and is low in bandwidth utilization rate.

A method, apparatus and computer-readable medium for transmitting a medium access control (MAC) protocol data unit (PDU) including one or more MAC service data units (SDUs) of a logical channel; and transmitting a first type of MAC subheader including or excluding first logical channel identifier (LCID) information and including or excluding first length information, wherein a first size of the first LCID information is equal to or smaller than a second size of second LCID information of a second type of MAC subheader that is different than the first type of MAC subheader, and a third size of the first length information is equal to or smaller than a fourth size of second length information of the second type of MAC subheader.

This disclosure provides a data processing method, system, and apparatus, belonging to the field of computer communication technology. The data processing system includes: a terminal device used to store the current running data and current timestamp generated by the terminal device as a historical data record when the network is offline; if the network returns to online status, generating a historical data message based on at least one historical data record; sending the historical data message to a platform; and a platform connected to the terminal device via a communication network for receiving the data message sent by the terminal device; if the starting register address is a first starting register address, determining the number of historical data records based on the value of the register count field and the preset register length of a single historical data record; and parsing and storing the timestamps and running data of the specified number of historical data records from the data area. This system enables offline data traceability while maintaining the original simple protocol and without increasing protocol overhead.