751 results about "Error check" patented technology

Iterative decoder employing multiple external code error checks to lower the error floor and/or improve decoding performance. Data block redundancy, sometimes via a cyclic redundancy check (CRC) or Reed Solomon (RS) code, enables enhanced iterative decoding performance. Improved decoding performance is achieved during interim iterations before the final iteration. A correctly decoded CRC block, indicating a decoded segment is correct with a high degree of certainty, assigns a very high confidence level to the bits in this segment and is fed back to inner and/or outer decoders (with interleaving, when appropriate) for improved iterative decoding. High confidence bits may be scattered throughout inner decoded frames to influence other bit decisions in subsequent iterations. Turbo decoders typically operate relatively well at regions where the BER is high; the invention improves iterative decoder operation at lower BERs, lowering the ‘BER floor’ that is sometimes problematic with conventional turbo decoders.

A method for detecting control information in a wireless communication system is provided. The method includes checking a cyclic redundancy check (CRC) error by monitoring control channels, determining whether a value of an error check field is equal to a specific value, and, if the value of the error check field is equal to the specific value, detecting the control information on the control channel.

A signal transmission apparatus is connected to a network as one node among a plurality of nodes involved in the network which is provided with an audio signal transmission period for transmitting a plurality of channels of audio signals each transmission cycle and a control data transmission period for transmitting control data of the plurality of the nodes each control cycle by using an idle time period other than the audio signal transmission period. In the signal transmission apparatus, a storage section stores configuration information of the one node. A transmitting section transmits the control data including an error checking code of the configuration information. A receiving section receives request data from another node, the request data requesting the one node for transmission of an information block of the configuration information. A control section controls the transmitting section to transmit the information block in response to the request data.

A semiconductor memory device having an error check and correction (ECC) type error recovery circuit in which disposition of ECC cells is improved. The memory device comprises: a memory cell array including a plurality of normal cell array portions and an ECC cell array portion; an X decoder for selecting one of word lines in the memory cell array, the word lines extending from the X decoder to the memory cell array; an ECC operation circuit for performing error check and correction based on cell data read out from a selected word line, the cell data including data from normal cells and ECC cells of the selected word line. The ECC memory cell array portion is disposed at a location other than the far end of the word lines from the X decoder, that is, the ECC cell array portion is disposed at a location in which read out speed of data from ECC cell or cells does not become the worst speed in the memory device. Therefore, the worst data read out speed can be measured from outside.

A hardware and software implemented, standardize testing, scoring and reporting system has a network interface, being either LAN or the Internet. A test is selected from a library, assigned to a group of examinees, and a record is made of the assignment. The test is available on-line, or downloaded, or both. Downloaded tests are saved as PDF files and printed into booklets. Examinees record answers on bubble sheets, which are scanned at the customer site or shipped to a processing plant. Individual scanned answer sheets provided data for individual scanned records. Scanning software performs an initial auto-correct and then performs an initial check for errors in scanned records. Tests are batched for later inspection. Scanned records with errors are classified as invalid and the test papers are separated. Prompts are generated for a human test paper inspection and scanned record editing. Accepted batches of scanned records are sent to a scanned records server where a second scanned records error check is performed. Prompts are sent to the appropriate scanning station for further human editing of invalid scanned records. Once all records are valid they are scored and the test results stored in a database, which is accessed by a reporting subsystem associated with an on-line server.

A method for detecting an error in data stored in configuration SRAM and user assignable SRAM in a FPGA comprises the steps of providing a serial data stream into the FPGA from an external source, loading data from the serial data stream into the configuration SRAM in response to address signals generated by row column counters, loading data from the serial data stream into the user assignable SRAM in response to address signals generated by row and column counters, loading a seed and signature from the serial data stream into a cyclic redundancy checking circuit, cycling data out of the configuration SRAM and the user assignable SRAM by the row and column counters; performing error checking on the data that has been cycled out of the configuration SRAM and out of the user assignable SRAM by the cyclic redundancy checking circuit, and generating an error signal when an error is detected by the error checking circuit.

A cache controller configured to speculatively invalidate a cache line may respond to an invalidating request or instruction immediately instead of waiting for error checking to complete. In case the error checking determines that the invalidation is erroneous and thus should not be performed, the cache controller protects the speculatively invalidated cache line from modification until error checking is complete. This way, if the invalidation is later found to be erroneous, the speculative invalidation can be reversed. If error checking completes without detecting any errors, the speculative invalidation becomes non-speculative.

This invention relates to an error-check and error-correction code circuit for storages and a method for reading and writing data by it taking matrix G as a logic core including: a decoding process and a coding process and a method for writing in data by this method. Apart from a decoding process and an error correction process, it also includes a coding process, and finally puts forward an error check and correction and coding circuit for realizing said two methods including a decoder, an error-correction circuit, a coding circuit, an interface circuit and related data transmission circuit so as to simplify layout of bottom circuit and speed up operation speed of circuits.

A non-volatile memory chip having SLC blocks acting as a write cache for MLC blocks for high density storage requires constant copying or folding of SLC blocks into MLC blocks. To avoid the time-consuming toggling out and in of the pages of the entire SLC block for ECC checking by a controller chip, only a small sample is checked. An optimal read point for reading the memory cells in the sample of the SLC block is dynamically determined by trying different read points so that the data is read within an error budget. Once the optimal read point is determined, it is used to read the entire SLC block without further error checking. Then the SLC block can be copied (blind folded) to the MLC block with the confidence of being within the error budget.

A processor includes first and second execution cores that operate in a redundant (FRC) mode, an FRC check unit to compare results from the first and second execution cores, and an error check unit to detect recoverable errors in the first and second cores. The error detector disables the FRC checker, responsive to detection of a recoverable error. A multi-mode embodiment of the processor implements a multi-core mode in addition to the FRC mode. An arbitration unit regulates access to resources shared by the first and second execution cores in multi-core mode. The FRC checker is located proximate to the arbitration unit in the multi-mode embodiment.

Integrated circuit memory devices include a memory cell array having therein a plurality of stored data bits and a plurality of parity bits generated from a plurality of write data bits received by the memory device during a write operation. The plurality of stored data bits and the plurality of parity bits may collectively form a word having a length of m+p bits, where m and p are integers. An error check circuit is provided that converts the plurality of stored data bits and the plurality of parity bits into a plurality of syndrome bits (e.g., Si) that designate a location of a bit error in the plurality of stored data bits when compared against the original write data bits. An error correction circuit is provided that uses the plurality of syndrome bits to correct an error in the plurality of stored data bits and generate a plurality of read data bits that match the plurality of original write data bits.

A semiconductor memory device is disclosed which comprises a cell array including a normal data section used for normal data write and read and a parity data section used for check data write and read, the check data being for execution of error check of data as read out of the normal data section, a data buffer for temporal stage of read data from the cell array and write data into the cell array, and an ECC circuit for generating the check data to be stored in the parity data section from write data as input during data writing, and for performing error check and correction of data read out of the normal section based on the data read out of the normal data section and the check data read out of said parity data section during data reading. N-bit parallel data transfer is performed between the data buffer and normal data section whereas m-bit parallel data transfer is done between the data buffer and external input/output terminals (where m and n are integers satisfying m<n).

A solid state storage system having a hierarchy of different control units that systematically process data in a corresponding memory area is disclosed. The solid state storage system includes

• • a first control unit and at least one second control unit. The first control unit distributes and transmits external command signals that are provided from a host interface. The second control unit is controlled by the first control unit and performs an address mapping operation, an error checking/correcting operation, an ad defective block managing operation on a corresponding plurality of memory chips in the memory area.

The invention discloses a method for generating configuration for middleware protocol conversion of the Internet of vehicles. According to the method, the rapid development of a protocol conversion module is realized through configuration, vehicle enterprise communication protocol conversion parameters are added into a configuration tool through reading DBC (DataBase Commander) file description information which is compiled according to the communication protocol of the Internet of vehicles, configuration information is stored in a database, and middleware protocol conversion module codes of the Internet of vehicles are automatically generated by using protocol conversion template files; a vehicle body network is rapidly integrated with other networks, so as to realize the communication of the Internet of vehicles; the configuration tool can automatically generate configuration files and an application framework and carries out error check on the configuration of a user, worker involvement is avoided as much as possible, and the error rate is lowered, so that the stability of the protocol conversion module can be actively improved.

The invention discloses a Chinese text automatic correction method. The method comprises the following steps of: a) inputting a to-be-corrected Chinese text, and performing word segmentation preprocessing on the Chinese text sentence by sentence; b) searching for one-character words, two-character words or disperse strings of three or more than three characters occurring in the text subjected to word segmentation sentence by sentence; c) performing continuous determination on the disperse strings occurring in the text subjected to word segmentation by adopting an N-gram model, and checking text word level errors for each single sentence in combination with a word forming probability of separate characters; and d) constructing an error correction knowledge base to generate an error correction candidate text. According to the Chinese text automatic correction method provided by the invention, the one-character words, two-character words or disperse strings of three or more than three characters occurring in the text subjected to word segmentation are searched for sentence by sentence, the disperse strings occurring in the text subjected to word segmentation are subjected to continuous determination by adopting the N-gram model to determine identification errors, and the error correction knowledge base is constructed to generate the error correction candidate text, so that error checking and correcting processes are combined very well, and the method has the characteristics of high error checking speed and high error correcting efficiency.

Systems and methods are provided for building and implementing formulas. The systems and methods may treat operands in a formula as having a value and a unit type or dimension and may recognize the compatibility of unit types among operands. One embodiment performs automatic error checking of a formula based on the value and dimension of the operands and the expected result. The automatic error checking may be performed to assist a user in defining and building a formula. Another embodiment performs automatic unit conversion based on the value and unit type of the formula's operands. The automatic unit conversion may be performed when applying data to the formula during runtime or execution of an application program.

A system transmits a plurality of media programs in a network. In one embodiment of the invention, a media program distribution system determines a first resource attribute of a first media program and a second resource attribute of a second media program. The distribution system compares the first resource attribute with the second resource attribute to determine a relative value. In turn, the media server assigns a first distribution resource to the first media program and a second distribution resource to the second media program in response to the relative value and applies one of a plurality of transmission modes to each media program in response to the resource attribute and distribution resource type. Examples of distribution resources include unicast, multicast and broadcast channels. Examples of transmission modes include various protocols such as error checking protocols and encoding mechanisms such as codecs.