95 results about "Error check" patented technology

The invention relates to the technical field of text inspection and analysis, in particular to a localized bidding document error inspection method based on a large language model, which comprises the following steps of: constructing a bidding requirement knowledge graph which comprises a plurality of requirement item nodes, the requirement item node attribute comprises requirement content, a chapter to which the requirement item node attribute belongs and an importance level; establishing a preliminary mapping relationship between the requirement item node and the text content set, and generating a structured bidding file parse body; and carrying out double-round model analysis and error checking, generating an error record for the items judged to be not satisfied, and outputting a structured error list comprising the non-satisfied items and reasons of the non-satisfied items. The method improves the accuracy and coverage of error checking, and is especially suitable for checking scenes of bidding and tendering documents with numerous and jumbled contents and various formats.

The invention provides an intelligent guide algorithm system and an intelligent search guide method for an AI configuration tool. Comprising an intention recognition module used for receiving a demand text input by a user and performing multi-modal vectorization processing on the demand text; the intelligent question and answer module is used for generating function description information, operation example information and module mark information according to knowledge entries matched with the demand text when the function category label indicates that the platform has the function category; the AI auxiliary programming module retrieves function description information in an external information source based on the demand text when the function category label indicates that the platform does not have the function category; and the AI configuration judgment module is used for judging the legality of each connection line according to a pre-trained configuration rule model in the process of configuring and dragging the connection lines by the user, and outputting configuration error prompt information when the judgment result is illegal. According to the method, rapid and accurate retrieval, dynamic knowledge expansion, automatic code generation and configuration error real-time verification can be realized.

The invention discloses a self-adaptive integrated navigation method and system based on satellite differential signals, and belongs to the field of integrated navigation, and the method comprises the following steps: carrying out state prediction based on the output of an inertial navigation system; a deviation function is established through sliding window fitting, and effectiveness evaluation and preventive correction are carried out on differential satellite navigation system signals; dynamically adjusting a measurement noise matrix according to the positioning mode and performing residual error verification; carrying out measurement updating by utilizing the deviation passing the verification to obtain an estimated value containing the error of the inertial device so as to carry out closed-loop feedback correction on navigation parameters; and when the satellite signal fails, compensating the inertial navigation system by using the device error parameter in the estimated value and realizing pure inertial recursion. According to the method, the data quality can be improved from the source, the self-adaptive robustness of the system in a complex environment is enhanced, inertial navigation error divergence is continuously inhibited, and the navigation endurance precision under the extreme condition of satellite signal failure is guaranteed.

A memory device includes a memory cell array including normal cell blocks and at least one error correction code (ECC) cell block, which include a plurality of rows; a scrub control circuit configured to perform an error check operation on each of the plurality of rows; and a write-back prevention circuit configured to store, based on local error signals for the normal cell blocks and the at least one ECC cell block during the error check operation, a severe address for a row in which a severe error occurs, and selectively perform a write-back operation on the row corresponding to the stored severe address during the error check operation or a read-modify-write (RMW) operation.

The application discloses an encryption method and device for locating errors, and the method comprises the following steps: based on preset encryption information, encrypting to-be-encrypted data in a pre-created forward encryption process, obtaining ciphertext data and generating an exception; based on the encryption information and the exception, creating a reverse decryption process, and decrypting the ciphertext data in the reverse decryption process to obtain decrypted data; judging whether the decrypted data matches the to-be-encrypted data; if yes, performing a next layer of encryption operation on the ciphertext data; and if no, based on the exception, determining that an error exists in the encryption process of the current layer. The method can locate the encryption level in the encryption process, avoids error checking after completing the entire encryption process, thereby shortening the problem checking time of the developer and improving the efficiency.

Systems, methods, and apparatus for memory management operations in a memory device. In one approach, each of multiple banks in a memory array includes a scrub holding register. Data is scrubbed in the background by moving data from a location in a memory array to the scrub holding register. Data in the scrub holding register is scrubbed by error correction circuitry shared by the multiple banks. Status data is recorded for any writes that occur to the array location during the scrubbing. After scrubbing is complete, some or all portions of the scrubbed data are moved back to the array location. The status data is used to identify those portions to move back.

Error checking of data used in an offloaded operation is disclosed. A remote execution device receives a request from a host to store a data block in a memory region. The data block includes data and host-generated error checking information for the data. The remote execution device updates the data block by overwriting the host-generated error checking information with locally generated error checking information for the data. The data block is then stored in the memory region.

This invention discloses a method, apparatus, and electronic device for handling application layer errors in an operating system, comprising: obtaining the build status of the operating system; performing error checks on the application layer by calling multiple application programming interfaces (APIs) based on the build status to obtain error identifiers; determining the error type of the application layer based on the error identifiers; determining whether to enable a pre-configured error log based on the error type; if so, obtaining error information by enabling the error log; determining the interface information of the API that caused the error during the call based on the error information through a preset interface; and handling the operating system application layer error based on the interface information of the API. This invention improves the efficiency and accuracy of operating system application layer error handling by centrally processing operating system application layer errors through calling multiple APIs.

The present disclosure provides an error checking circuit, comprising: a first generation circuit for generating a read command; and the control circuit is used for reading conventional data in the storage array based on the read command, generating corresponding second verification data based on the conventional data, comparing the second verification data with initial verification data corresponding to the conventional data, and if the second verification data is different from the initial verification data, sending the second verification data to the storage array. If yes, generating an error flag signal of the first state; the second generation circuit is used for receiving the error flag signal and generating a write command based on the error flag signal in the first state; the control circuit is further used for replacing the initial verification data with the second verification data based on the write command.

A universal asynchronous receiver / transmitter includes a transmit register including information to be transmitted, a receive register including received information, a frame error check circuit that evaluates contents of the receive register for a frame error, and a control logic. The control logic routes contents of the transmit register to the receive register. During transmission of the contents of the transmit register to the receive register through a reprogrammable pin, the control logic modifies a bit inversion register to produce modified contents to be provided to the receive register. The modified contents cause a frame error. The control logic determines whether the frame error check circuit detects the frame error.

A memory, a memory operation method, and a storage device are provided. The memory includes multiple banks, multiple error checking circuits, and an error address generation circuit. Each of the banks includes multiple data memory array tiles and an ECC memory array tile. Each of the error checking circuits is configured to separately read stored data and check data from the bank, and generate a corresponding error checking signal based on the stored data and the check data. The error address generation circuit is configured to receive multiple error checking signals from the multiple error checking circuits, and when any one of the error checking signals is at an inactive level, store address information corresponding to an error failing to meet a condition. In this way, an on-die ECC may be employed to pre-identify an error occurring in the memory, and after an error uncorrectable by the on-die ECC is identified, an error checking signal is generated to record error address information in a timely manner, thereby facilitating subsequent correction of the error and improving accuracy of the memory.

Disclosed herein are embodiments of a hearing aid configured to receive a wireless signal including a succession of frames including a first frame including first encoded audio samples, and determine a first codec, perform an error check based on the first frame, and in accordance with a determination that the first frame fails to pass the error check, perform a test.

Disclosed is memory access logic that is operable to perform different accesses to a particular memory element depending on whether or not a memory error checking scheme is being implemented for the memory element. A set of error checking bits are stored in the memory element for implementing the memory error checking scheme. The memory error checking scheme can thus be selectively enabled and memory accesses performed accordingly such that when the memory error checking scheme is enabled, it is ensured that the required error checking bits are accessed.

A semiconductor system includes a controller outputting a chip selection signal and a command address for performing a read operation and then outputting the chip selection signal and the command address for performing an ECS operation, and a semiconductor device including a plurality of memory cells and generating a latch row address and a latch column address by latching the command address when an error occurs in internal data that are output from a memory cell that is selected, among a plurality of memory cells, after the start of the read operation based on the chip selection signal and the command address, determining the priority of the ECS operation for the plurality of memory cells based on the latch row address and the latch column address, and storing the internal data in the same memory cell again by correcting the error of the internal data.

Embodiments of this disclosure relate to analog-to-digital converter circuits, corresponding systems, and methods. In one embodiment, a circuit includes N sensing channels. Each channel includes a pair of first primary sensing nodes and second redundant sensing nodes. N analog-to-digital converters (ADCs) are coupled to the first sensing nodes, wherein digital processing circuitry is coupled to the N ADCs. A pair of multiplexers are coupled to the second sensing nodes and to the N ADCs, wherein another ADC is coupled to the output of the second multiplexer. Error checking circuitry is coupled to the output of the second multiplexer, and the other ADC compares a first digital value with a second digital value at each of a series of N time windows, the digital value being generated by a digital conversion of an analog sensing signal at one of the first sensing nodes and an analog sensing signal at a second sensing node paired with the selected first sensing node.

Systems, methods, and apparatus for memory management operations in a memory device. In one approach, each of multiple banks in a memory array includes a scrub holding register. Data is scrubbed in the background by moving data from a location in a memory array to the scrub holding register. Data in the scrub holding register is scrubbed by error correction circuitry shared by the multiple banks. Status data is recorded for any writes that occur to the array location during the scrubbing. After scrubbing is complete, some or all portions of the scrubbed data are moved back to the array location. The status data is used to identify those portions to move back.

The invention discloses an intelligent electric meter error verification system and method based on a convolutional neural network. The system comprises a frequency test signal generation module which is used for generating a combined voltage test signal with a fundamental wave frequency and a specified harmonic wave; the channel selection switch module is used for selecting power resistors with different powers for discharging; the standard power resistor is used for discharging the combined voltage test signal output by the frequency test signal generation module; the comparison test intelligent electric meter is used for metering the electric energy consumed in the discharge process of the standard resistor; on-site electricity utilization information is collected through a photovoltaic power station on-site intelligent electric meter, and combined voltage test signals with the same information are generated through an intelligent electric meter error verification system based on a convolutional neural network and used for verifying metering errors of the photovoltaic power station on-site intelligent electric meter; electric energy with different frequency components is accurately metered in a standard power resistance mode, and the problem of metering error verification of an intelligent electric meter of a current photovoltaic power station is solved.

A memory subsystem is disclosed. The memory subsystem includes a memory controller and a memory having at least a first rank and a second rank, the first and second ranks being separately addressable from one another. The memory controller is configured to, in response to receiving a write command, determine if corresponding data is to be written to a single rank or to multiple ranks. When written to multiple ranks, data can be read from the multiple ranks, with comparisons being performed for error checking. Data associated with some write commands may be written to only a single rank, forgoing error protection.

The invention relates to an overprinting error detection method for a digital ink-jet printer and a related device, and the method comprises the steps: controlling a nozzle system of the digital ink-jet printer, and spraying a preset test pattern on a printing stock driven by a main shaft; in the process of spraying the test pattern, a position coding signal of rotation of the main shaft is obtained through an encoder linked with the main shaft, and the position coding signal comprises a pulse signal count value and a period count value; through an image acquisition device, acquiring an actual printing image of the printed material which is painted with the test pattern; and analyzing the position coding signal and the actual printing image to obtain error characteristics, and classifying the error into one of a plurality of preset error types based on the error characteristics. The method has the advantages that the printing errors caused by different roots are accurately found out, later maintenance or compensation is facilitated, and the error checking difficulty and the checking time are reduced.

The invention discloses an industrial vehicle node data entry method based on man-machine interaction, and relates to the technical field of automation control, and the method comprises the steps: obtaining the pose data of an industrial vehicle, building a track recording session, forming a track sequence, and recording a bookmark sequence; track and bookmark data are solidified, and time axis and canvas linkage playback is achieved on the same interface; generating candidate points based on the tracks and bookmarks, calculating candidate scores, ranking and presenting the candidate scores in a candidate list, and clicking the candidate points to drive a time axis to jump and position on a canvas; aiming at the positioning candidate points, determining node types, inputting and generating nodes according to minimum necessary fields, enabling node records to be adsorbed to corresponding moments and poses, and writing the node records into a node sequence; track subsequences between adjacent nodes are intercepted according to node moments, track segment constraint fitting is carried out on edges to generate curve parameters, error verification is carried out, if the curve parameters do not pass, rollback and remarking are carried out, and after the error verification, a road network is published and loaded. And the road network quality and the deployment stability are improved through trajectory segment constraint fitting and verification of a rollback closed loop.

The application discloses a kind of light microwave source system and method, the system includes light signal generation module, for generating CPT phenomenon, output optical filtered laser beam;Photodetector, for converting optical signal into electrical signal;Electric signal adjustment module, for amplifying the electrical signal output by photodetector, and carry out beam splitting;Crystal oscillator locking module, including crystal oscillator, for the second road signal after beam splitting is modulated and input to frequency divider, with the signal output by crystal oscillator after frequency division is phase detected and forms error check signal, crystal oscillator locking module generates the microwave signal of the microwave source system;PID control module, for processing error check signal, forms voltage control signal to control voltage control phase shifter.The application has the stability of CPT atomic clock and the advantage of low phase noise of photoelectric oscillator, improves the stability of microwave signal, can provide high-stability and low-phase-noise microwave and time frequency signal.

The invention discloses a list screening method, device and equipment and a readable storage medium, and the method comprises the steps: obtaining a reference list and a to-be-screened target list, and carrying out the standardization processing and semantic enhancement processing; utilizing a machine learning model interpreter and a random forest model, and combining continuously updated historical screening data to determine the dynamic weight of each dimension under different types of entities; after standardization and semantic enhancement processing are completed, the similarity of all dimensions between the two entities of the same type in the target list and the reference list is calculated, weighted stacking is carried out according to corresponding dynamic weights, and the total similarity between the two entities is obtained; and after comparing the total similarity with a threshold value, obtaining screening data of the entities in the target list relative to the reference list by using a comparison result. According to the method and the device, the missing check rate and the error check rate of list screening can be reduced, so that the actual list screening requirement is met.

A codeword is received and stored in a first data structure to be decoded by flipping one or more of a plurality of bits over multiple iterations by a bit flip decoder, an error check is executed on the codeword, by a controller, to identify error bits from the plurality of bits, and the state of an error bit is flipped from one of the identified error bits if parity check (PC) violations associated with the error bit meet or exceed a PC violation threshold associated with a bit flip state of the error bit, where the bit flip state is selected from one of a first bit flip state with a first PC violation threshold and a second bit flip state with a second PC violation threshold different than the first PC violation threshold. The current state of the error bit is stored in a second data structure.

The application provides a kind of composite material automatic feeding device software control method and system, comprising: executing initialization program;Carrying out program error check, judge whether there is program error, in the presence of program error, initialization program is executed in a loop, in the absence of program error, running main program;Running manual program, automatic program and debugging program;Executing manual function, automatic function and debugging function;Executing automatic function and continuous transmission feeding.The application solves the technical problems of low operation precision and low production efficiency caused by relying on manual operation.

Because Kubernetes clusters can be ephemeral, backing up in-cluster data to storage outside the cluster is important. Prior art solutions used the cluster's API server, which facilitates communications with the cluster control plane, to transfer backup data through the API server. However, the API server as a data transfer node has resiliency weaknesses and can slow down backup job performance. The present solution provides a more streamlined and scalable approach, which circumvents the API server and additionally includes more robust error checking, log capture, and realtime job monitoring to provide improved data protection resilience. The disclosed approach employs a “sponsor” data agent outside the cluster and temporarily deploys a specialized backup resource within the cluster during a backup job, such as an enhanced File System Data Agent and / or a lightweight Kubernetes File Client, both of which present substantial performance and resiliency advantages over the API server.

The application provides a method and system for enhancing data transmission reliability based on interleaving. In step A1, a sending end forms a first data by interleaving a to-be-sent original data sequence, and sends the first data to a receiving end. In step A2, the receiving end receives the first data and performs deinterleaving to obtain a second data. In step A3, the receiving end performs error checking on the second data. By the method of interleaving, continuous multiple bit errors in a data frame are dispersed into different data frames or different positions of the data frame, the error checking capability is enhanced, the influence on data quality is reduced, the user experience is improved, and continuous multiple bit errors can be corrected, and the method is applicable to MIPI, HSMT and ASA image transmission protocols.

An aircraft includes engines, electronic engine controllers (EECs) associated with the engines, and a flight management computer (FMC). The FMC includes a non-volatile memory and processor(s) configured to perform one or more error check operations based on engine data from a non-volatile memory of the FMC to determine whether to select an engine thrust rating for a thrust model of the aircraft based, in part, on an engine rating identifier associated with the engine data. The processor(s) may also, or alternatively, be configured to select, based on the plurality of local thrust rating model (TRM) identifiers, intermix thrust model data for use by the FMC during a flight of the aircraft, where the intermix thrust model data is associated with a thrust model identifier that is common to two or more engines of the aircraft.

The present application relates to a kind of data security intelligent verification method, system, electronic equipment and program product based on batch privacy intersection, the method features in it include, the whole amount of data to be compared by participant is uploaded to local;According to sequence, the data field and the verification mode of intersection are selected;The selected data field is spliced, and the spliced field is committed, the commitment value of the spliced field is formed, and the commitment value is specified as new ID column;The new ID column is calculated as the input value of batch privacy intersection calculation;The intersection result is converted into data intelligent verification result, the consistency verification and error check of multiple arbitrary data field are realized.

A memory device is provided. The memory device includes: a memory cell array including a plurality of memory cell rows; a refresh control circuit configured to output a refresh row address to control a refresh operation to be performed on at least one memory cell row among the plurality of memory cell rows; and a control logic circuit configured to receive, from a memory controller, error check and scrub (ECS) setting data corresponding to a mode among a plurality of modes, store the ECS setting data in a mode register, and provide a target row address of a memory cell row to be refreshed to the refresh control circuit based on a value of the ECS setting data in response to a refresh command provided from the memory controller.