155 results about "Error check" patented technology

The invention relates to the technical field of text inspection and analysis, in particular to a localized bidding document error inspection method based on a large language model, which comprises the following steps of: constructing a bidding requirement knowledge graph which comprises a plurality of requirement item nodes, the requirement item node attribute comprises requirement content, a chapter to which the requirement item node attribute belongs and an importance level; establishing a preliminary mapping relationship between the requirement item node and the text content set, and generating a structured bidding file parse body; and carrying out double-round model analysis and error checking, generating an error record for the items judged to be not satisfied, and outputting a structured error list comprising the non-satisfied items and reasons of the non-satisfied items. The method improves the accuracy and coverage of error checking, and is especially suitable for checking scenes of bidding and tendering documents with numerous and jumbled contents and various formats.

A memory subsystem with error checking and scrubbing (ECS) logic on-device on the memory can adapt the rate of ECS operations in response to detection of errors in the memory when the memory device is in automatic ECS mode. The ECS logic can include an indication of rows of memory that have been offlined by the host. The ECS logic can skip the offlined rows in ECS operation counts. The ECS logic can include requests or hints by the host to have ECS operations performed. An internal address generator of the ECS logic can select between generated addresses and the hints. The system can allow a memory controller to detect multibit errors (MBEs) related to a specific address of the associated memory. When the detected MBEs indicate a pattern of errors, the memory controller triggers a row hammer response for the specific address.

The invention discloses a method for rapidly and stably solving a buckling path after multiple critical points based on a generalized displacement control method. The method comprises the steps that S1, a state variable and an anchoring type secant predictor are initialized; s2, predicting a reference displacement, a calibration displacement and a load increment factor based on the state variable and the anchored secant predictor; s3, calculating the displacement increment of the current iteration step based on the reference displacement, the calibration displacement and the load increment factor, and updating the total displacement and the total load of the structure; s4, updating the geometric state of the structure and the internal force of the unit based on the displacement increment of the current iteration step; s5, calculating the difference value between the total internal force and the external load of the structure based on the updated geometric state of the structure and the unit internal force to obtain the unbalanced force of the structure, and performing error checking based on the unbalanced force of the structure; s6, executing the steps S1 to S5 circularly until the unbalanced force of the structure meets the balance condition, and starting the next increment step; and incremental analysis is executed until user requirements are met, and a buckling path after multiple critical points is output.

Memory with enhanced fail tracking, and associated systems, devices, and methods, are disclosed herein. In one embodiment, a memory device comprises a memory array and fail tracking circuitry. The fail tracking circuitry can include a counter and a plurality of memory slots and can be configured to, for each memory row of a plurality of memory rows in a memory region of the memory array, (a) count errors detected in data read from the memory row to determine an error count, and (b) store the error count and address information for the memory row in a memory slot of the plurality of memory slots. In some embodiments, the fail tracking circuitry can be configured to count the errors and store the error counts during error check and scrub operations of the memory device (e.g., to identify the worst memory rows in the memory region for post-package repair operations).

A display system increases a number of supported regions of interest and allowing for a dynamic background image by offloading region of interest calculations and data integrity checks from a display controller to a parallel processor of the display system. The parallel processor calculates a configurable number of regions of interest of a frame and error checks each of the regions of interest before transmitting the frame to the display controller.

A system that includes determining whether an interface between sender and receiver devices is defective. For an interface between a sender device and a receiver device: a configured number of stalls can be injected in a communication from the sender device to the receiver device. Based on the counted number of stalls being less than an injected number of stalls or exceeding the injected number of stalls by more than a threshold level, the interface can be identified as defective with respect to stall state counting. Based on the counted number of stalls being the same as the injected number of stalls or exceeding the injected number of stalls by not more than the threshold level, the interface can be identified as non-defective with respect to stall state counting.

The invention provides an intelligent guide algorithm system and an intelligent search guide method for an AI configuration tool. Comprising an intention recognition module used for receiving a demand text input by a user and performing multi-modal vectorization processing on the demand text; the intelligent question and answer module is used for generating function description information, operation example information and module mark information according to knowledge entries matched with the demand text when the function category label indicates that the platform has the function category; the AI auxiliary programming module retrieves function description information in an external information source based on the demand text when the function category label indicates that the platform does not have the function category; and the AI configuration judgment module is used for judging the legality of each connection line according to a pre-trained configuration rule model in the process of configuring and dragging the connection lines by the user, and outputting configuration error prompt information when the judgment result is illegal. According to the method, rapid and accurate retrieval, dynamic knowledge expansion, automatic code generation and configuration error real-time verification can be realized.

The invention relates to the technical field of material review, and discloses a material review processing platform based on an AI model, and the platform comprises a front-end interaction and display module which is used for receiving application information containing one or more application materials from a user terminal; the AI cognition and processing center is used for receiving the application information and carrying out first-stage dominant error check and second-stage implicit logic risk study and judgment on the application material; and the dominant error verification aims at determining whether the application material has preset dominant errors in the aspects of integrity, format normalization and cross-material data dominant consistency. According to the method and the device, the multi-modal material analysis and dominant error verification functions are set, so that the technical problem that applications are frequently rejected and repeatedly submitted due to the fact that simple form errors exist in applied materials is solved, and the effect of remarkably improving the one-time passing rate of material submission is achieved.

In various examples, systems and methods are disclosed relating to health and error monitoring of sensor fusion systems. Systems and methods are disclosed that aggregate results of monitoring and error checking in a sensor fusion system in a single checkpoint. A processor may include one or more circuits. The one or more circuits may receive perception data from one or more first sensors of a machine. The one or more circuits may receive position data from one or more second sensors of the machine. The one or more circuits may generate output data by performing fusion of at least the perception data and the position data. The one or more circuits may evaluate a plurality of criteria according to at least a subset of the perception data, the position data, and the output data. The one or more circuits may output an error signal according to the evaluation.

The invention discloses a method for determining activation time of a liquid storage type reserve battery, which comprises the following steps: S10, acquiring parameters of a standard-size battery: selecting the standard-size battery as a pilot sample and an independent verification sample, and acquiring an electrolyte infiltration quality-time curve and actual activation time; s20, prediction parameter acquisition: calculating an initial time scaling factor and an initial infiltration quality critical threshold value of the pilot sample according to the electrolyte infiltration quality-time curve and the actual activation time of the pilot sample, and performing error verification by using independent verification sample parameters to obtain a prediction time scaling factor and a prediction infiltration quality critical threshold value; and S30, target battery activation time prediction: according to a target battery electrolyte infiltration quality-time curve, obtaining the time required for the target battery infiltration quality to reach the prediction critical threshold, and calculating the activation time of the target battery in combination with the prediction time scaling factor. The activation time determination method is high in efficiency and good in precision.

The invention discloses a self-adaptive integrated navigation method and system based on satellite differential signals, and belongs to the field of integrated navigation, and the method comprises the following steps: carrying out state prediction based on the output of an inertial navigation system; a deviation function is established through sliding window fitting, and effectiveness evaluation and preventive correction are carried out on differential satellite navigation system signals; dynamically adjusting a measurement noise matrix according to the positioning mode and performing residual error verification; carrying out measurement updating by utilizing the deviation passing the verification to obtain an estimated value containing the error of the inertial device so as to carry out closed-loop feedback correction on navigation parameters; and when the satellite signal fails, compensating the inertial navigation system by using the device error parameter in the estimated value and realizing pure inertial recursion. According to the method, the data quality can be improved from the source, the self-adaptive robustness of the system in a complex environment is enhanced, inertial navigation error divergence is continuously inhibited, and the navigation endurance precision under the extreme condition of satellite signal failure is guaranteed.

A memory device includes a memory cell array including normal cell blocks and at least one error correction code (ECC) cell block, which include a plurality of rows; a scrub control circuit configured to perform an error check operation on each of the plurality of rows; and a write-back prevention circuit configured to store, based on local error signals for the normal cell blocks and the at least one ECC cell block during the error check operation, a severe address for a row in which a severe error occurs, and selectively perform a write-back operation on the row corresponding to the stored severe address during the error check operation or a read-modify-write (RMW) operation.

The application discloses an encryption method and device for locating errors, and the method comprises the following steps: based on preset encryption information, encrypting to-be-encrypted data in a pre-created forward encryption process, obtaining ciphertext data and generating an exception; based on the encryption information and the exception, creating a reverse decryption process, and decrypting the ciphertext data in the reverse decryption process to obtain decrypted data; judging whether the decrypted data matches the to-be-encrypted data; if yes, performing a next layer of encryption operation on the ciphertext data; and if no, based on the exception, determining that an error exists in the encryption process of the current layer. The method can locate the encryption level in the encryption process, avoids error checking after completing the entire encryption process, thereby shortening the problem checking time of the developer and improving the efficiency.

Systems, methods, and apparatus for memory management operations in a memory device. In one approach, each of multiple banks in a memory array includes a scrub holding register. Data is scrubbed in the background by moving data from a location in a memory array to the scrub holding register. Data in the scrub holding register is scrubbed by error correction circuitry shared by the multiple banks. Status data is recorded for any writes that occur to the array location during the scrubbing. After scrubbing is complete, some or all portions of the scrubbed data are moved back to the array location. The status data is used to identify those portions to move back.

Error checking of data used in an offloaded operation is disclosed. A remote execution device receives a request from a host to store a data block in a memory region. The data block includes data and host-generated error checking information for the data. The remote execution device updates the data block by overwriting the host-generated error checking information with locally generated error checking information for the data. The data block is then stored in the memory region.

This invention discloses a method, apparatus, and electronic device for handling application layer errors in an operating system, comprising: obtaining the build status of the operating system; performing error checks on the application layer by calling multiple application programming interfaces (APIs) based on the build status to obtain error identifiers; determining the error type of the application layer based on the error identifiers; determining whether to enable a pre-configured error log based on the error type; if so, obtaining error information by enabling the error log; determining the interface information of the API that caused the error during the call based on the error information through a preset interface; and handling the operating system application layer error based on the interface information of the API. This invention improves the efficiency and accuracy of operating system application layer error handling by centrally processing operating system application layer errors through calling multiple APIs.

The present disclosure provides an error checking circuit, comprising: a first generation circuit for generating a read command; and the control circuit is used for reading conventional data in the storage array based on the read command, generating corresponding second verification data based on the conventional data, comparing the second verification data with initial verification data corresponding to the conventional data, and if the second verification data is different from the initial verification data, sending the second verification data to the storage array. If yes, generating an error flag signal of the first state; the second generation circuit is used for receiving the error flag signal and generating a write command based on the error flag signal in the first state; the control circuit is further used for replacing the initial verification data with the second verification data based on the write command.

A universal asynchronous receiver / transmitter includes a transmit register including information to be transmitted, a receive register including received information, a frame error check circuit that evaluates contents of the receive register for a frame error, and a control logic. The control logic routes contents of the transmit register to the receive register. During transmission of the contents of the transmit register to the receive register through a reprogrammable pin, the control logic modifies a bit inversion register to produce modified contents to be provided to the receive register. The modified contents cause a frame error. The control logic determines whether the frame error check circuit detects the frame error.

Methods, systems, and devices for address error checking using counters are described. A memory system may verify the validity of portions of a mapping table. During an access operation, the memory system may transfer a portion of the mapping table to a volatile memory and may maintain a copy of the portion in non-volatile memory. The memory system may implement a counter for each portion of the mapping table in the volatile memory and the non-volatile memory. The memory system may compare a value of the counter associated with the portion of the mapping table stored to the volatile memory with a value of the counter associated with the portion of the mapping table stored to the non-volatile memory. If the values match, the portion may be considered valid and an access operation using the portion in the volatile memory may be permitted.

A memory, a memory operation method, and a storage device are provided. The memory includes multiple banks, multiple error checking circuits, and an error address generation circuit. Each of the banks includes multiple data memory array tiles and an ECC memory array tile. Each of the error checking circuits is configured to separately read stored data and check data from the bank, and generate a corresponding error checking signal based on the stored data and the check data. The error address generation circuit is configured to receive multiple error checking signals from the multiple error checking circuits, and when any one of the error checking signals is at an inactive level, store address information corresponding to an error failing to meet a condition. In this way, an on-die ECC may be employed to pre-identify an error occurring in the memory, and after an error uncorrectable by the on-die ECC is identified, an error checking signal is generated to record error address information in a timely manner, thereby facilitating subsequent correction of the error and improving accuracy of the memory.

The invention discloses a method for improving the reading speed of a cache supporting ECC (error correction code) error correction, which comprises the following steps of: initiating an RAM (random access memory) reading request by a processor, and if a request address index hits an AEDR (automatic edge data rate) register, comparing multiple groups of data in the AEDR register with the request address and judging whether the AEDR register hits the request address; if the request address index does not hit the AEDR register, outputting a plurality of groups of original data from the cache memory, comparing and judging whether the AEDR register is hit or not, and sending the data to an ECC error correction logic module for ECC verification; and finally, checking the number of multiple groups of original data errors checked by the ECC before the data and the judgment result are output, and respectively executing different operations according to the number of the data errors. According to the method, the selection judgment logic module and the ECC error correction logic module are executed in parallel, so that the data storage reliability of the cache memory is improved, and the data reading efficiency of the processor is improved.

The invention provides an atlas transverse ligament geometric model establishment method, device and equipment and a storage medium, and the method comprises the steps: carrying out ray scanning extraction in an atlas region to obtain a bony structure, carrying out magnetic resonance imaging in the atlas region, and marking a transverse ligament region; preliminarily aligning the transverse ligament area with the bony structure through a feature point marking method; dividing the preliminarily aligned transverse ligament area into grids with a preset size, performing non-rigid matching on each grid and a corresponding area in the bony structure in sequence by using a local affine optimization algorithm, and performing global smoothing processing to obtain a modal alignment area graph; and generating a preliminary three-dimensional model based on the bony structure and the modal alignment area map, and sequentially performing curved surface optimization and error check on the preliminary three-dimensional model to generate a final atlas transverse ligament geometric model. According to the method, advantages of physical characteristics of ray scanning and magnetic resonance imaging are complementary, the imaging limitation of a single mode is broken through, and the construction of the geometric model of the atlas transverse ligament is more accurate.

Disclosed herein are embodiments of a hearing aid configured to receive a wireless signal including a succession of frames including a first frame including first encoded audio samples, and determine a first codec, perform an error check based on the first frame, and in accordance with a determination that the first frame fails to pass the error check, perform a test.

The present invention provides a memory controller and a three-dimensional stacked memory, wherein a read cache area and a prefetch cache area are provided in the memory controller. Each time data is read, it is first determined whether the data to be read has been cached in advance in the prefetch cache area. If not, while reading the corresponding data in the hit layer of the multi-layer memory chip (i.e., the data stored in the hit storage unit), the corresponding data in at least one non-hit layer of the multi-layer memory chip is also read (i.e., prefetched), and error checking and correction are further performed on both the read and prefetched data. After the error checking and correction, the data in the hit layer is cached in the read cache area, the prefetched data is cached in the prefetch cache area, and the data cached in the read cache area is retrieved and returned to the main chip. This realizes the functions of prefetching data from the multi-layer memory chip, performing ECC error correction on the read and prefetched data first, and then caching them separately, thereby improving the reliability of stored data and system performance.

Systems and methods are provided for implementing system object tracking for rule violation detection. In various examples, in response to a trigger event, a computing system may track a system object by tracking a tracker object corresponding to a memory address range of a database that has been allocated to the system object. Contemporaneous with the trigger event, the computing system determines, based on tracking of the tracker object, whether a system rule associated with the system object has been violated. Based on a determination that a system rule associated with the system object has been violated, the computing system triggers at least one action associated with the system object, including performing a contemporaneous error check, sending messages indicating an error caused by violation of the system rule, identifying a system component or driver that caused the error, and / or causing an immediate system crash.

Disclosed is memory access logic that is operable to perform different accesses to a particular memory element depending on whether or not a memory error checking scheme is being implemented for the memory element. A set of error checking bits are stored in the memory element for implementing the memory error checking scheme. The memory error checking scheme can thus be selectively enabled and memory accesses performed accordingly such that when the memory error checking scheme is enabled, it is ensured that the required error checking bits are accessed.

A semiconductor system includes a controller outputting a chip selection signal and a command address for performing a read operation and then outputting the chip selection signal and the command address for performing an ECS operation, and a semiconductor device including a plurality of memory cells and generating a latch row address and a latch column address by latching the command address when an error occurs in internal data that are output from a memory cell that is selected, among a plurality of memory cells, after the start of the read operation based on the chip selection signal and the command address, determining the priority of the ECS operation for the plurality of memory cells based on the latch row address and the latch column address, and storing the internal data in the same memory cell again by correcting the error of the internal data.

Embodiments of this disclosure relate to analog-to-digital converter circuits, corresponding systems, and methods. In one embodiment, a circuit includes N sensing channels. Each channel includes a pair of first primary sensing nodes and second redundant sensing nodes. N analog-to-digital converters (ADCs) are coupled to the first sensing nodes, wherein digital processing circuitry is coupled to the N ADCs. A pair of multiplexers are coupled to the second sensing nodes and to the N ADCs, wherein another ADC is coupled to the output of the second multiplexer. Error checking circuitry is coupled to the output of the second multiplexer, and the other ADC compares a first digital value with a second digital value at each of a series of N time windows, the digital value being generated by a digital conversion of an analog sensing signal at one of the first sensing nodes and an analog sensing signal at a second sensing node paired with the selected first sensing node.

The invention discloses a high-speed uplink data injection storage and forwarding system and method, a medium and equipment, and belongs to the technical field of spacecraft data transmission. The system comprises a data receiving and transmitting module, a data storage module and a data control module, wherein the data receiving and transmitting module receives an input number through an RS422 or LVDS differential interface and transmits the input number to a load, the RS422 is used for a long distance and a low rate, and the LVDS is used for a high rate; the data storage module stores data in a nonvolatile memory according to the ratio of the virtual channel identifier to the effective data of 1: 256; and the data control module performs CRC verification on the remote control frame, extracts a virtual channel identifier in the dominant header to determine a distribution port, and realizes flow control through an adjustable sending interval. The method comprises the steps of receiving and analyzing data, extracting and storing verification identifiers and distributing the verification identifiers according to instructions. According to the method, accurate multi-load distribution and link multiplexing are realized through the virtual channel identifier, the port occupation of the spacecraft is reduced, the reliability is improved by combining differential transmission and error code check, and the method is suitable for a multi-load on-orbit reconstruction scene.

The invention provides an error checking and correcting circuit and a memory, and the circuit comprises a first time sequence regulation and control circuit, a second time sequence regulation and control circuit, a reading amplification circuit, an operational circuit, a time sequence matching circuit and a latch circuit, the time delay and the wiring time delay of the first time sequence regulation and control circuit, the reading amplification circuit and the operation circuit are matched through the second time sequence regulation and control circuit and the time sequence matching circuit, so that the time delays of control signals and operation time in the circuits are basically close under different process angle, voltage and temperature conditions, and the waiting time can be shortened; the read-out error correction efficiency of the circuit is improved while asynchronous data signal acquisition is completed, the circuit structure is simple, the used circuit area is small, and the time sequence matching circuit does not involve winding on the circuit layout, so that the time delay effect close to the circuit can be obtained on the premise that wiring matching is not performed, and the circuit reliability is improved. And meanwhile, a part of area is saved, and the flexibility is improved.