247 results about "Error check" patented technology

An apparatus for correcting an error of a clock signal may include a phase adjuster that corrects an error of half-rate clock signals based on an error correction signal to output an error-corrected clock signal, a phase splitter that outputs quadrature clock signals from the error-corrected clock signal, an error detector that outputs an internal clock signal based on one of the quadrature clock signals, selects two quadrature clock signals among the quadrature clock signals based on a clock selection signal, and detects errors of the two quadrature clock signals based on an error check signal to output a correction request signal, and a controller that outputs a mode selection signal and the clock selection signal based on the internal clock signal and that outputs the error correction signal and the error check signal based on the mode selection signal, the clock selection signal, and the correction request signal.

The invention relates to the technical field of text inspection and analysis, in particular to a localized bidding document error inspection method based on a large language model, which comprises the following steps of: constructing a bidding requirement knowledge graph which comprises a plurality of requirement item nodes, the requirement item node attribute comprises requirement content, a chapter to which the requirement item node attribute belongs and an importance level; establishing a preliminary mapping relationship between the requirement item node and the text content set, and generating a structured bidding file parse body; and carrying out double-round model analysis and error checking, generating an error record for the items judged to be not satisfied, and outputting a structured error list comprising the non-satisfied items and reasons of the non-satisfied items. The method improves the accuracy and coverage of error checking, and is especially suitable for checking scenes of bidding and tendering documents with numerous and jumbled contents and various formats.

The invention discloses privacy protection query language PQL and system thereof, comprising PQL statement and system, the system comprises parsing module, query module and noise-injection module; the parsing module comprises lexical analyzer and syntactic analyzer; user inputs PQL statement according to predetermined semantic and syntactic rules, after parsing module receives the PQL statement, lexical analyzer performs error checks on the PQL statement, correct results are sent to syntactic analyzer; the syntactic analyzer performs grammatical and semantic checks on PQL statement, generates a mapping table and a parameter table with correct results; after receiving mapping table, the query module encapsulates the same into SQL statement, and verifies the encapsulated SQL statement; the noise-injection module obtains final query results of the query module, calculates noise injection sensitivity according to parameter table; the invention ensures the data privacy security and satisfies that the injected noise does not affect data availability.

The embodiment of the invention provides an internal error checking circuit and a memory. The internal error checking circuit comprises a clock generation circuit, an internal command generation circuit, an address generation circuit, a control logic circuit and an error correction circuit, wherein the clock generation circuit is used for generating and outputting a self-refresh clock signal in response to a self-refresh enable signal; the internal command generation circuit is used for counting the self-refreshing clock signal when the error checking enable signal indicates that the internal error checking function is started, and generating and outputting an internal error checking command signal when the counting value of the self-refreshing clock signal is a first preset value; an address generation circuit counting the internal error check command signals to generate and output an internal error check address; and the control logic circuit responds to the internal error check command signal and controls the error correction circuit to sequentially execute one internal read-modify-write operation on the target storage units corresponding to the internal error check addresses in the plurality of storage arrays.

The invention discloses an intelligent graph ticketing system with topology verification in a power distribution program. Comprising a plurality of modules such as a data access and preprocessing module, a single line diagram topology coloring module and an equipment state intelligent identification module, and the data access module can access and preprocess data such as a distribution network GIS (Geographic Information System) graph model; the topology coloring module marks an area during ticket simulation; the intelligent identification module can identify the equipment state and the wiring mode; the operation ticket intelligent generation module generates operation steps through a graphic platform and can perform integrated verification; the drawing ticket anti-error checking module carries out ticket face and topology anti-error checking; the operation sequence generation and security check module generates a reasonable operation sequence and checks the reasonable operation sequence; the remote control operation pre-checking module checks the remote control operation working environment state and the equipment condition; the automatic remote control execution module initiates an execution request; the programmed operation monitoring and log recording module provides a monitoring interface and records ticket formation days. The system improves the efficiency and accuracy of operation ticket generation, and guarantees the operation safety.

A method and system for error check and scrub (ECS) error data collection and reporting for a memory device. A controller includes circuitry and a buffer. The circuitry may be configured to read ECS error data from a register of a memory device and calculate an ECS error increase rate based on the ECS error data. The circuitry may be configured to inform basic input output system (BIOS) by interrupt if a total number of ECS errors reaches or exceeds an ECS error number threshold or if the ECS error increase rate reaches or exceeds an ECS error rate threshold. The controller may be an out-of-band device, e.g., a baseboard management controller or a memory micro controller.

The invention relates to a multi-disaster risk early warning method and system using weather forecast data, and the method comprises the steps: storing the weather forecast data of an electric energy meter to construct a database, the weather forecast data comprising a precision grade, a weather data parameter sequence and a weather data increment; dividing the database into sub-databases according to the precision levels, and clustering meteorological data parameter sequences in the sub-databases to obtain clusters of all the precision levels; acquiring real-time data detected by the meteorological data acquisition instrument; calculating the sub-error of the target precision grade based on the clustering cluster of the target precision grade and the real-time data, and integrating all the sub-errors of the target precision grade to obtain a real-time error, the target precision grade being equal to or greater than the precision grade of the meteorological data acquisition instrument; and comparing the real-time error with the precision grade of the meteorological data acquisition instrument to obtain an error verification result. According to the technical scheme, the error checking efficiency of the electric energy meter is improved, and the hysteresis problem of checking time is solved.

The invention discloses a similarity and distance calculation system and method based on an R language, and relates to the technical field of data processing, and the key point of the technical scheme is that the system comprises the following modules: a data reading module, a data standardization module, a similarity calculation module and an error checking module. Through automatic data inspection, standardized processing and efficient similarity calculation, the user can easily perform complex similarity analysis. The method has a wide prospect in the application of big data analysis, machine learning and the like, a more convenient and more accurate similarity calculation scheme can be provided for a user, and the data processing and analysis efficiency is greatly improved.

A memory subsystem with error checking and scrubbing (ECS) logic on-device on the memory can adapt the rate of ECS operations in response to detection of errors in the memory when the memory device is in automatic ECS mode. The ECS logic can include an indication of rows of memory that have been offlined by the host. The ECS logic can skip the offlined rows in ECS operation counts. The ECS logic can include requests or hints by the host to have ECS operations performed. An internal address generator of the ECS logic can select between generated addresses and the hints. The system can allow a memory controller to detect multibit errors (MBEs) related to a specific address of the associated memory. When the detected MBEs indicate a pattern of errors, the memory controller triggers a row hammer response for the specific address.

The invention discloses a method for rapidly and stably solving a buckling path after multiple critical points based on a generalized displacement control method. The method comprises the steps that S1, a state variable and an anchoring type secant predictor are initialized; s2, predicting a reference displacement, a calibration displacement and a load increment factor based on the state variable and the anchored secant predictor; s3, calculating the displacement increment of the current iteration step based on the reference displacement, the calibration displacement and the load increment factor, and updating the total displacement and the total load of the structure; s4, updating the geometric state of the structure and the internal force of the unit based on the displacement increment of the current iteration step; s5, calculating the difference value between the total internal force and the external load of the structure based on the updated geometric state of the structure and the unit internal force to obtain the unbalanced force of the structure, and performing error checking based on the unbalanced force of the structure; s6, executing the steps S1 to S5 circularly until the unbalanced force of the structure meets the balance condition, and starting the next increment step; and incremental analysis is executed until user requirements are met, and a buckling path after multiple critical points is output.

A semiconductor system includes a controller configured to output a command and address for performing an ECS operation after the start of entry into a power-down operation, receive data and output the data in response to correcting one or more errors occurring in the data, and output a command for performing a self-refresh operation when the ECS operation is terminated, and a semiconductor device configured to output, as the data, internal data stored in multiple memory cells after the start of a read operation of the ECS operation in response to receiving the command and address, receive the data having the one or more errors corrected after the start of a write operation of the ECS operation, store the data having the one or more errors corrected, and perform a self-refresh operation on the multiple memory cells after receiving the command when the ECS operation is terminated.

Provided are a storage system, a memory chip, and an error check and scrub method. The storage system includes a memory controller and a memory chip. The memory chip performs an error check and scrub ECS operation on a memory array; and sends a generated ECS finish flag signal to the memory controller after a current ECS operation is completed. The memory controller receives the ECS finish flag signal, and sends a generated ECS start flag signal to the memory chip based on the ECS finish flag signal, so that the memory chip enters a new ECS operation cycle.

A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an error check and scrub (ECS) circuit, a row hammer management circuit and a refresh control circuit. The ECC engine generates an error generation signal based on a result of an ECC decoding. The ECS circuit generates scrubbing addresses and outputs at least one of the scrubbing addresses as an error address based on the error generation signal. The row hammer management circuit stores an error flag with a first logic level in count cells, compares counted values with different reference number of times based on a logic level of the error flag and outputs a hammer address. The refresh control circuit receives the hammer address and performs a hammer refresh operation on one or more victim memory cell rows which are physically adjacent to the memory cell row corresponding to the hammer address.

To provide a system.SOLUTION: A system includes: means for acquiring information inputted by a user; means for generating a form of a predetermined language using a generative AI model based on the information; means for translating the generated form into a language different from the predetermined language; and means for performing error check on whether the content of the generated form is appropriate or not based on the rule defined beforehand.SELECTED DRAWING: Figure 1

Memory with enhanced fail tracking, and associated systems, devices, and methods, are disclosed herein. In one embodiment, a memory device comprises a memory array and fail tracking circuitry. The fail tracking circuitry can include a counter and a plurality of memory slots and can be configured to, for each memory row of a plurality of memory rows in a memory region of the memory array, (a) count errors detected in data read from the memory row to determine an error count, and (b) store the error count and address information for the memory row in a memory slot of the plurality of memory slots. In some embodiments, the fail tracking circuitry can be configured to count the errors and store the error counts during error check and scrub operations of the memory device (e.g., to identify the worst memory rows in the memory region for post-package repair operations).

A display system increases a number of supported regions of interest and allowing for a dynamic background image by offloading region of interest calculations and data integrity checks from a display controller to a parallel processor of the display system. The parallel processor calculates a configurable number of regions of interest of a frame and error checks each of the regions of interest before transmitting the frame to the display controller.

Provided are a control circuit, a control method, and a semiconductor memory. The control circuit includes a timing control module and a command control module. An output terminal of the timing control module is connected to an input terminal of the command control module. The timing control module is configured to receive a first clock signal, perform counting based on the first clock signal, generate an error check and scrub (ECS) flag signal, and send the ECS flag signal to the command control module. The ECS flag signal is in a valid state when a counting value meets a preset condition. The command control module is configured to receive the ECS flag signal, obtain a refresh command signal when the ECS flag signal is in the valid state, and generate an ECS command signal based on the refresh command signal.

A method for operating a memory includes: receiving a predetermined command; performing an error check operation on a selected row and selected columns of one memory bank among a plurality of memory banks in response to the predetermined command; and performing a refresh operation on a selected row of each of the other memory banks among the memory banks in response to the predetermined command.

Various aspects include methods and devices for implementing the methods for error checking a memory system. Aspects may include receiving, from a row buffer of a memory, access data corresponding to a column address of a memory access, in which the row buffer has data of an activation unit of the memory corresponding to a row address of the memory access, determining multiple error correction codes (ECCs) for the access data using the column address, and checking the access data for an error utilizing at least one of the multiple ECCs. In some aspects, the multiple ECCs may include a first ECC having data from an access unit of the memory corresponding with the column address, and at least one second ECC having data from the access unit and data from the activation unit other than from the access unit.

A system that includes determining whether an interface between sender and receiver devices is defective. For an interface between a sender device and a receiver device: a configured number of stalls can be injected in a communication from the sender device to the receiver device. Based on the counted number of stalls being less than an injected number of stalls or exceeding the injected number of stalls by more than a threshold level, the interface can be identified as defective with respect to stall state counting. Based on the counted number of stalls being the same as the injected number of stalls or exceeding the injected number of stalls by not more than the threshold level, the interface can be identified as non-defective with respect to stall state counting.

The invention provides an intelligent guide algorithm system and an intelligent search guide method for an AI configuration tool. Comprising an intention recognition module used for receiving a demand text input by a user and performing multi-modal vectorization processing on the demand text; the intelligent question and answer module is used for generating function description information, operation example information and module mark information according to knowledge entries matched with the demand text when the function category label indicates that the platform has the function category; the AI auxiliary programming module retrieves function description information in an external information source based on the demand text when the function category label indicates that the platform does not have the function category; and the AI configuration judgment module is used for judging the legality of each connection line according to a pre-trained configuration rule model in the process of configuring and dragging the connection lines by the user, and outputting configuration error prompt information when the judgment result is illegal. According to the method, rapid and accurate retrieval, dynamic knowledge expansion, automatic code generation and configuration error real-time verification can be realized.

Chunks of data are identified and deduplication is performed on the chunks of data using associated cyclic redundancy check (CRC) values. A plurality of CRC values is obtained that is associated with consecutive data blocks stored in a payload data store. Cut point CRC values are identified in the plurality of CRC values and CRC chunks are identified based on those cut point CRC values, wherein each CRC chunk is bounded by two consecutive cut point CRC values. A CRC chunk hash value is generated for each CRC chunk. A pair of duplicate CRC chunks is identified using the CRC chunk hash values and a deduplication operation is performed in association with the identified pair of duplicate CRC chunks. Using existing CRC values during the identification of chunk cut points reduces the computing resource costs associated with performing that process using the data blocks.

A memory device having on-die error checking and correction (ECC) circuitry can provide uncorrected data in response to a read command. The ECC circuitry can perform error correction for errors detected, generating the corrected data in parallel with providing the uncorrected data. The memory device stores the corrected data internally to the memory device. When an error is detected, the memory device provides an indication to the memory controller, which can then request the corrected data.

Methods, systems, and apparatuses for a memory device (e.g., DRAM) including a directed error check and scrub (ECS) procedure are described. The directed ECS procedure may include read-modify-write cycles when errors are detected in code words. In some embodiments, the memory device may perform the directed ECS procedure on a code word in which an error was previously detected (for example, in response to a read command). The directed ECS procedure described herein may facilitate correcting code word errors before too many errors, exceeding the detection and / or correction capabilities of the memory device, accumulate in the code words.

The invention relates to the technical field of material review, and discloses a material review processing platform based on an AI model, and the platform comprises a front-end interaction and display module which is used for receiving application information containing one or more application materials from a user terminal; the AI cognition and processing center is used for receiving the application information and carrying out first-stage dominant error check and second-stage implicit logic risk study and judgment on the application material; and the dominant error verification aims at determining whether the application material has preset dominant errors in the aspects of integrity, format normalization and cross-material data dominant consistency. According to the method and the device, the multi-modal material analysis and dominant error verification functions are set, so that the technical problem that applications are frequently rejected and repeatedly submitted due to the fact that simple form errors exist in applied materials is solved, and the effect of remarkably improving the one-time passing rate of material submission is achieved.

In various examples, systems and methods are disclosed relating to health and error monitoring of sensor fusion systems. Systems and methods are disclosed that aggregate results of monitoring and error checking in a sensor fusion system in a single checkpoint. A processor may include one or more circuits. The one or more circuits may receive perception data from one or more first sensors of a machine. The one or more circuits may receive position data from one or more second sensors of the machine. The one or more circuits may generate output data by performing fusion of at least the perception data and the position data. The one or more circuits may evaluate a plurality of criteria according to at least a subset of the perception data, the position data, and the output data. The one or more circuits may output an error signal according to the evaluation.

The invention discloses a method for determining activation time of a liquid storage type reserve battery, which comprises the following steps: S10, acquiring parameters of a standard-size battery: selecting the standard-size battery as a pilot sample and an independent verification sample, and acquiring an electrolyte infiltration quality-time curve and actual activation time; s20, prediction parameter acquisition: calculating an initial time scaling factor and an initial infiltration quality critical threshold value of the pilot sample according to the electrolyte infiltration quality-time curve and the actual activation time of the pilot sample, and performing error verification by using independent verification sample parameters to obtain a prediction time scaling factor and a prediction infiltration quality critical threshold value; and S30, target battery activation time prediction: according to a target battery electrolyte infiltration quality-time curve, obtaining the time required for the target battery infiltration quality to reach the prediction critical threshold, and calculating the activation time of the target battery in combination with the prediction time scaling factor. The activation time determination method is high in efficiency and good in precision.

The invention discloses a self-adaptive integrated navigation method and system based on satellite differential signals, and belongs to the field of integrated navigation, and the method comprises the following steps: carrying out state prediction based on the output of an inertial navigation system; a deviation function is established through sliding window fitting, and effectiveness evaluation and preventive correction are carried out on differential satellite navigation system signals; dynamically adjusting a measurement noise matrix according to the positioning mode and performing residual error verification; carrying out measurement updating by utilizing the deviation passing the verification to obtain an estimated value containing the error of the inertial device so as to carry out closed-loop feedback correction on navigation parameters; and when the satellite signal fails, compensating the inertial navigation system by using the device error parameter in the estimated value and realizing pure inertial recursion. According to the method, the data quality can be improved from the source, the self-adaptive robustness of the system in a complex environment is enhanced, inertial navigation error divergence is continuously inhibited, and the navigation endurance precision under the extreme condition of satellite signal failure is guaranteed.

To provide a computer program, an information processing apparatus, and an information processing method which can further easily realize software development.SOLUTION: A computer program causes a computer to execute processing of acquiring a code relating to described database processing, accepting designation of any one of a plurality of functions including error check, creating an instruction sentence for use in obtaining a reply relating to the code according to the designated function, transmitting the acquired code and the created instruction sentence to a leaned language model, and, based on a reply from the language model, outputting data corresponding to the designated function.SELECTED DRAWING: Figure 1

The invention provides a test system for an inertial measurement control single machine, and belongs to the technical field of test equipment, the test system comprises a lower computer and an upper computer, the lower computer comprises a master control module and a slave control module, the modules realize the design of the lower computer through an MLVDS bus in a one-master multi-slave mode, and the master control module is connected with the slave control module. The module unit can independently realize a test function, one end of the lower computer is connected with an inertial measurement combination or control single-machine equipment through a test interface, and the other end of the lower computer is connected with the upper computer through a transmission cable. The master control module is integrated with an HDLC bus controller, and the protocol is integrated with the functions of flow control and error check, so that the system has the characteristics of high reliability, high transmission efficiency, strong adaptability and the like; by integrating the MLVDS bus controller, the problem of multi-node interconnection is effectively solved. All the modules are tightly connected through an MLVDS high-speed bus, efficient data communication is achieved, and meanwhile the accuracy and reliability of testing are guaranteed.