22 results about "Error check" patented technology

A universal asynchronous receiver / transmitter includes a transmit register including information to be transmitted, a receive register including received information, a frame error check circuit that evaluates contents of the receive register for a frame error, and a control logic. The control logic routes contents of the transmit register to the receive register. During transmission of the contents of the transmit register to the receive register through a reprogrammable pin, the control logic modifies a bit inversion register to produce modified contents to be provided to the receive register. The modified contents cause a frame error. The control logic determines whether the frame error check circuit detects the frame error.

A memory, a memory operation method, and a storage device are provided. The memory includes multiple banks, multiple error checking circuits, and an error address generation circuit. Each of the banks includes multiple data memory array tiles and an ECC memory array tile. Each of the error checking circuits is configured to separately read stored data and check data from the bank, and generate a corresponding error checking signal based on the stored data and the check data. The error address generation circuit is configured to receive multiple error checking signals from the multiple error checking circuits, and when any one of the error checking signals is at an inactive level, store address information corresponding to an error failing to meet a condition. In this way, an on-die ECC may be employed to pre-identify an error occurring in the memory, and after an error uncorrectable by the on-die ECC is identified, an error checking signal is generated to record error address information in a timely manner, thereby facilitating subsequent correction of the error and improving accuracy of the memory.

Disclosed is memory access logic that is operable to perform different accesses to a particular memory element depending on whether or not a memory error checking scheme is being implemented for the memory element. A set of error checking bits are stored in the memory element for implementing the memory error checking scheme. The memory error checking scheme can thus be selectively enabled and memory accesses performed accordingly such that when the memory error checking scheme is enabled, it is ensured that the required error checking bits are accessed.

A memory device is provided. The memory device includes: a memory cell array including a plurality of memory cell rows; a refresh control circuit configured to output a refresh row address to control a refresh operation to be performed on at least one memory cell row among the plurality of memory cell rows; and a control logic circuit configured to receive, from a memory controller, error check and scrub (ECS) setting data corresponding to a mode among a plurality of modes, store the ECS setting data in a mode register, and provide a target row address of a memory cell row to be refreshed to the refresh control circuit based on a value of the ECS setting data in response to a refresh command provided from the memory controller.

The application relates to a method for detecting overprint error of a digital inkjet printer and a related device, the method comprising controlling a nozzle system of the digital inkjet printer to print a preset test pattern on a substrate driven by a spindle; during the printing of the test pattern, a position encoding signal of the spindle rotation is acquired through an encoder linked with the spindle, wherein the position encoding signal comprises a pulse signal count value and a period count value; an actual printed image of the test pattern printed on the substrate is acquired through an image acquisition device; the position encoding signal and the actual printed image are analyzed to obtain error characteristics, and the error is classified into one of a plurality of preset error types based on the error characteristics. The application has the advantages of accurately finding out printing errors caused by different sources, facilitating later maintenance or compensation, and reducing error checking difficulty and checking time.

Even if an AI performs well on an evaluation dataset, it may not achieve the same level of accuracy in real-world applications. In such cases, confidence in the AI ​​diminishes, highlighting the need for a mechanism to develop reliable AI. [Solution] In the label error checking function, the CPU 201 of the client terminal 101 determines whether the label assigned to the object to be detected in the image included in the dataset to be checked is appropriate or not (S603~S608), and controls the display of the image containing the object to be detected that has been assigned an inappropriate label as a result of the determination (S609).

A memory includes multiple banks, multiple error checking circuits, and an error address generation circuit. Each of the banks includes multiple data memory array tiles and an ECC memory array tile. Each of the error checking circuits is configured to separately read stored data and check data from the bank, and generate a corresponding error checking signal based on the stored data and the check data. The error address generation circuit is configured to receive multiple error checking signals from the multiple error checking circuits, and when any one of the error checking signals is at an inactive level, store address information corresponding to an error failing to meet a condition.

A wireless transmit / receive unit (WTRU) may low-density parity-check (LDPC) encode data into LDPC blocks. Further, the WTRU may produce and append a cyclic redundancy check (CRC) to each of the LDPC blocks. Also, the WTRU may concatenate the plurality of LDPC blocks and appended CRCs. Additionally, the WTRU may produce information associated with error checks. Moreover, the WTRU may produce a codeword using a codebook. The codeword may be based on the information associated with the error checks. In addition, the WTRU may produce an orthogonal frequency-division multiplex (OFDM) signal by mapping the codeword and the concatenated plurality of LDPC blocks and appended CRCs onto resource elements of the OFDM signal. Further, the WTRU may transmit the produced OFDM signal. In a further example, the WTRU may produce an additional CRC in addition to the appended CRCs, and the produced OFDM signal may include the additional CRC.

A memory, a method of operating a memory, and a method of operating a memory system are disclosed. The method of operating a memory includes performing an error checking operation, detecting N bad sections during the error checking operation, where N is an integer equal to or greater than 1, stopping the error checking operation in response to detecting the N bad sections, transferring information about the N bad sections to a memory controller, and resuming the error checking operation in response to the information about the N bad sections being transferred to the memory controller.

An internal error-checking circuit includes a clock generation circuit, an internal command generation circuit, an address generation circuit, a control logic circuit, and an error correction circuit. The clock generation circuit generates and outputs a self-refresh clock signal in response to a self-refresh enable signal; the internal command generation circuit counts the self-refresh clock signals when the error-checking enable signal indicates that an internal error-checking function is enabled and generates and outputs one internal error-checking command signal when the count value of the self-refresh clock signal is a first preset value; the address generation circuit counts the internal error-checking command signal to generate and output an internal error-checking address; the control logic circuit controls, in response to the internal error-checking command signal, the error correction circuit to sequentially execute a single internal read-modify-write operation on the target memory cells corresponding to the internal error-checking address in memory arrays.

An inductive proximity sensor unit for detecting a detection body, wherein the detection body has metallic properties, comprising a sensor coil supplied with individual, time-spaced pulsed signals, an evaluation unit, wherein the evaluation unit is configured to measure values ​​for voltage or current of the pulsed signal at several sampling times and to determine an actual time series signal from the measured values, a storage unit, wherein at least three values ​​of a reference time series signal are stored in the storage unit for the detection body, wherein the evaluation unit is configured to check the actual time series signal for a disturbance by determining a functional relationship between the actual time series signal and the reference time series signal.

This application discloses a method, apparatus, device, and storage medium for real-time error checking on a low-code platform. The method acquires document editing attributes on the low-code platform in real time and determines document priority based on these attributes. It then performs deduplication on event documents of different priorities using an enqueue deduplication mechanism to generate document queues of different levels. Following the dequeue order of the document queues, it prioritizes checking the area the user is currently editing and documents that directly reference that editing area, ensuring that the user's focus is addressed first. Only affected resources are checked, allowing for rapid feedback even in large projects. Error checking can be completed without manual user intervention, effectively improving error checking efficiency.

A memory device and a method of operating the memory device are provided. The memory device includes a memory cell array including a plurality of memory cells to store data, an error correction code (ECC) circuit, and an error check and scrub (ECS) circuit. The ECC circuit reads the data from the memory cell array and corrects errors in the data. The ECS circuit performs a scrubbing operation on the memory cell array and transmits a signal for an error address detected based on the scrubbing operation to an external circuit and stores the error address which was transmitted.

The application discloses a tension error checking method and device and electronic equipment. First, the motor torque is obtained, then the model coefficient is obtained according to the motor torque, the torque tension model is obtained according to the model coefficient, the tension change amount is obtained, the target tension value is obtained according to the tension change amount, the torque instruction is obtained based on the torque tension model and the target tension value, finally, the difference checking is performed based on the torque instruction to obtain the checking result, and the tension error is checked based on the checking result, so that the tension cannot be compensated in time, and the fire caused by the slip is avoided.

The application discloses a method, system and device for converting ladder diagram language into ST language, comprising the following steps: S1, obtaining XML text of the ladder diagram language; S2, parsing the text of the ladder diagram language to obtain a multi-way tree; S3, traversing all first-level nodes of the multi-way tree, and after eliminating nodes irrelevant to the generation of the ST language, composing an element tree list; S4, formulating a sorting rule, sorting the element tree list according to the sorting rule to obtain a new list; and S5, traversing the new list, and calculating an expression of the ST language according to the type of a current node and the connection condition of the current node. The application can realize one-to-one correspondence between the ladder diagram elements and the ST code lines, facilitate static analysis and error checking of the code, and increase the portability of the project.

A method of an error checking scrub operation and a semiconductor system using the same are disclosed. The semiconductor system includes a controller configured to count a number of error checking scrub (ECS) operations and configured to generate ECS information including information about an address at which an ECS operation will be performed based on the number of ECS operations. The semiconductor system also includes a storage device configured to perform the ECS operation on an area selected by the ECS information.

Systems and methods are provided for implementing system object tracking for rule violation detection. In various examples, in response to a trigger event, a computing system may track a system object by tracking a tracker object corresponding to a memory address range of a database that has been allocated to the system object. Contemporaneous with the trigger event, the computing system determines, based on tracking of the tracker object, whether a system rule associated with the system object has been violated. Based on a determination that a system rule associated with the system object has been violated, the computing system triggers at least one action associated with the system object, including performing a contemporaneous error check, sending messages indicating an error caused by violation of the system rule, identifying a system component or driver that caused the error, and / or causing an immediate system crash.

The disclosure provides an apparatus, system, and method that increases the power efficiency of reading data from a storage device using, for example, reading guidance. The reading guidance allows software-defined data sizes that are beneficial for saving power when accessing data. The reading guidance can be the result of requesting agents providing additional contextual information with data requests that improves the power efficiency of obtaining the data for the data requests. In one example, an augmented data controller is disclosed that is configured to perform one or more operations associated with obtaining data from data storage for one or more requesting agents, wherein the operations include providing reading guidance to a storage controller associated with the data storage, wherein the reading guidance indicates one or more of an amount of data to read for a request or error checking procedures for data provided in response to the request.

The disclosure provides an apparatus, system, and method that increases the power efficiency of reading data from a storage device using, for example, reading guidance. The reading guidance allows software-defined data sizes that are beneficial for saving power when accessing data. The reading guidance can be the result of requesting agents providing additional contextual information with data requests that improves the power efficiency of obtaining the data for the data requests. In one example, an augmented data controller is disclosed that is configured to perform one or more operations associated with obtaining data from data storage for one or more requesting agents, wherein the operations include providing reading guidance to a storage controller associated with the data storage, wherein the reading guidance indicates one or more of an amount of data to read for a request or error checking procedures for data provided in response to the request.

The application relates to the technical field of intelligent control systems for garment processing, and discloses an internet-based intelligent control system for garment weaving, which comprises a transport vehicle, a control terminal used for receiving and modifying task information, distributing the task to corresponding sewing stations, controlling the operation of a control device, and performing label counting, the control device, a label reader, an error checking module, a rework module, and a warehouse. The internet-based intelligent control system for garment weaving receives, classifies and modifies the task information through the control terminal, then identifies the electronic labels on the transport vehicle by using a station reader, further identifies the stations, matches corresponding task amounts by the control terminal, and distributes the task amounts by the cooperation of the control device and the counter while feeding, so that the task amounts of all the stations can be accurately distributed to the stations, thereby achieving the effects of reasonable and effective task distribution and high processing efficiency.