90 results about "Type error" patented technology

A semiconductor memory device having an error check and correction (ECC) type error recovery circuit in which disposition of ECC cells is improved. The memory device comprises: a memory cell array including a plurality of normal cell array portions and an ECC cell array portion; an X decoder for selecting one of word lines in the memory cell array, the word lines extending from the X decoder to the memory cell array; an ECC operation circuit for performing error check and correction based on cell data read out from a selected word line, the cell data including data from normal cells and ECC cells of the selected word line. The ECC memory cell array portion is disposed at a location other than the far end of the word lines from the X decoder, that is, the ECC cell array portion is disposed at a location in which read out speed of data from ECC cell or cells does not become the worst speed in the memory device. Therefore, the worst data read out speed can be measured from outside.

A method for mitigating false positive type errors while applying an information leak prevention policy, the method comprising the computer implemented steps of: defining at least one positive criterion for a positive set, wherein the positive criterion comprises at least one indicator of a possible breach of the information leak prevention policy; defining at least one negative criterion for a negative set, wherein the negative criterion comprises at least one indicator of benign traffic; establishing an ambiguity set in association with an intersection between the positive set and the negative set, such that information items in the intersection enter the ambiguity set; defining at least one ambiguity resolution criterion for resolving the ambiguity; monitoring and analyzing electronic traffic, where each information item in the traffic is searched for matches with the positive set; checking for membership of each item in the positive set in the ambiguity set; resolving ambiguities using one of the ambiguity resolution criterion for each member of the ambiguity set and removing items from the positive set accordingly, and applying information leak prevention policy for all items remaining in the positive set following the removal of items using ones of the ambiguity resolution criteria.

The present invention relates to the field of computer programming. More specifically the invention relates to a method and a data processing system for editing the source code of a computer program. It is an object of the present invention to provide an easy source code editing technique, by which programming errors and type errors can reliably be avoided in cases where changes to the program are supposed not to change the semantics of the program. This object is achieved according to the invention by a method for editing source code, the method comprising the steps of: receiving a modification to the source code, said modification being made by a user, determining whether the modification would change the semantics of the source code, and handling the modification depending on the result of the determining step.

The invention provides a technical proposal for controlling errors in network systems. The technical proposal comprises the following steps: an user device captures the error generated in the operation of the user device to generate an error report which is sent to a network server through the user device; the network server collects the errors of a plurality of user devices and carries out analysis of the errors; and if the occurrence times of a same type errors reach to a preset threshold value, a corresponding processing can be executed. Through adopting the method and the device of the invention, the network server can know the errors generated by a plurality of user devices, and the cause of the errors can be found out through carrying out a statistical analysis of the errors and a corresponding processing measure can be adopted in time. The user device can also carry out analysis to the captured errors, sets the type of the errors and adopts a corresponding processing measure to deal with the errors in time.

A method for automatically detecting errors in machine translation using a parallel corpus includes analyzing morphemes of a target language sentence in the parallel corpus and a machine-translated target language sentence, corresponding to a source language sentence, to classify the morphemes into words; aligning by words and decoding, respectively, a group of the source language sentence and the machine-translated target language sentence, and a group of the source language sentence and the target language sentence in the parallel corpus; classifying by types errors in the machine-translated target language sentence by making a comparison, word by word, between the decoded target language sentence in the parallel corpus and the decoded machine-translated target language sentence; and computing error information in the machine-translated target language sentence by examining a frequency of occurrence of the classified error types.

An error processing method for a rewritable non-volatile memory module, a memory storage device and a memory controlling circuit unit are provided. The rewritable non-volatile memory module includes a plurality of memory cells. The error processing method includes: sending a first read command sequence for reading a plurality of bits from the memory cells; performing a first decoding on the bits; determining whether each error belongs to a first type error or a second type error if the bits have at least one error; recording related information of a first error in the at least one error if the first error belongs to the first type error; and not recording the related information of the first error if the first error belongs to the second type error. Accordingly, errors with particular type may be processed suitably.

An enhanced interleave type error correction method is provided in which decoding of an enhanced interleave block is done. Subsequently the decoding may be done by decoding the estimated codewords multiple times using a single error correction code. In addition, a decoder and a digital communication system for implementing the enhanced interleave type error correction method are provided.

An apparatus comprising an array controller and a frame buffer. The array controller may be configured to read/write data to/from a drive array in response to one or more input/output requests. The frame buffer may be implemented within the array controller and may be configured to perform (i) a first data integrity check to determine a first type of data error and (ii) a second data integrity check to determine a second type of data error. The frame buffer may log occurrences of the first type of error and the second type of error in a field transmitted with the data. The field may be used to determine a source of possible corruption of the data.

The invention discloses a memory storage device, a memory controller and a data writing method. The memory storage device is coupled to a host computer system; and the memory storage device comprises an error check and correction circuit and a reproducible nonvolatile memory chip. The method comprises a step of judging whether written data belong to a specific type when the written data are to be written into the reproducible nonvolatile memory chip, and also comprises the steps of generating at least one first type error check and correction code according with the first length by the error check and correction circuit according to the written data if the written data belong to the specific type, and generating at least one second type error check and correction code according with the second length by the error check and correction circuit according to the written data if the written data do not belong to the specific type, wherein the first length is larger than the second length.

The invention discloses an automatic upgrading method and an automatic upgrading device of communication equipment. The method comprises the following steps of: requiring a network side for downloading a required system file; verifying the system file according to file verification information carried in the downloaded system file and determining that verification passes if the file verification information is consistent with a requested system file, wherein the file verification information at least comprises information for indicating the file type and/or equipment model of the system file; and after the verification passes, replacing an original corresponding system file by the system file. Through the technical scheme, the correctness and completeness of a file downloaded during automatic upgrading of the communication equipment can be ensured, file type errors or equipment model errors can be avoided, and the situation of unavailable startup of the equipment after automatic upgrading due to a file error is avoided.

The invention relates to a network group control-type error dynamic compensation system of numerically-controlled machine tools. The network group control-type error dynamic compensation system includes a machine tool error measuring instrument, a temperature sensor, a temperature data acquisition card, a first router, an industrial personal computer and a second router; a group control error compensation and monitoring subsystem is embedded in the industrial personal computer and includes an error modeling module, a state monitoring module and an error compensation module; and a secondary interface subsystems is embedded in each numerically-controlled machine tool and includes a communication module, a machine tool parameter access module and an error compensation implementing module. Compared with the prior art, and according to the network group control-type error dynamic compensation system of the invention, each module is matched with each other, such that error dynamic compensation and state information monitoring of a plurality of numerically-controlled machine tools can be realized on one industrial personal computer, and therefore, the machining accuracy of the numerically-controlled machine tools can be improved in a batched manner. The network group control-type error dynamic compensation system has the advantages of high compensation efficiency, high compensation precision and low implementation cost.

The invention provides a method for digging a non-recalled type error correction word of a searching engine. The method comprises the following steps: the searching engine obtains a conversation log of a user, wherein the conversation log at least comprises a first conversation and a second conversation, and the first conversation and the second conversation respectively comprise a first searching word and a second searching word; the searching engine obtains related relation information between the first searching word and the second searching word; the searching engine judges whether the first searching word is the non-recalled type error correction word or not according to the related relation information. The invention further provides a device for digging the non-recalled type error correction word of the searching engine. According to the method and the device, modeling analysis on a user searching word sequence and a searching result is carried out so that the non-recalled type error correction word can be automatically found, and the recalling efficiency is considerably higher than that of manual searching; the manpower cost for finding out the non-recalled type error correction word is greatly reduced.

The invention discloses a reinforcement binding alignment device. The reinforcement binding alignment device comprises a first guiding rail, end surface alignment structures are symmetrically arrangedat the two ends of the first guiding rail, and each end surface alignment structure comprises a first motor, a gear set, a rack, a pushing block, a flat plate, a plurality of pressure sensors and a first processor. First binding structures are symmetrically disposed on the left and right sides of the first guiding rail, and each first binding structure comprises a slanting plate, a second guidingrail, an extrusion block, a telescopic rod and a first controller. The reinforcement binding alignment device further includes a second binding structure, and the second binding structure comprises abase, a mechanical arm, a second controller, a second motor, a connecting rod and an electric clamping jaw. The technical problems of the recognition quantity and type errors of an existing reinforcement recognition system are solved, the end face alignment and binding processing of the reinforcement is realized, the acquisition of accurate images is facilitated, and the technical effect of improving the accuracy of the reinforcement recognition system is achieved.

The invention discloses a method for detecting a physical topological link. The method comprises the following steps of: detecting a current networking type; and if the detected networking type is different from a pre-configured networking type, carrying out alarming on a networking type error. The invention further provides a system for detecting the physical topological link. According to the technical scheme provided by the invention, an abnormal condition that an RRU (Remote Radio-Frequency Unit) which is actually connected under a BBU (Base Band Unit) is different from an RRU which is pre-configured by a background can be detected.

A clock offset compensation arrangement may include a fractional interpolator for applying a trigonometric interpolation to a sampled input signal according to a clock offset signal. It uses transform-based processing in the frequency domain. Compared to a polynomial type interpolation it may be easier to implement, and may achieve a closer approximation to an ideal interpolation. It may reduce the effects of non-linear type errors introduced by truncation of higher powers. The arrangement may be applied to receivers or transmitters of multi-carrier modems, as well as other applications which use rate adaptation or synchronization.

The invention discloses a movable radar networking batch-processing type error register and belongs to the field of radar data processing. According to the conventional movable radar network error registration technology, supposed and constructed models do not meet actual engineering background requirements, the problem about movable radar network error registration is not systematically and comprehensively modeled and solved, and availability is low. The invention relates to a batch-processing algorithm for measurement. According to the algorithm, converged system error estimation is finally realized by recursively optimizing system errors along the maximum gradient of disturbance. The distance between radars is not limited, the priori knowledge of fixed reference points is not required to be utilized, and the error register is high in convergence speed and high in accuracy and has popularization and application values.

The invention relates to a logic node tree-shaped visual game editing engine. Different name lists are constructed by adopting tree-shaped programming, wherein the name lists of a logic set are arranged at the left side of a visual programming interface; the name lists correspond to the function lists in programming languages; a tree-shaped logic list is arranged at the right side of the visual programming interface; in a programming process, execution of the whole programming logic is started from a first line; the nodes are equipped with different icons for distinguishing different logic properties of the nodes; the part at the most right side of the visual programming interface is the attribute setting part of a single node; dynamical adjustment can be carried out according to the currently selected nodes; and the most lower part of the visual programming interface is equipped with a debugging operation interface. According to the method provided by the invention, logic errors resulting from typing errors can be reduced; the tree-shaped structure is clear in logic and is convenient for organizing and reading the logic; and the speed and efficiency of debugging the logic can be greatly improved.