5 results about "ECC memory" patented technology

The utility model discloses a COME board with ECC memory expansion interface, include: mainboard body, the mainboard body surface panel carries memory one side is equipped with the on -board expansion seat for the memory expansion of mainboard storage and operation, the on -board expansion seat upper end is equipped with the memory pressure plate for the compression of memory combination after expansion switching over through the slot hole of surface both ends, the utility model discloses the cooperation of positioning stand and memory positioning hole, realize the three -dimensional space orientation of memory stick main body on the mainboard body, avoid horizontal or longitudinal displacement, simultaneously, the memory pressure plate is connected through locking screw and the locking slot of on -board expansion seat, forms the even compression force to memory expansion switching over board, ensures the close contact of memory stick main body and memory slot, memory switching over plug and memory expansion slot, significantly improves the connection reliability under the complex environment such as vibration, high temperature, and prevents the data transmission unstable problem caused by poor contact.

A memory, a memory operation method, and a storage device are provided. The memory includes multiple banks, multiple error checking circuits, and an error address generation circuit. Each of the banks includes multiple data memory array tiles and an ECC memory array tile. Each of the error checking circuits is configured to separately read stored data and check data from the bank, and generate a corresponding error checking signal based on the stored data and the check data. The error address generation circuit is configured to receive multiple error checking signals from the multiple error checking circuits, and when any one of the error checking signals is at an inactive level, store address information corresponding to an error failing to meet a condition. In this way, an on-die ECC may be employed to pre-identify an error occurring in the memory, and after an error uncorrectable by the on-die ECC is identified, an error checking signal is generated to record error address information in a timely manner, thereby facilitating subsequent correction of the error and improving accuracy of the memory.

A memory includes multiple banks, multiple error checking circuits, and an error address generation circuit. Each of the banks includes multiple data memory array tiles and an ECC memory array tile. Each of the error checking circuits is configured to separately read stored data and check data from the bank, and generate a corresponding error checking signal based on the stored data and the check data. The error address generation circuit is configured to receive multiple error checking signals from the multiple error checking circuits, and when any one of the error checking signals is at an inactive level, store address information corresponding to an error failing to meet a condition.

A translation cache and configurable error checking and correction (“ECC”) memory reduces ECC memory overhead. The translation cache supports a configurable ECC memory capable of storing a portion of a cache line, along with any ECC data, in corresponding parts of memory devices to reduce the ECC memory overhead in a memory subsystem. The corresponding parts include any same one of an upper, lower, left or right part of memory devices in a memory module, including dynamic random access memory (“DRAM”) devices in a dual inline memory module (“DIMM”).

The invention discloses a collaborative parallelization error correction method and equipment for a DRAM (Dynamic Random Access Memory), and belongs to the field of computer storage, and the method comprises the following steps: at a DRAM chip end, carrying out error detection on a code word consisting of a data block D and a check bit thereof by utilizing an in-memory error correction code, if an error is detected in the D, generating a pseudo-random number at the DRAM chip end and injecting the pseudo-random number into a sub-block where the error is located, and if the error is detected in the D, carrying out error correction on the sub-block; obtaining a data block D ', and sending the D' to a memory controller; in a memory controller, a plurality of data blocks from a DRAM chip are combined into RS erasure code words, and pseudo-random numbers in the RS erasure code words are identified as known errors through pseudo-random number comparison; performing error correction on the RS erasure code word based on known error information; in the memory controller, a new pseudo-random number is generated every time the pseudo-random numbers are successfully compared, and the pseudo-random number generated at the ith time is the same as the pseudo-random number generated at the ith time in the DRAM chip. According to the invention, DRAM error correction with low overhead, high reliability and low delay can be realized.