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BIST and ECC combined memory detection device in system chip

A system chip and detection device technology, applied in static memory, instruments, etc., can solve problems such as increased processing overhead and system performance degradation

Active Publication Date: 2019-09-27
ZHEJIANG UNIV +1
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Rewriting data will increase the processing overhead, which will lead to a significant decrease in system performance

Method used

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  • BIST and ECC combined memory detection device in system chip
  • BIST and ECC combined memory detection device in system chip
  • BIST and ECC combined memory detection device in system chip

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Embodiment Construction

[0034] The technical solution of the present invention will be further described below in conjunction with the accompanying drawings.

[0035] The memory detection device combining BIST and ECC proposed by the present invention is as follows: figure 1 shown. The whole device is composed of a BIST circuit module, a selector, a memory and an ECC module, and the ECC module includes an ECC memory, an error correction encoder and an error correction decoder. The BIST circuit module is used to receive external test control signals, initiate test operations, manufacture test vectors, test results, and give test result signals; the selector is used to select the ECC module, and the ECC module is used in combination by BIST in a multiplexed manner. The architecture of the system is reconfigurable.

[0036] When the ECC module detects a problem, it cannot be used. At this time, BIST cannot reuse the ECC module, and the selector will not select the ECC module; figure 2 The shown ECC ...

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Abstract

The invention provides a memory detection device for an ECC module in a BIST multiplexing system chip, and belongs to the field of memory detection. The device comprises a BIST circuit module, an ECC memory, a memory, an error correction encoder and an error correction decoder. When the ECC module has no error, the BIST may select to multiplex the ECC module. According to the device provided by the invention, the data is detected in a manner of reading and writing the data into the memory. In the process, when an error of one bit occurs, the error can be corrected by the ECC error correction decoder module, the error cannot be detected at the BIST detection end, a given detection result signal is pass, and it is considered that the area is still available. And when more than two bits of errors exist, it is considered that the errors are true errors, and a fail signal is reported. The device improves the yield of the memory during detection.

Description

technical field [0001] The invention relates to the field of built-in self-test of memory, in particular to a memory detection device combining BIST and ECC in a system chip. Background technique [0002] Nowadays, semiconductor manufacturers mostly focus on the performance of storage array technology in terms of capacity, process technology, and quality. System on chip (soc, System on Chip), also known as system on chip, is to integrate a complete system on a single chip. System chips are mainly used in embedded systems, mobile devices, personal computers and other fields. At the same time, embedded memory is an important part of soc, and its performance index and reliability directly determine the performance of soc. The stability of embedded memories is becoming more and more important in the design and test world. In microprocessors and ASICs, large-scale SRAM (Static Random-Access Memory, Static Random-Access Memory) arrays, which are widely used as cache memory, occ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/42G11C29/44
CPCG11C29/42G11C29/44G11C2029/4402
Inventor 黄凯郑昌立余慜修思文
Owner ZHEJIANG UNIV
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