69 results about "Embedded memory" patented technology

The invention relates to the technical field of embedded data storage, and discloses a data storage method and system for an embedded storage chip. The method comprises the following steps: acquiring a to-be-stored original data stream through a data acquisition interface and performing segmentation marking; performing hierarchical decomposition on the data segments by adopting a dynamic decomposition algorithm to generate a plurality of data components; calculating an information density index of each data component, and screening key data components and non-key data components according to the information density index; key data components are stored in a high-speed cache region, and non-key data components are stored in a conventional storage region; performing redundancy check on the key data components in the cache region and generating a check result; after correcting the key data component based on the verification result, recombining the key data component with the non-key data component to generate an optimized data stream; writing the optimized data stream into a physical storage medium and recording a storage position; and monitoring the storage load state, and dynamically adjusting the distribution proportion of the two storage areas.

Systems or methods of the present disclosure may provide an integrated circuit system that includes a programmable logic device that includes a clock, one or more local controllers, programmable logic units implementing a systolic array to compute a matrix multiplication, and embedded memory blocks. The embedded memory blocks include a single port random access memory (SPRAM). The one or more local controllers are configured to, on a first set of alternating clock cycles of the clock, load matrix sub-elements from two rows of a matrix into corresponding matrix element of the SPRAM. The one or more local controllers are configured to, on a second set of alternating clock cycles of the clock, read out the matrix elements from the SPRAM to the systolic array to compute the matrix multiplication.

The invention discloses a test method and system for dynamic configuration and verification of a GPP of an eMMC memory, and relates to the technical field of embedded memorizers, and the method comprises the following steps: S1, the test system obtains a test parameter set through external input or from a predefined test case library, S2, after the input test set is processed through a dynamic parameterization engine DPCE, the test parameter set is stored in the test case library; the test system analyzes the configuration data to obtain analysis parameters, and to-be-written configuration data is formed; s3, before a configuration command is sent, dynamically constructing an eMMC partition layout model, and executing a conflict detection algorithm; s4, the test system writes the configuration data to be written after conflict detection into the eMMC; s5, adopting a triple persistence verification ring mechanism to form closed-loop verification with configuration taking effect; and S6, outputting a detailed test report by the test system based on the judgment node in the test process. According to the method, the test efficiency is remarkably improved, the test coverage rate and the product quality are enhanced, and more flexible and comprehensive test case design is supported.

A single integrated circuit is provided, comprising a memory region and a non-memory region. The memory region comprises a first conductive structure, a memory element disposed upon the first conductive structure, and a first via disposed upon the memory element. The non-memory region comprises a second conductive structure, and a second via disposed upon the second conductive structure. The first conductive structure and the second conductive structure are formed by a first photolithography process comprising a first photomask, and the first conductive structure is configured to be a first bottom electrode in the memory region. The first via and the second via are formed by a third photolithography process comprising a third photomask. The first photomask and the third photomask comprise a same pattern.

The present application relates to an image processing method, and a computer program product, a device and a storage medium. The method comprises: acquiring a first image file and a second image file, wherein the first image file is a binary image file, and the second image file is a folder image file; verifying the first image file and the second image file; and refreshing the successfully verified first image file to a first partition of a preset logical flash, and refreshing the successfully verified second image file to a second partition of the preset logical flash, wherein the first partition of the preset logical flash is a flash partition, and the second partition of the preset logical flash is an embedded memory partition. The method can improve the efficiency of system updating and maintenance.

The present disclosure provides an automatic driving controller data idle uploading method, system, medium and equipment, relates to the technical field of intelligent network connected vehicles, and comprises an automatic driving domain controller, a double rate synchronous random access memory, an embedded memory, a regional network management controller, a vehicle-mounted communication terminal and a vehicle domain controller. When the vehicle power supply mode is in an ON mode, the automatic driving domain controller writes and stores the backhaul data generated during the automatic driving function operation in the embedded memory through the double rate synchronous random access memory. When the vehicle is powered off, the regional network management controller sends a CAN message maintenance request, wakes up the vehicle-mounted communication terminal and the vehicle domain controller which need data uploading, and then uploads the temporarily stored data in the embedded memory.

A semiconductor device and methods of fabrication thereof including a substrate, a doped well formed in the substrate, a transistor formed on the substrate, a dielectric material located over the doped well and the transistor and including interconnect structures extending through the dielectric material, the interconnect structures including a first set of interconnect structures electrically coupled to an active region of the transistor and a second set of interconnect structures electrically coupled to the doped well, an active memory cell electrically coupled to the active region of the transistor via the first set of interconnect structures; and a dummy memory cell electrically coupled to the doped well via the second set of conductive interconnect structures. The dummy memory cell and the second set of conductive interconnect structures may provide a low resistance pathway for plasma charge to flow to the doped well, thereby minimizing plasma induced damage to the transistor.

Embodiments of the present application provide a chip, a preparation method thereof and an electronic device, and relate to the technical field of semiconductors, and are used to improve the storage density of embedded memories. The chip comprises a plurality of memory cell groups. A memory cell group comprises a first transistor and two memory cells. A memory cell comprises a second transistor and a storage element, and the first transistor and the second transistor each comprise an active structure, and the active structure of the first transistor is located between the active structures of the second transistors of the two memory cells. The active structure comprises a channel region, a first contact region and a second contact region. The first contact region of the first transistor is connected to the first contact region of the second transistor of one memory cell, and the second contact region of the first transistor is connected to the first contact region of the second transistor of the other memory cell; wherein in the same memory cell group, when the memory cells are in a working state, the first transistor is in an off state. The above chip is applied to an electronic device, thereby improving the performance of the electronic device.

The invention relates to the technical field of cues, in particular to a carbon fiber forelimb embedded with memory titanium alloy, which comprises a skin head, a tip, a forelimb main body and a middle wheel, the diameter of the forelimb main body is gradually increased from the front end to the rear end, the tip is arranged at the front end of the forelimb main body, and the middle wheel is arranged at the rear end of the forelimb main body. The skin head is arranged on one end face, away from the forelimb main body, of the tip; the forelimb body comprises a hollow carbon fiber tube and a plurality of memory titanium alloy rods embedded in the carbon fiber tube in an annular array mode. The invention further provides a carbon fiber rear handle embedded with the memory titanium alloy and a carbon fiber billiard cue. According to the carbon fiber billiard cue, the carbon fiber tube and the memory titanium alloy rod are combined together, so that the carbon fiber billiard cue has the characteristics of high hardness, high elasticity and high deformation resistance, can bear large deformation bending and restore original straightness, provides more stable and reliable performance for the billiard cue, is more wear-resistant and corrosion-resistant in the use process of the billiard cue, and has the advantages of being simple in structure and convenient to use. The service life is longer, and the weight of the carbon fiber forelimb is reduced through the hollow carbon fiber tube.

The invention discloses a BE-SONOS (Bipolar-Silicon Oxide Nitride Oxide Semiconductor) embedded memory structure. The BE-SONOS embedded memory structure comprises a selection gate, a control gate and a floating gate, the control gate is located on the floating gate, and the floating gate and the control gate are isolated by an insulating dielectric layer; the control gates and the floating gates are divided into a plurality of groups, and the selection gate is of a groove type and is positioned in the substrate between the adjacent control gate and floating gate; channel regions are formed in the substrate on the two sides of the trench-type selection gate; the floating gate is of a composite BE-SONOS multi-layer structure and sequentially comprises a first oxide layer, a first nitride layer, a second oxide layer, a second nitride layer and a third oxide layer from bottom to top. According to the invention, the characteristic that an Si dangling bond in the nitride can capture electrons and holes is utilized, the nitride is used as an electron capture layer, and a floating gate of an existing structure is replaced by a BE-SONOS structure, so that the carrier injection efficiency is relatively improved, fewer masks are used in the manufacturing process, the process time is shortened, and the manufacturing efficiency is improved.

An embedded memory device includes a retention voltage supply circuit outputting a retention voltage in response to a retention activation signal, and a plurality of array voltage supply circuits outputting corresponding array voltages to corresponding bit cells. The plurality of array voltage supply circuits respectively include an array switch providing the retention voltage as a corresponding array voltage in response to the retention activation signal, a power switch providing a power supply voltage as the corresponding array voltage in response to a power gate activation signal, and an auxiliary circuit compensating the corresponding array voltage during a write operation or a read operation.

The present application relates to the technical field of data processing, and more particularly to a large-scale knowledge graph construction system based on a graph neural network, comprising a node incremental receiver, a historical embedding memory, a dynamic neighbor sampler, a local subgraph generator, a quantum state aggregator, a space-time topology verifier, an embedding propagation controller and a graph updater. The time sequence control closed loop adopts time window batch processing of new nodes, the historical embedding memory aligns version snapshots and reuses historical embeddings, and the dynamic neighbor sampler optimizes sampling resources according to time sequence density; the precision adjustment closed loop triggers relationship weight correction and quantum circuit parameter updating, the embedding propagation controller freezes the gradient of non-activated nodes to focus on key changes; the resource optimization chain adjusts to reduce neighborhood complexity, the time decay coefficient compresses the size of the adjacency matrix, and the historical embedding memory pointer call eliminates vector copy overhead. The present application significantly reduces the computational resource consumption of the dynamic updating process and maintains the quality of the knowledge graph representation.

An apparatus is provided which comprises: an interposer comprising traces and conductive contacts on a first interposer surface and a second interposer surface opposite the first interposer surface, a computing device coupled with contacts on the first interposer surface, a first memory array coupled with contacts on the first interposer surface, and a second memory array embedded between the first interposer surface and the second interposer surface, the second memory array inverted in orientation relative to the first memory array, the second memory array directly coupled through traces in the interposer with the first memory array and the computing device. Other embodiments are also disclosed and claimed.

The invention provides a temperature self-adaptive adjusting method and system of an eMMC memory, and belongs to the technical field of embedded memories. Comprising the following steps: acquiring a real-time temperature and a temperature change rate of an eMMC memory; when the temperature change rate does not exceed a change rate threshold value, executing a corresponding parameter adjustment strategy according to the change condition of a preset temperature interval where the real-time temperature of the eMMC memory is located; after the parameters are adjusted, a diagnosis test link is operated, the performance of the eMMC memory under the current parameters is evaluated, and the current configuration is selectively effective according to a performance evaluation result; and when the temperature change rate exceeds a change rate threshold value, directly interrupting a current process to enter a quick response process, skipping a diagnostic test link and directly applying predefined conservative parameters to the eMMC memory regardless of the real-time temperature of the eMMC memory until the temperature change rate returns to normal or maintains the lowest performance level.

1. The name of the design product: industrial router (industrial S10 series). 2. The use of the design product: for an industrial router, with built-in embedded memory, supporting local storage and data processing; can be used for remote control, remote operation and maintenance, industrial manufacturing, PLC management, logistics sorting, etc. 3. The design points of the design product: the combination of shape and pattern. 4. The picture or photo that best shows the design points: perspective view 1.

An embedded memory system includes an embedded memory circuit and a host circuit. The embedded memory circuit is used to store a lookup table. The host circuit is used to test the embedded memory circuit using a test clock signal having a plurality of phases and a plurality of instructions of a program of the embedded memory circuit, and record a correspondence between each of the instructions and the phases to generate the lookup table.

The utility model provides a circuit board, an embedded memory and a solid state disk. The circuit board comprises a base body and multiple layers of wires arranged on the base body, the wires in different layers are coupled through via holes formed in the base body, the multiple layers of wires form a topological structure, and the topological structure comprises a first transmission path, at least two second transmission paths and multiple third transmission paths. One end of each second transmission path is coupled with the first transmission path, the other end of each second transmission path is coupled with at least two third transmission paths, and the wires of each second transmission path are located on the same layer; wherein the length of the first transmission path is greater than that of the second transmission path, and the length of the second transmission path is greater than that of the third transmission path. Therefore, the signal attenuation and the transmission delay can be improved, and the reliability, the stability and the high efficiency of signal transmission can be improved.

A pixel driving circuit for a display device includes a data driving circuit configured to output control signals indicating operation modes and a data signal indicating image data through a column line or a row line, and an array of a plurality of pixels, each pixel including a light-emitting element, and a pixel-embedded memory configured to receive the data signal from the column or row line via a first signal path, and configured to store the image data to drive the light-emitting element of a pixel, and a signal distributor configured to connect the first signal path to or disconnect the first signal path from the column or row line based on the operation modes.

The invention relates to the technical field of data analysis, and discloses an electrocardiosignal analysis method and system.The electrocardiosignal analysis method comprises the steps that original electrocardiosignals and physiological index data of a target user are collected; performing adaptive filtering processing on the original electrocardiosignal based on the motion sensing state of the electrocardiograph unit to obtain a target electrocardiosignal; using a preset multi-scale morphological algorithm to extract electrocardio waveform features of the target electrocardio signal, and performing data fusion on the electrocardio waveform features and the physiological index data to obtain a feature fusion vector; generating an electrocardiosignal analysis model according to embedded memory resources of the medical equipment and a network structure of a preset lightweight neural network model; training an electrocardiosignal analysis model according to pre-acquired medical health training data, and analyzing the feature fusion vector through the trained electrocardiosignal analysis model to obtain an electrocardiosignal graph of the target user. According to the invention, the accuracy of electrocardiosignal analysis can be improved.

Various embodiments of the present disclosure are directed towards a memory device. The memory device has a first transistor having a first source / drain and a second source / drain, where the first source / drain and the second source / drain are disposed in a semiconductor substrate. A dielectric structure is disposed over the semiconductor substrate. A first memory cell is disposed in the dielectric structure and over the semiconductor substrate, where the first memory cell has a first electrode and a second electrode, where the first electrode of the first memory cell is electrically coupled to the first source / drain of the first transistor. A second memory cell is disposed in the dielectric structure and over the semiconductor substrate, where the second memory cell has a first electrode and a second electrode, where the first electrode of the second memory cell is electrically coupled to the second source / drain of the first transistor.

The invention discloses a vacuum nanowell embedded memory device and a 1nm node equivalent density reconstruction method thereof. The memory device is formed in a CMOS rear-end metal layer, and the core of the memory device is a vacuum nanowell which is wrapped by an insulating side wall in an airtight manner. The device has the excellent characteristics of ultra-low power consumption, high density, high reliability and the like, specifically, the write-in voltage is less than or equal to 0.45 V, and the single-bit energy consumption is lt; 1.0 fJ, the surface density is greater than or equal to 12 Gbit / cm, and the cycle life at the ambient temperature of 150 DEG C exceeds 2 * 10 times. The manufacturing method provided by the invention is completely based on a 193nm ArFi DUV photoetching platform, realizes storage performance and density equivalent to a 1nm technical node on the premise of not depending on EUV photoetching through lateral self-alignment quadruple patterning, a two-dimensional channel material, a bismuth semi-metal contact and a back micro-channel heat dissipation key technology, and can be widely applied to the field of high-end chips such as a vehicle gauge MCU (Microprogrammed Control Unit), an AIoT SoC (Advanced Internet of Things SoC) and the like.

This application relates to a method and system for identifying eMMC performance degradation based on access time-series entropy. The method includes: performing timestamp differential processing on the interaction request data corresponding to the embedded memory to obtain access latency data and access request feature data; extracting access entropy features from the access request feature data to obtain access time-series entropy feature set data; modeling a health baseline based on the mapping relationship between entropy domain load and access latency according to the access time-series entropy feature set data and the access request feature data to obtain health baseline model data; calculating information-theoretic channel residuals on the deviation between actual access latency and expected access latency based on the access latency data and the health baseline model data to obtain degradation characterization data; and performing multi-evidence change detection on the degradation characterization data to obtain performance degradation identification result data. This method can ensure the stability of eMMC operation.

An integration process including an etch stop layer for high density memory and logic applications and methods of fabrication are described. While various examples are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For instance, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and / or threshold gate.

The application discloses a kind of storage assembly test method and system, storage medium and electronic equipment.The method comprises: in the case where receiving the first instruction sent by host, using the test parameter carried by first instruction to carry out the compatible test of main equipment and the slave equipment to be tested;Wherein, at least including: the first storage assembly corresponding to secure digital card and the second storage assembly corresponding to embedded memory on the slave equipment to be tested;In the process of carrying out the compatible test of main equipment and the slave equipment to be tested corresponding, the numerical set corresponding to multiple preset target parameters of main equipment is determined, and the numerical allowable range supported by the slave equipment to be tested for each parameter in multiple preset target parameters is determined;According to numerical set and numerical allowable range, it is determined whether the first storage assembly and / or second storage assembly in main equipment and the slave equipment to be tested is compatible.Solve the problem that the test efficiency of whether the storage assembly and other equipment are compatible in the prior art is lower.

A computer-implemented system and method for distributed memory-native networking using agents. Each agent comprises a unique identifier, payload, memory field containing lineage and policy references, transport metadata, and a cryptographic signature. A modular protocol stack processes these agents through routing, indexing, and consensus layers, with behavior determined by embedded memory. Routing decisions are trust-scoped based on memory-derived access logs and health feedback. Mutation proposals are validated using dynamic, memory-referenced quorum formation. The system enables stateful, policy-bound propagation, structural reorganization, and adaptive execution without centralized coordination or persistent session state. It operates over conventional transport protocols and supports interoperability with cognition-layer payloads, including semantic execution. The architecture allows dynamic trust modeling, autonomous network adaptation, and memory-driven mutation governance across heterogeneous, decentralized, and highlatency environments.

The invention discloses a capacitor structure based on an embedded memory and a manufacturing method thereof. The capacitor structure based on the embedded memory comprises a first word line, a second word line and a third word line which are located on a substrate, a first floating gate which is located between the first word line and the second word line uninterruptedly, a second floating gate which is located between the second word line and the third word line uninterruptedly, and a second floating gate which is located between the second word line and the third word line uninterruptedly, a plurality of first contacts are connected to the word lines, a plurality of second contacts are connected to the floating gates, and the capacitor structure is in mirror symmetry with the second word line as the center line.

The utility model discloses an embedded memory chip testing device, which comprises a chip strip, a testing seat and a pressing block, and is characterized in that the chip strip is a splicing body of a plurality of chips subjected to patch and wire bonding, and the plurality of chips are distributed in an array; a plurality of connecting pieces are arranged on the upper end surface of the test seat, and the connecting pieces are in one-to-one correspondence with pin bonding pads on the back surface of a to-be-tested chip strip; the chip strip is pressed and attached to the test seat through the pressing block, a hollow window is formed in the pressing block, and the position of the hollow window is matched with that of the chip. By testing part of the chip after wire bonding, whether each process is abnormal or not before packaging can be quickly confirmed, so that the test verification of the chip is greatly accelerated, the function verification period is shortened, and the product development risk, the later invalid production investment and the application risk in a terminal are reduced.

The invention provides an intelligent network card, an operating system switching method and electronic equipment, which can be applied to the technical field of computers. The intelligent network card comprises a system-on-chip, a nonvolatile memory and an embedded memory, wherein the system-on-chip, the nonvolatile memory and the embedded memory are deployed in the intelligent network card; the nonvolatile memory is used for storing programmable gate array mirror images and bootstrap programs of a main system and a standby system in the intelligent network card; the embedded memory is used for storing an operating system mirror image of the standby system, user data shared by the main system and the standby system and a system running file; the intelligent network card is configured to control the processor to run a bootstrap program of the standby system through a system switching module in the programmable gate array under the condition of determining that the main system has a fault, so as to configure a programmable gate array mirror image of the standby system to the programmable gate array, and load an operating system mirror image of the standby system to the processor; and mounting the user data and the system running file at the same time to start the standby system.

Methods, systems, and devices for techniques for managed NAND translation with embedded memory systems are described. A host system may generate a first command to access a logical memory address associated with a memory system. The host system may identify a physical memory address of the memory system based on generating the first command. The host system may output to the memory system a second command and the physical memory address, where the second command may be communicated to the memory device using a protocol associated with a controller of the memory system. The memory system may then access memory cells in a memory device associated with the physical memory address based on receiving the second command and the physical memory address.