14 results about "Embedded memory" patented technology

Embodiments of the present application provide a chip, a preparation method thereof and an electronic device, and relate to the technical field of semiconductors, and are used to improve the storage density of embedded memories. The chip comprises a plurality of memory cell groups. A memory cell group comprises a first transistor and two memory cells. A memory cell comprises a second transistor and a storage element, and the first transistor and the second transistor each comprise an active structure, and the active structure of the first transistor is located between the active structures of the second transistors of the two memory cells. The active structure comprises a channel region, a first contact region and a second contact region. The first contact region of the first transistor is connected to the first contact region of the second transistor of one memory cell, and the second contact region of the first transistor is connected to the first contact region of the second transistor of the other memory cell; wherein in the same memory cell group, when the memory cells are in a working state, the first transistor is in an off state. The above chip is applied to an electronic device, thereby improving the performance of the electronic device.

An apparatus is provided which comprises: an interposer comprising traces and conductive contacts on a first interposer surface and a second interposer surface opposite the first interposer surface, a computing device coupled with contacts on the first interposer surface, a first memory array coupled with contacts on the first interposer surface, and a second memory array embedded between the first interposer surface and the second interposer surface, the second memory array inverted in orientation relative to the first memory array, the second memory array directly coupled through traces in the interposer with the first memory array and the computing device. Other embodiments are also disclosed and claimed.

This application relates to a method and system for identifying eMMC performance degradation based on access time-series entropy. The method includes: performing timestamp differential processing on the interaction request data corresponding to the embedded memory to obtain access latency data and access request feature data; extracting access entropy features from the access request feature data to obtain access time-series entropy feature set data; modeling a health baseline based on the mapping relationship between entropy domain load and access latency according to the access time-series entropy feature set data and the access request feature data to obtain health baseline model data; calculating information-theoretic channel residuals on the deviation between actual access latency and expected access latency based on the access latency data and the health baseline model data to obtain degradation characterization data; and performing multi-evidence change detection on the degradation characterization data to obtain performance degradation identification result data. This method can ensure the stability of eMMC operation.

A computer-implemented system and method for distributed memory-native networking using agents. Each agent comprises a unique identifier, payload, memory field containing lineage and policy references, transport metadata, and a cryptographic signature. A modular protocol stack processes these agents through routing, indexing, and consensus layers, with behavior determined by embedded memory. Routing decisions are trust-scoped based on memory-derived access logs and health feedback. Mutation proposals are validated using dynamic, memory-referenced quorum formation. The system enables stateful, policy-bound propagation, structural reorganization, and adaptive execution without centralized coordination or persistent session state. It operates over conventional transport protocols and supports interoperability with cognition-layer payloads, including semantic execution. The architecture allows dynamic trust modeling, autonomous network adaptation, and memory-driven mutation governance across heterogeneous, decentralized, and highlatency environments.

Integrated circuit (IC) devices having transition regions between logic and memory regions. An IC device may include interconnect lines through a dielectric material in interconnect layers over a device layer, a stack of memory cells over the device layer and laterally adjacent the interconnect layers, a conductor extending vertically through the memory cells, a distance shorter than a height of the stack of memory cells separating the stack of memory cells and a sidewall of the dielectric material, and lateral surfaces of the memory cells not vertically aligned with lateral surfaces of any of the interconnect lines. A chemically metallic sidewall layer may enable a dielectric-on-dielectric process that negates the need for a large transition region between logic and memory regions.

This application discloses a fault diagnosis method and electronic device applied to a baseboard management controller. The method includes: in response to a detection status bit in a shared memory shared by the host and the baseboard management controller being configured to a start detection state by the host; loading a target diagnostic script from multiple diagnostic scripts stored in the embedded memory of the baseboard management controller according to a script flag bit set by the host; obtaining a fault diagnosis result file based on the target diagnostic script; writing the fault diagnosis result file into at least one data segment of the shared memory; setting the segment flag bit corresponding to the data segment containing the fault diagnosis result file in the shared memory to the file timestamp of obtaining the fault diagnosis result file; the shared memory includes a data partition and a configuration partition; the data partition includes multiple data segments; the configuration partition includes multiple segment flag bits corresponding one-to-one with the multiple data segments; and configuring the detection status bit to an end detection state, so that the host obtains the fault diagnosis result file from the shared memory.

This utility model discloses a silicon interposer, a packaging structure, and a semiconductor device, relating to the field of semiconductor technology. The silicon interposer is formed within a silicon interposer layer and specifically includes: a memory cell layer, comprising at least one memory cell embedded within the silicon interposer; a bottom circuit layer located on one side of the memory cell layer and connected to the memory cell; the bottom circuit layer is used to control the memory cell; and a metal wiring layer located on the side of the memory cell layer away from the bottom circuit layer; the metal wiring layer is connected to the memory cell and is used to achieve signal interconnection between external circuitry and the memory cell. This utility model achieves a collaborative technical solution of a silicon interposer structure without through-silicon vias (TSVs) and an embedded memory cell.

The present disclosure provides a framework for enhancing artificial intelligence models while reducing its memory requirements, for example, via a multi-field embedding approach. In one exemplary aspect, this framework may be applied to knowledge graphs to mitigate the effects of node degree extremity and to reduce embedding memory demand. For example, this framework may provide multiple graph fields in knowledge graphs that embed nodes in different dimensions to correct for skewness in the distribution of node degrees and decrease memory requirements when training KGE models. In some aspects, the framework may implement a user-specified strategy to split a knowledge graph into a number of distinct fields with similar connectivity patterns. KGEs may then be computed in a model-agnostic manner to allow each field to embed into a different dimensionality, and mathematical transformations may be used to convert embedding dimensions between fields when needed during algorithmic processing.

Integrated circuit (IC) devices with transition areas between logic and memory regions. An IC device may include interconnects through a dielectric material in interconnect layers above a component layer, a stack of memory cells above the component layer and laterally adjacent to the interconnect layers, a conductor extending vertically through the memory cells, a gap shorter than the height of the stack of memory cells separating the stack of memory cells from a side wall of the dielectric material, and side faces of the memory cells that are not vertically aligned with side faces of any of the interconnects. A chemically metallic side wall layer may enable a dielectric-on-dielectric process, eliminating the need for a large transition area between logic and memory regions.

The present disclosure relates to the technical field of intelligent devices, and discloses a display device and a method for monitoring application software. The display device comprises a display, an embedded memory and a controller. The controller is configured to acquire, by an acquisition unit, a data amount of downloaded data of each process in a current detection period. The acquisition unit is a data amount acquisition channel arranged at a bottom layer of the controller. For each process, the acquisition unit acquires, by the acquisition unit, a sub-data amount of sub-data downloaded by each thread corresponding to the process in the current detection period. If the sum of the data amount of the process and the sub-data amount of the sub-data downloaded by each thread corresponding to the process reaches a preset downloaded data amount of application software corresponding to the process, the process and each thread corresponding to the process are prohibited from continuing to write downloaded data and sub-data into an eMMC in the current detection period, and the process and each thread corresponding to the process are prohibited from continuing to download in the current detection period, thereby avoiding a large amount of data written into the eMMC.

The invention relates to the field of heat dissipation of electronic equipment, in particular to communication equipment which comprises a case, a circuit mainboard, a high-power-consumption chip, a flexible connecting piece and a heat dissipation device, the circuit mainboard, the high-power-consumption chip, the flexible connecting piece and the heat dissipation device are arranged in the case, and a memory piece, a power module, a hard disk interface and a network card chip are embedded in the circuit mainboard. The high-power-consumption chip is electrically connected with the circuit mainboard through a flexible connecting piece and used for enabling the high-power-consumption chip to be independent from the surface of the circuit mainboard, and the high-power-consumption chip is detachably installed in the heat dissipation area of the heat dissipation device and used for heat dissipation. According to the heat dissipation equipment, rapid heat dissipation of the high-power-consumption chip in the communication equipment is improved, the energy consumption cost is reduced, and the problems that noise is generated by an existing heat dissipation mode, and the circuit mainboard is prone to short circuit and corrosion are effectively solved.

This application discloses a method, apparatus, device, and medium for assessing student knowledge status by integrating KAN and evidence theory, relating to the field of artificial intelligence technology. The method includes: constructing an enhanced feature representation that integrates question difficulty and discrimination; performing deep temporal modeling using a transformer encoder with an embedded memory decay operator; and employing KAN to map hidden state to beta-distributed evidence parameters, thereby achieving decoupled output of prediction probability and cognitive uncertainty. The beneficial effects include improving model parameter efficiency and interpretability, quantifying cognitive uncertainty to distinguish between true mastery and accidental guessing, enhancing the reliability of prediction results from the knowledge tracking model, and providing a credible assessment basis for smart education.

This application provides an apparatus comprising: an interposer including traces and conductive contacts disposed on a first interposer surface and a second interposer surface opposite to the first interposer surface; a computing device coupled to the contacts on the first interposer surface; a first memory array coupled to the contacts on the first interposer surface; and a second memory array embedded between the first and second interposer surfaces, the second memory array being oriented inverted relative to the first memory array, the second memory array being directly coupled to the first memory array and the computing device via traces in the interposer. This application also discloses and claims other embodiments.