129 results about "Controller architecture" patented technology

The present invention discloses a non-volatile memory storage system with two-stage controller, comprising: a plurality of flash memory devices; a plurality of first stage controllers coupled to the plurality of flash memory devices, respectively, wherein each of the first stage controllers performs data integrity management as well as writes and reads data to and from a corresponding flash memory device; and a storage adapter communicating with the plurality of first stage controllers through one or more internal interfaces.

Disclosed herein is a controller architecture that pairs a controller with a NVM (non-volatile memory) storage system over a high-level, high speed interface such as PCIe. In one embodiment, the NVM storage system includes a bridge that communicates with the controller via the high-level interface, and controls the NVM via an interface (e.g., ONFI). The controller is provided a rich set of physical level of controls over individual elements of the NVM. In one embodiment, the controller is implemented in a higher powered processor that supports advanced functions such as mapping, garbage collection, wear leveling, etc. In one embodiment, the bridge is implemented in a lower powered processor and performs basic signal processing, channel management, basic error correction functions, etc. This labor division provides the controller physical control of the NVM over a fast, high-level interface, resulting in the controller managing the NVM at both the page and block level.

A separate control system may be configured for a combined sensor device. Alternatively, at least part of the control system may be included in another device, such as a processor of a mobile device. Software for handwriting, touch and fingerprint detection may be included in the control system. Low, medium and high resolution may be obtained with a single combined sensor device by scanning a subset of the sensels, or by aggregating lines or columns. Power consumption may be reduced by aggregating sensor pixels (or rows or columns) electrically using the controller, so that they perform as a low power small array until higher resolution with a larger array is needed. Power consumption may be reduced by turning off portions or all of the sensor device, turning off parts of the control system, and/or employing first-level screening at a reduced frame rate.

Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design also includes programmable input/output blocks for coupling selected signals to external pins. The memory components also include user programs that the embedded microprocessor executes. These programs may include instructions for programming the digital and analog blocks “on-the-fly,” e.g., dynamically. In one implementation, there are a plurality of programmable digital blocks and a plurality of programmable analog blocks.

A system, method and program product in a Model-View-Controller architecture for communicating between objects such as a Model object and a View object. A transform object is provided in the interface between any of the conventional Model, View and Controller objects such that transformation of data types into appropriate other data types is accomplished outside of the MVC object. This relieves the recipient MVC object of the responsibility of being designed to support multiple data types in order to perform a function.

Described embodiments provide a method of transferring data from host devices to a media controller. The media controller generates a transfer context for each write request received from a host device. Receive-data threads corresponding to data transfer contexts for each transfer context are generated, each receive-data thread corresponding to a data transfer between a host device and the media controller. Buffer threads corresponding to data transfer contexts for each transfer context are generated, each buffer thread corresponding to a data transfer between the receive data path and a buffer subsystem. The receive-data and buffer threads are tracked for each transfer context. For each tracked transfer context, data from the receive datapath is iteratively transferred to the buffer subsystem for a previous data transfer context of the buffer thread while data from the host device is transferred to the receive datapath for a subsequent data transfer context of the receive-data thread.

A fault tolerant, multi-protocol shelf management controller architecture that is extensible provides an intelligent platform management interface that is version indifferent as well as programmable and reconfigurable. The shelf management controller is arranged in a dual redundant configuration in a client-server mode and has a message driven configuration with the messages conforming to the Intelligent Platform Management Interface (IPMI) specification as extended by PICMG 3.0. In one embodiment, each shelf management controller includes at least one bit stream processor comprising sequenced stage machines implementing one or more finite state machines associated with one or more devices that are under control of the shelf management controller. The finite state machines could be hardware or software based. The shelf management controller is also modeled as a layered architecture that includes an IPMI API layer. The IPMI API layer enables the shelf manager to interface with legacy and future IPMI specifications.

A brake control system for brake by wire applications having a dual fail-silent pair controller architecture. The system utilizes two supervisory controllers and a shared monitoring controller to achieve the dual fail-silent pair configuration. The brake control system also features a mechanism whereby the monitoring controller ensures the fail-silent operation of the brake control units in the event of certain undesired events occurring within the system by assuming control of the affected brake control units. The control system further assures that no single event, including an event related to the monitoring controller, causes loss of more than half the braking functionality. The control system also features additional redundancy with regard to the brake command signals by sharing a separate unprocessed brake command signal with each of the supervisory controllers and the monitoring controller.

Preparing a computer software application for static analysis by identifying a control flow within a model portion of a computer software application having a model-view-controller architecture, where the control flow passes a value to a controller portion of the computer software application, analyzing a declarative specification of the controller portion of the computer software application to identify a view to which the controller portion passes control based on the value, and synthesizing a method within the computer software application, where the method calls the view.

A motor controller architecture and method of operating the same. The motor controller includes a function for estimating the low speed operation of the motor, for example by evaluating the response to a periodic excitation signal injected into the control loop of the controller architecture. A periodic excitation signal in the form of a square wave allows for analysis of the response of the motor without requiring demodulation, which allows the frequency of the excitation signal to be above the audible range. Control logic for controlling the motor at transitional speeds between low speed control and high speed (back emf) control is provided in some embodiments.

The invention relates to a deadline-fixed PFM (pulse frequency modulation) mode switching power supply controller belonging to the technical field of power integrated circuits, and mainly relates to the application area of BOOST switching power supplies. The switching power supply controller comprises an error amplifier (107), a frequency compensation network (106), a comparator (104), a deadline-fixed PFM control module (101), a maximum frequency limit module (102), a power switching tube drive circuit (103), a current sampling module (105) and a power switch (108). The PFM controller architecture is simple in implementation mode, can work in an interrupted current mode and can also work in a continuous current mode; and in practical application, the controller has the advantages of small size of external energy storage elements, low ripple voltage in case of a light load, low switching loss and high efficiency in case of a heavy load, and the like.

The invention provides a self-adaptive I/O (Input / Output) scheduling method of a multi-control storage system. The self-adaptive I/O scheduling method of the multi-control storage system has the advantages of being capable of achieving load balance of a multiple controller architecture and among controllers; avoiding risk and performance choke points caused by single controller failure; supporting a plurality of host connecting interfaces; supporting an ISCSI (Internet Small Computer System Interface), an FC (Fibre Channel), an InfiniBand and 10 gigabit network connection; being capable of providing high bandwidth IB (InfiniBand) and the 10 gigabit network connection for users at the same time; and meeting the differentiation requirements of customers for high bandwidth and high performance. The invention relates to I/O scheduling of the multi-control storage system and provides the I/O scheduling method among multiple controllers. When the multi-control storage system accepts an I/O request from an application layer, the self-adaptive I/O scheduling method of the multi-control storage system can be utilized to schedule the I/O request to the multiple controllers to perform simultaneous concurrent execution, not only allocates unallocated I/O requests to low load controllers, but also reschedules I/O requests to lower load controllers from overload controllers, so that the load state of every controller in a system is improved, I/O load scheduling and balance on multi-control nodes are achieved, potentials of equipment are fully scheduled, and the performance of the system is improved.

The invention relates to a secure communication method for a distributed multi-granularity controller of a software defined network based on proxy, and belongs to the technical field of inter-domain secure communication of a multi-domain SDN. The method comprises the following steps: designing architecture of a distributed multi-granularity security controller, wherein the architecture comprises a message data packet format between controllers, establishing a communication tunnel via the connection between a controller domain and inter-domain proxies and the connection between the inter-domain proxies, and completing neighbor discovery between the controller, two-step identity authentication and encrypted transmission to achieve direct communication between multi-domain network controllers. In the communication method, the infrastructure is based on the security controller and the inter-domain proxies, a message of a control plane is released to a data plane by the inter-domain proxies for transmission, and thus the communication problem between independent control planes is solved; and meanwhile, the two-step authentication scheme of communication of the controller is given based on a challenge response mechanism and a DTLS protocol, service supply can be defended and refused, and the identity authentication is completed to improve the security.

Avionic display systems and methods are provided for generating avionic displays, which include symbology and other graphics pertaining to forecast overpressure events, which are forecast to occur during supersonic aircraft flight. In various embodiments, the avionic display system includes a display device on which an avionic display is produced. A controller architecture is operably coupled to the display device. Storage media contains computer-readable code or instructions that, when executed by the controller architecture, cause the avionic display system to determine whether an overpressure event is forecast to occur due to the predicted future occurrence of a sonic boom, which has a magnitude exceeding a boom tolerance threshold. When the controller architecture determines that an overpressure event is forecast to occur, the avionic display system further generates symbology on the avionic display indicative of or visually signifying the forecast overpressure event.

Described embodiments provide for transferring data between a host device and a storage media. A host data transfer request is received and a total size of the data transfer is determined. One or more contexts corresponding to the total size of the requested transfer are generated and are associated with transfers of data. If the data transfer is a write operation, one or more data segments from the host device are transferred into a buffer. The combined size of the data segments corresponds to the total size of the data transfer. In accordance with the contexts, the one or more data segments are transferred from the buffer to the storage media. If the requested data transfer is a read operation, in accordance with the contexts, data from the storage media is retrieved into a buffer and grouped into one or more segments, which are transmitted to the host device.

Systems and methods for designing a programmable solid state drive (SSD) controller and a non-volatile memory apparatus are provided. The disclosed systems and methods utilize data structures, termed “Superbufs” for organizing internal activities in an SSD controller. Superbufs can be used for providing control flow services, such as, sequencing, synchronization, completion, and interrupt generation, as well as data flow services, for example, data transfer, data transformation, and data distribution.

A highly parallel computer system including dual processors and dual memory controllers are coupled to an Assisted Gunning Transceiver Logic Plus (AGTL+) high speed system bus. The microprocessors are designed for a quad processor architecture requiring four processors and four connectors for the processors. To maintain signal timing and integrity in a dual processor/dual memory controller architecture, additional terminations are inserted. Printed circuit board space is conserved with a dual processor architecture. The additional connectors and traces to the additional connectors for the processors are no longer needed. Furthermore, with the dual processor design, there is no need for two additional termination cards.

At present, two multi-controller architecture models mainly exist in software defined networking, namely, a distributed multi-controller architecture model and a centralized multi-controller architecture model. The two architecture models have advantages and defects. Even though the distributed multi-controller architecture model can effectively solve the problem of a single controller in performance and reliability, time delay of message transmission among a plurality of distributed controllers is long. Even though the centralized multi-controller architecture model can effectively reduce time delay of message transmission among the controllers, the defects of centralized control still exist. Therefore, the invention provides a distributed-centralized type multi-controller architecture model to avoid the defects of the previous architecture models. On this basis, a multi-controller load balancing method based on the distributed-centralized type architecture model is provided. Therefore, the load of the whole networking can be distributed in a balanced mode.

A motor controller architecture and method of operating the same. The motor controller includes a function for estimating the low speed operation of the motor, for example by evaluating the response to a periodic excitation signal injected into the control loop of the controller architecture. A periodic excitation signal in the form of a square wave allows for analysis of the response of the motor without requiring demodulation, which allows the frequency of the excitation signal to be above the audible range. Control logic for controlling the motor at transitional speeds between low speed control and high speed (back emf) control is provided in some embodiments.

A dual display mode portable computer is disclosed. The portable computer includes a flat-panel display, and a display controller for outputting an internal video signal to the flat panel display. The portable computer further includes means for receiving an external video signal, and a multiplexer for outputting the internal video signal to the flat-panel display during a first display mode, and for outputting the external video signal to the flat-panel display during a second display mode, thereby enabling the portable computer to act as a display device for an external computer.