68 results about "Wear leveling" patented technology

The invention discloses an SSD B + tree indexing method and system based on wear leveling, and relates to the technical field of database indexing structure optimizing.The method comprises the steps that B + tree logic nodes and SSD physical addresses are decoupled, and a dynamic node mapping table is introduced; replacing local updating with additional updating, and writing the new version of the node into a new position of the SSD; when a write-in address is allocated to the node, an allocation strategy considering a block wear state is adopted, and write operation is guided to an area with relatively light wear; during garbage collection, high-wear blocks are preferentially treated to integrate wear. According to the method, the problems of writing hot spots and unbalanced abrasion of the B + tree on the SSD are effectively solved on the database software level, the service life of the SSD can be remarkably prolonged while the high performance of the B + tree is kept, and the method has very high universality and practical value.

The invention relates to the technical field of intelligent chips, in particular to an NAND wear leveling method based on integrated circuit ECC (error correction code) and read delay, which comprises the following steps: acquiring read delay data and error correction code usage amount of a three-layer unit page of a target block in an NAND flash memory chip; on the basis of the read delay increment and the error correction code increment of the middle-layer page, the health index of the target block is calculated by combining the read delay difference value of the middle-layer page and the lower-layer page, the target block is divided into a plurality of health levels, and logic blocks of different health levels are mapped to different physical planes of the NAND flash memory chip; synchronously executing data migration and erasure operations of the plurality of blocks to be migrated by utilizing the parallel erasure capability of the multi-plane architecture for the target block of which the health level is degraded to a preset threshold value; and monitoring the deviation degree between the current read delay and the specification read delay in real time, and selecting the error correction strength grade of the error correction code according to the deviation degree.

The invention relates to a solid state disk dynamic wear balancing method and system based on data popularity, and the method comprises the steps: tracking the access characteristics of each data page in a solid state disk through a page-level counter, and enabling the access characteristics to comprise the write operation frequency, the modification period and the survival time; the data pages are dynamically divided into high-heat data, medium-heat data or cold data based on a preset threshold value, and corresponding heat layering labels are marked; collecting accumulated writing times and I / O request queue length of each channel of the solid state disk in real time, and calculating wear imbalance degree and load imbalance degree; performing data exchange according to a preset exchange mode priority based on the popularity hierarchical label, the wear imbalance degree and the load imbalance degree; and updating the logic mapping table and the channel state parameters, carrying out statistics on the balance income and the system overhead, and dynamically correcting the tolerance coefficient based on the current load type according to the income-overhead ratio.

The invention discloses a flash memory management method and a flash memory management device capable of balancing wear degree, and relates to the technical field of storage. According to the flash memory management method capable of balancing wear degree, blocks of different wear degree hierarchies are forced to be uniformly mixed and distributed to each region based on a hierarchical polling partitioning strategy, so that the wear degree is balanced; the abrasion degrees between the areas and in the areas are effectively promoted to approach to an equilibrium state, and the situation that local blocks fail in advance due to excessive abrasion is avoided; a double-layer erasure cycle sequence table is established for erasure operation of the flash memory, ascending sorting is performed according to the actual wear degree of each block, and the blocks with low wear degree are erased preferentially, so that global wear balance of the flash memory is synchronously realized while the complexity and the frequency of sorting calculation are reduced, the service life of the flash memory can be remarkably prolonged, and the service life of the flash memory is prolonged. And the calculation load and resource consumption of the system can be greatly reduced.

Mechanisms for controlling background wear leveling are provided, including: increasing a first counter; comparing the first counter to a first threshold; and in response to the first counter meeting the first threshold: decreasing the first counter by a value of the first threshold; and triggering background wear leveling. In some embodiments, the first counter is increased in response to receiving a write trigger. In some embodiments, the first threshold is based upon a page size and a number of planes of physical media of an SSD. In some embodiments, the mechanisms further comprise: incrementing a second counter in response to receiving a host write trigger; comparing the second counter to a second threshold; and in response to the second counter meeting the second threshold, decreasing the second counter by the second threshold, wherein the increasing the first counter is performed in response to the second counter meeting the second threshold.

A data storage system may include a memory device and a controller. The memory device may include a plurality of virtual blocks. The controller may include at least one processor and a memory. The memory may include instructions stored thereon, that when executed by the at least one processor, cause the at least one processor to: monitor a number of program / erase cycles for the plurality of virtual blocks; collect read errors for the plurality of virtual blocks; select a virtual block of the plurality of virtual blocks to open based on the number of program / erase cycles and the collected read errors; and write data to the selected open virtual block.

The invention discloses a door lock operation log management method applied to an intelligent door lock and the intelligent door lock. The door lock operation log management method comprises the following steps: receiving a door lock operation log plaintext, and converting the door lock operation log plaintext into coded log data in a preset format; determining an active sector in the plurality of storage sectors, and writing the coding log data into a current to-be-written address of the active sector; updating metadata of the active sector after writing, wherein the metadata at least comprises a next to-be-written address, the number of logs of the current sector and sector state information; and judging whether the active sector is fully written or not, and when the active sector is fully written, selecting a next storage sector from the plurality of storage sectors for erasing, and setting the next storage sector as a new active sector, so as to realize cyclic coverage and wear balance of the sectors. According to the invention, through log coding compression and sector rotation management, the space occupied by the log is reduced, and the FLASH utilization rate is improved; and wear balance is realized through cyclic coverage.

The application discloses a kind of support in-orbit program reconfiguration's satellite-borne solid-state memory, belong to electronic information field.Satellite-borne solid-state memory includes control core, data storage array, cache unit, refresh loading circuit, interface unit, program storage unit, control core realizes the control of storage array, parse host computer instruction, bad block management, wear leveling and address management, cache unit effectively prevents single event upset error.Storage array avoids the timing violation of FPGA that can appear under high main frequency and other difficult problems.Load refresh circuit uses refresh loading circuit to refresh FPGA internal program regularly, reduces the influence of single event upset.Interface unit realizes the control management of host computer to satellite-borne solid-state memory.Program storage unit selects storage carrier according to function, storage capacity size, read-write bandwidth requirement.The whole hardware design is with FPGA soft core to realize the control management function of satellite-borne solid-state memory, and special CPU hardware does not have to be designed.

Methods, systems, and devices for sacrificial block pool are described. For instance, a memory device may allocate a first pool of blocks and a second pool of blocks. The first pool of blocks may be associated with access operations in which each memory cell stores a single bit and the second pool of blocks may be associated with operations where each memory cell stores a single bit or multiple bits. The memory device may perform access operations according to the allocation, where for the access operations a first wear-leveling criteria is applied to a first subset of the second pool of blocks and a second wear-leveling criteria is applied to a second subset of the second pool of blocks. The memory device may move a block of the second subset to the first pool of blocks based on an amount of access operations associated with the block satisfying a threshold.

Provided are a solid-state drive and a wear leveling method. The solid-state drive includes a plurality of zones, a mapping relationship and an SSD controller. The SSD controller is configured to: determine, according to the mapping relationship, an identifier of a first target zone corresponding to an identifier of a to-be-written zone in response to receiving a data write command from a host drive unit, and write the to-be-written data to the first target zone. The data write command carries the identifier of the to-be-written zone determined by the host drive unit and to-be-written data, the mapping relationship includes an identifier of an alternate zone corresponding to an identifier of each of the plurality of zones, and the alternate zone of each zone is a zone, determined from the plurality of zones, with fewest programmed / erased cycles.

This disclosure provides for improvements in managing multi-drive, multi-die or multi-plane NAND flash memory. In one embodiment, the host directly assigns physical addresses and performs logical-to-physical address translation in a manner that reduces or eliminates the need for a memory controller to handle these functions, and initiates functions such as wear leveling in a manner that avoids competition with host data accesses. A memory controller optionally educates the host on array composition, capabilities and addressing restrictions. Host software can therefore interleave write and read requests across dies in a manner unencumbered by memory controller address translation. For multi-plane designs, the host writes related data in a manner consistent with multi-plane device addressing limitations. The host is therefore able to “plan ahead” in a manner supporting host issuance of true multi-plane read commands.

The application discloses a kind of hardware supplement method, system and circuit of space data processing and knowledge management system, belong to spaceborne data processing technical field, for solving existing spaceborne data processing relies on central processing unit and software architecture, it is easy to be affected by space single particle effect, space radiation interference and appear operation exception, real-time and reliability insufficient problem.The core method of the application includes: reading cache knowledge according to time decay calculation current confidence;Data packet hop count or survival time is directly discarded when exceeding limit;After inter-satellite link interruption recovers, master artificial intelligence node is elected according to preset rule and conflict is judged;When cache is written, it is accumulated to the minimum writing unit after being written once, and wear leveling is triggered according to the number of erasing and writing.The whole process of the application is automatically executed by pure hardware circuit, without central processing unit, without instruction execution, without software code running, with the characteristics of anti-radiation, high real-time, high reliability, can be adapted to space on-orbit environment.

A computer-implemented method of operating a counter is described, the method comprising: i) performing a counting operation, where the counting operation is performed in a bitwise manner, in particular using Gray codes; ii) segmenting the counting operation using wear leveling; and iii) performing an error correction scheme for the count operation using majority voting.

The invention relates to the technical field of storage management, and discloses a wear leveling method of a memory and electronic equipment. The wear leveling method comprises the following steps: when a data reading operation is executed on a current storage block, determining the number of ECC (Error Correction Code) bits generated by the data reading operation and the historical erasure times of the current storage block; comparing the number of ECC error correction bits with a risk threshold, wherein the risk threshold is determined based on the historical erasure times and the maximum ECC error correction capability; and if the number of the ECC error correction bits is greater than the risk threshold, judging that the current storage block is a risk block, and executing a preset risk response operation on the risk block. According to the embodiment of the invention, the storage blocks with deteriorated states can be found and isolated in advance, and data loss or system crash caused by sudden errors is avoided; the data reliability is improved, and the storage blocks are eliminated before approaching the ECC error correction limit; the service life management is more accurate and reliable, the potential of each block is fully utilized, and meanwhile high-risk use is avoided.

This invention provides a method and device for predicting the lifespan of a solid-state drive (SSD) based on predictive wear leveling. The method acquires a snapshot sequence of the SSD's wear state and a historical wear leveling scheduling record. It performs a wear trend state space reconstruction operation on the acquired data, iteratively injecting historical migration operation information as a state perturbation factor into the state transition matrix to obtain a set of wear evolution correction trajectories including a deviation correction factor. Based on the deviation correction factor, it dynamically adjusts the wear threshold to generate a set of imbalance tolerance thresholds at the storage unit level. It compares the predicted wear index value sequence with the imbalance tolerance thresholds to identify predictive wear imbalance units. Based on the identification results, it generates a set of dynamic wear leveling strategies. This method integrates historical wear leveling operations as perturbation factors into the wear prediction process, enabling early identification and targeted intervention of wear imbalance units.

The application relates to a NAND FLASH-based file data access method and device, equipment and a storage medium, and relates to the technical field of file storage. The method comprises the following steps: acquiring file data; selecting a writable storage block from a NAND FLASH as a current storage block based on block attributes; writing data in the file data which has not been written into the NAND FLASH into the current storage block; judging whether the data in the file data which has not been written into the NAND FLASH has been written into the current storage block; if not, repeating the step of selecting a writable storage block from the NAND FLASH as the current storage block until the file is completely written into the NAND FLASH; if a plurality of writable storage blocks are selected as the current storage block, the first selected writable storage block is a file head block, the last selected writable storage block is a file tail block, and the remaining selected writable blocks are ordinary storage blocks. The application has the effect of improving the performance of NAND FLASH wear leveling.

Systems, methods, and apparatus for memory management operations in a memory device. In one approach, wear leveling for the memory device is performed using a start-gap algorithm. The wear leveling is implemented using multiple gap locations in a single pool. In response to a memory management command, one or more gap locations and corresponding user data are moved. After moving the user data, one or more pointers to the gap locations are updated. A start location pointer for the pool is updated each time the gap locations complete a cycle of movement in the pool.

This invention provides a method, circuit, and system for managing wear leveling in non-volatile memory. First, a raw physical block address (PBA) for a logical block address (LBA) used for a write operation is received. The raw PBA is one of a set of PBAs for data blocks in a non-volatile memory array. Each of these PBAs is uniquely mapped to a specific LBA using a multi-level interconnect network (MIN). Next, a swapped PBA is determined for the LBA. The swapped PBA can be selected from the set of PBAs uniquely mapped using the MIN. Then, the MIN can be configured to map the LBA to the swapped PBA. Finally, data from a first data block stored at the raw PBA can be swapped with data from a second data block stored at the swapped PBA.

The invention discloses a nonvolatile memory system for improving space irradiation capability, which provides convenience for a user to use through a hybrid integrated memory design, a memory architecture comprising a switch circuit, a logic control circuit, a program memory, a crystal oscillator and an NAND memory and a bad block management and wear leveling algorithm of an internal integrated NAND memory. And the requirements of a program memory in a satellite electronic system on high capacity, high reliability and low cost are met.

The application relates to a wear-balanced space management method and device, and relates to the technical field of storage space management.The method comprises the following steps: combining physical hard disks according to preset space sizes to obtain a plurality of corresponding preset storage spaces; counting write-related parameters for recording the data write-in conditions of the preset storage spaces; and based on the write-related parameters, selecting the preset storage space with the lowest relative write-in frequency to store the data corresponding to the next data write-in operation.The application counts the write-in conditions of the storage spaces, and reasonably allocates the storage spaces based on the differences in write-in frequencies, so that the wear conditions of the storage spaces are balanced, and the storage spaces can maintain a good performance level, thereby avoiding performance fluctuations.

The embodiment of the present disclosure discloses a wear leveling circuit applied to a memory and the memory, wherein the circuit comprises: a control module configured to read data write information in the memory and control a leveling module and an address mapping module to perform corresponding operations according to the data write information; the leveling module is configured to update a first parameter and a second parameter in the memory according to the control of the control module in response to the data write information reaching a preset condition, and return the updated first parameter and second parameter to the memory through the control module; and the address mapping module is configured to determine a mapping relationship between a logical storage address and a physical storage address in the memory after the leveling module updates the first parameter and the second parameter each time. The embodiment balances the inconsistency of read-write address distribution, improves the use rate of each physical storage address in the memory, prolongs the use time of the memory, and enhances the durability of the memory.

The embodiment of the invention provides a pluggable memory card writing rate monitoring method and device, a computer readable storage medium and a computer program product, and the method comprises the steps: carrying out aggregation writing in a writing path of a pluggable memory card in a preset duration, and generating an interval throughput sample; storing the interval throughput samples by adopting an FIFO (First In First Out) window with a preset capacity, and when the FIFO window is full, covering the oldest interval throughput sample by a newly entered interval throughput sample; calculating and counting write rate data of the pluggable memory card based on the interval throughput sample in the FIFO window, wherein the write rate data at least comprises an average write rate; and displaying the write rate data to a user. According to the embodiment of the invention, interval sampling and sliding windows are adopted, instantaneous jitter caused by system scheduling, cache back-brushing, FTL garbage collection / wear leveling and the like is suppressed, the anti-interference performance is high, the system operation stability can be improved, and the method has the advantages of low resource occupation, good platform compatibility, easiness in transplantation and the like.

This invention relates to the field of computer storage technology and discloses a storage cell wear equalization method based on tunneling effect compensation. The method includes: monitoring the characteristic offset of the write and erase durations of the physical address cells to be equalized with the number of operation cycles to determine the tunnel oxide aging factor; constructing a topological interference model by combining the spatial spacing between physical address cells and the data update frequency, and performing interference boundary calculations to determine the physical stress divergence profile generated by the compensation voltage pulse; selecting idle physical address cells with stress values ​​below a safety threshold as cold zone nodes, and then correcting the address mapping conversion logic and implementing write redirection. This invention utilizes address mapping conversion logic to resolve physical stress conflicts in the logical dimension, suppresses the loss of induced charge caused by tunnel oxide damage, and effectively improves the data retention characteristics and system stability of the storage medium at the end of its lifespan.

The invention relates to the technical field of data storage, and discloses a solid state disk service life prolonging method based on a wear leveling algorithm, and the method comprises the following steps: collecting physical block wear state data and logic block access thermodynamic data of a solid state disk; performing solid state disk global health degree evaluation processing based on the physical block wear state data and the logic block access thermodynamic data to generate solid state disk global health degree feature data; when wear balancing is carried out on the solid state disk to prolong the service life, logic block access thermodynamic data are collected in real time, logic data cold and hot partitions are dynamically updated, sudden changes of written loads and dynamic migration of data access locality can be perceived and adapted, and therefore a balancing strategy is adjusted in time when load characteristics change, and the service life of the solid state disk is prolonged. Concentrated abrasion of the specific physical block caused by sudden writing is relieved, and timeliness and effectiveness of the service life prolonging effect are improved.

The invention provides an IO block management method and system based on PCM storage. The method comprises the steps that a CXL interface receives multiple pieces of IO data block request information sent by a host; aggregating the plurality of pieces of IO data block request information to obtain a plurality of codes; aggregating the plurality of codes into a plurality of logic blocks; enabling each logic block to pass through an L2P mapping table to obtain a mapping relation between each logic block and the corresponding physical block; based on the mapping relation between each logic block and the corresponding physical block, obtaining a physical address redistributed by the logic block through a wear leveling algorithm; writing the logic block into the corresponding physical PCM medium according to the reallocated physical address of the logic block; through a flexible IO mapping mode, the PCM is prevented from being written into the same physical block all the time, it is guaranteed that each PCM physical block is used uniformly, and the reliability of a PCM storage system is guaranteed.

This application is directed to opcode storage for on-die microprocessors. A microprocessor can be formed on a die with a memory array. Opcodes for the microprocessor can be stored in the memory array, possibly along with other data (e.g., trace or statistical data) for use by or generated by the on-die microprocessor. A wear leveling algorithm can cause a number of rows within the memory array to not be used to store user data at any given time, and these rows can be used to store the opcodes and possibly other data for the on-die microprocessor. The on-die microprocessor can be initiated and run based on the opcodes stored in the memory array.

A wear leveling method, a memory storage device and a memory control circuit unit are provided. The wear leveling method includes: obtaining an open bit count of each physical erasing unit; determining whether there is a first physical erasing unit with the open bit count greater than a first threshold; and in response to there being the first physical erasing unit with the open bit count greater than the first threshold, performing a first wear leveling operation on the first physical erasing unit.

Methods, systems, and devices for wear leveling techniques using data characteristics are described. The described techniques provide for wear leveling across blocks of a memory system. A controller of the memory system may include additional criteria for determining a destination block for an operation, which may include a characteristic of data associated with the operation. The controller may select a destination block according to both an age of the block and the characteristic of the data. For example, the controller may select a relatively young block for data having a first characteristic and may select a relatively old block for data having a second characteristic. In some cases, the controller may partition free blocks into sub-pools based on an average age of virtual blocks (VBs) associated with each free block.

This invention belongs to the field of memory, specifically relating to a wear-aware space allocation method for persistent memory file systems based on multi-level bitmaps. The method includes constructing a fine-grained multi-granularity allocation heap based on the number of consecutive pages contained in the free block min-heap; constructing an index structure based on multi-level bitmaps based on the availability of the min-heap; and quickly locating the first available min-heap with a granularity greater than or equal to the requested granularity using the multi-level bitmap index structure, based on the selected granularity requested by the upper-layer application, and allocating the free block with the lowest average wear from this min-heap. This invention solves the problem of low wear leveling accuracy in existing persistent memory file systems, further improving wear accuracy; it also solves the problem of high performance overhead caused by large block partitioning and sub-block average wear, significantly improving the performance of persistent memory file systems.