987 results about "Memory chip" patented technology

The present application discloses a compute-in-memory chip, an instruction scheduling method, and a related apparatus. The compute-in-memory chip comprises an instruction memory, an instruction scheduler, and at least one compute-in-memory memory; each compute-in-memory memory comprises at least one storage array; the instruction memory is used for acquiring a first tensor instruction to be executed; and the instruction scheduler is used for scheduling, on the basis of the association relationship between the first tensor instruction and a second tensor instruction and the state of a target storage array needing to be operated for executing the first tensor instruction, the first tensor instruction to the compute-in-memory memory to which the target storage array belongs so that the compute-in-memory memory executes the first tensor instruction. According to embodiments of the present application, diversified compute-in-memory computing can be supported, efficient out-of-order execution scheduling of a tensor instruction set is achieved on the basis of the compute-in-memory chip, and the requirements of compute-in-memory technology for high concurrency and high throughput rate are met.

A buffer chip includes a chip select signal reception circuit for receiving one or more system chip select signals transmitted from a memory controller and a chip ID reception circuit for receiving chip ID information transmitted from the memory controller. The buffer chip also includes a chip select signal generation circuit that generates memory chip select signals by using the one or more system chip select signals and the chip ID information and a chip select signal transmission circuit that transmits the memory chip select signals to a plurality of memory chips.

A semiconductor module includes a plurality of memory chips in a memory cube are stacked along a first direction parallel to a plane formed by a second direction and a third direction perpendicular to the first direction. The memory cube includes first and third outermost surfaces in the third direction and second and fourth outermost surfaces in the second direction. Each of the memory chips includes a substrate and a wiring layer. The substrate includes first to fourth side surfaces along each of the first to fourth outermost surfaces. A first insulating film is included between the first to fourth outermost surfaces and the corresponding first to fourth side surfaces. Internal wirings included in the wiring layer are connected to electrodes provided on at least one of the second to fourth outermost surfaces. The memory cube is spaced apart from the semiconductor chips and performs signal transmission.

Disclosed embodiments include a computational memory system. The computational memory system includes at least one computational memory chip including one or more processor subunits and one or more memory banks formed on a common substrate. The at least one computational memory chip is configured to store one or more portions of an embedding table in the one or more memory banks, the embedding table including one or more feature vectors. The one or more processor subunits are configured to receive a sparse vector indicator from a host external to the at least one computational memory chip and, based on the received sparse vector indicator and the one or more portions of the embedding table, generate one or more vector sums.

Methods and apparatus are disclosed for implementing data augmentation within a storage controller of a data storage device based on machine learning data read from a non-volatile memory (NVM) array of a memory die. Some particular aspects relate to configuring the storage controller to generate augmented versions of training images for use in training a Deep Learning Accelerator of an image recognition system by rotating, translating, skewing, cropping, etc., a set of initial training images obtained from a host device and stored in the NVM array. Other aspects relate to controlling components of the memory die to generate noise-augmented images by, for example, storing and then reading training images from worn regions of the NVM array to inject noise into the images. Data augmentation based on data read from multiple memory dies is also described, such as image data spread across multiple NVM arrays or multiple memory dies.

The invention provides a packaging processing method and system for a storage chip and a medium, and belongs to the technical field of semiconductor packaging. The method comprises the following steps: constructing an initial three-dimensional model of a packaging body, cleaning and detecting a bare chip, and correcting the model after laser cutting; electrical, thermal and stress performances are simulated and optimized, multiple chips are integrated by adopting an SiP technology, and three-dimensional wiring of a substrate is completed; and after three times of cleaning, a molding process is optimized through mold flow simulation, a system-level mainboard is connected by utilizing a BGA technology, and finally, a full-performance test is completed. Through multi-stage simulation and process collaborative optimization, the packaging density, reliability and manufacturing yield of the storage chip are improved, and the method is suitable for industrial production of high-density integrated storage devices.

The embodiment of the invention discloses an internal memory, a chip and related electronic equipment. A target computing unit of the internal memory comprises a plurality of groups of primary multipliers, a plurality of adder trees and a plurality of secondary multipliers, one group of first-level multipliers is connected with one second-level multiplier through one adder tree; the group of first-level multipliers comprises a plurality of pairs of first multipliers, and each adder tree comprises a first adder, a second adder and a third adder; each pair of first multipliers respectively receive data to perform multiplication operation, and respectively input output results into the first adder to perform addition operation; each second adder receives the output results of the plurality of first adders or the second adder at the upper level to carry out addition operation, and respectively inputs the output results to the second adder at the lower level or the third adder; and each third adder receives the output results of the plurality of second adders to carry out addition operation, and inputs the output results to the secondary multiplier to carry out multiplication operation. By implementing the embodiment of the invention, the memory computing capability can be improved.

The invention belongs to the technical field of chip packaging, and particularly relates to a three-dimensional stacked DRAM (Dynamic Random Access Memory) packaging structure based on electro-coppering cylinders. The packaging structure specifically comprises a bottom-layer logic chip, a top-layer DRAM chip, a second-layer DRAM chip, a vertical copper column interconnection region, a bottom-layer packaging body, a top-layer packaging body, a second-layer packaging body, a planar interconnection region, a signal longitudinal transmission path, a C4 bump array and a micro bump array, the bottom-layer packaging body packages the bottom-layer logic chip, the vertical copper cylinder and the planar metal wire interconnection layer together in a plastic mode, and the top-layer packaging body and the second-layer packaging body are similar to the bottom-layer packaging body in function; according to the invention, the TSV is replaced by the off-chip copper cylinder manufactured by electroplating in the packaging stage, so that the longitudinal interconnection of the chip is realized, and the DRAM three-dimensional integration with lower cost and high reliability is further realized; and meanwhile, the design difficulty of a memory chip is reduced, the system storage capacity is improved, and the overall performance of the system is improved.

A chip test system and method are provided. The chip test system includes a memory chip, a test device, and a test interface. The memory chip has a power pad and a driver pad coupled to the power pad. The test device is configured to provide a test signal. The test interface is configured to provide multiple signal transmission paths. The test device transmits the test signal to the power pad of the memory chip through the test interface, obtains a monitor voltage generated by the driver pad, and adjusts a test voltage value of the test signal according to the monitor voltage. The test device comprises a precise measurement unit configured to measure the monitor voltage, and a switch element coupled to the precise measurement unit, and when the memory chip starts to be tested, the switch element is turned on.

The invention belongs to the technical field of chip design, and discloses a three-dimensional stacked heterogeneous in-memory computing system and a data interaction processing method thereof.The three-dimensional stacked heterogeneous in-memory computing system comprises a storage chip layer and an AI processing chip layer located below the storage chip layer, the storage chip layer is electrically connected with the AI processing chip layer, and the AI processing chip layer is electrically connected with the storage chip layer. The AI processing chip layer is of a heterogeneous storage and calculation integrated structure integrating an RRAM storage and calculation array and an SRAM storage and calculation array, and the RRAM storage and calculation array is used for storing system configuration data; and the SRAM memory array is used for writing read-write data of the memory chip layer and completing data processing in the array. According to the three-dimensional stacking heterogeneous storage and calculation integrated device, through heterogeneous cooperation of the RRAM and the SRAM storage and calculation integrated array, key problems existing in the prior art are fully balanced and considered, finally, the optimal design of a system architecture level is achieved, and core obstacles are cleared away for large-scale application of the three-dimensional stacking technology in the field of AI chips.

A memory media includes a first memory chip stacked over a substrate, a second memory chip stacked over the first memory chip, and a third memory chip stacked over the second memory chip. The first memory chip, the second memory chip, and the third memory chip are stacked in a staircase. Each of the first memory chip, the second memory chip, and the third memory chip includes outer chip pads disposed to form an outer row which is adjacent to a first edge; and inner chip pads disposed to form an inner row which is spaced apart from the first edge. The third memory chip is stacked over the second memory chip to expose the outer chip pads of the second memory chip and to cover the inner chip pads of the second memory chip.

Memory systems and methods of assembly are described in which a memory system includes a routing substrate, a processor on a first side of the routing substrate, a memory die stack on the first side of the routing substrate, and a buffer bridge die embedded in the routing substrate and electrically connecting the memory die stack with the processor.

The invention discloses an FPGA-based DDR3 cache circuit, which comprises an interconnection structure of an FPGA chip and a plurality of DDR3 storage chips, point-to-point direct connection is adopted for DQ / DQS / DM signals of the DDR3 chips, control / address / clock signals are shared with the DDR3 chips through a Fly-by topological structure, and the sequential relationship between CK + / CK-and DQS + / DQS-is adjusted through a write-in equalization technology. Through the point-to-point direct connection design of DQ / DQS / DM signals, the problems of reflection and crosstalk in a traditional topological structure are eliminated, and the error code risk is reduced; the time sequence relation between CK + / CK-and DQS + / DQS-is dynamically adjusted through the write-in equalization technology, and time sequence deviation caused by PCB wiring length and impedance mismatching or temperature change is compensated; the Fly-by topological structure is connected with control / address / clock signals, so that signal branches and reflection are reduced, and signal attenuation and crosstalk are reduced.

A multi-chip package includes: a first semiconductor integrated-circuit (IC) chip; a second semiconductor integrated-circuit (IC) chip over and bonded to the first semiconductor integrated-circuit (IC) chip; a plurality of first metal posts over and coupling to the first semiconductor integrated-circuit (IC) chip, wherein the plurality of first metal posts are in a space beyond and extending from a sidewall of the second semiconductor integrated-circuit (IC) chip; and a first polymer layer over the first semiconductor integrated-circuit (IC) chip and in the space, wherein the plurality of first metal posts are in the first polymer layer, wherein a top surface of the first polymer layer, a top surface of the second semiconductor integrated-circuit (IC) chip and a top surface of each of the plurality of first metal posts are coplanar.

The invention discloses an intelligent memory chip high and low temperature test device and a test tuning method, and relates to the technical field of memory chip testing, the device comprises a test unit used for constructing a cold and hot test environment for a to-be-tested memory chip; the power supply unit is used for providing direct current for each unit; the management unit is used for detecting environment data in real time and uploading the environment data to the data acquisition and analysis server, and regulating and controlling the environment data in a closed-loop manner by combining a test instruction; the excitation generator is used for generating and sending test excitation for the to-be-tested storage chip according to the test instruction, recording test data and feeding back the test data to the data acquisition and analysis server; and the data acquisition and analysis server is used for pre-judging faults of the to-be-tested storage chip based on an AI model according to the real-time environment data and the test data, optimizing test instruction parameters or storage chip FTL algorithm parameters, generating a dynamic regulation and control test instruction and issuing the dynamic regulation and control test instruction. According to the invention, accurate test and optimization of the memory chip in an extreme temperature environment can be realized.

A method includes forming a reconstructed wafer, which includes forming a redistribution structure over a carrier, bonding a first plurality of memory dies over the redistribution structure, bonding a plurality of bridge dies over the redistribution structure, and bonding a plurality of logic dies over the first plurality of memory dies and the plurality of bridge dies. Each of the plurality of bridge dies interconnects, and is overlapped by corner regions of, four of the plurality of logic dies. A second plurality of memory dies are bonded over the plurality of logic dies. The plurality of logic dies form a first array, and the second plurality of memory dies form a second array.

This document describes apparatuses and techniques for die-based rank management for a memory system. In various aspects, a die-based rank controller (controller) can determine which memory dies of a memory device are not functional to store data and correlate rank selections of a memory system to ranks of other memory dies (e.g., functional memory dies). The controller may store information that indicates the correlation or mapping of the rank selections to the ranks of the other memory dies to enable access to those ranks of the memory system. In some aspects, the controller receives a command to access the memory device with a rank selection, and the controller enables access to a corresponding rank based on the information. By so doing, aspects of die-based rank management enable memory packages with non-functional memory dies to be used instead of discarded, which can increase production utilization or lower manufacturing costs.

A chip package includes a ball-grid-array (BGA) substrate; a first metal bump at a bottom of the ball-grid-array (BGA) substrate, wherein the first metal bump comprises tin; a field programmable chip package over and coupling to the ball-grid-array (BGA) substrate, wherein the field programmable chip package comprises a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip therein and a second metal bump at a bottom of the field programmable chip package and bonded to a top of the ball-grid-array (BGA) substrate; and a memory chip package under and coupling to the ball-grid-array (BGA) substrate, wherein the memory chip package comprises a first non-volatile memory (NVM) integrated-circuit (IC) chip therein and a third metal bump at a top of the memory chip package and bonded to the bottom of the ball-grid-array (BGA) substrate.

The invention discloses a method for realizing a redundant function memory chip test, which relates to the technical field of memory chip test, and comprises the following steps: calculating hyperedge coupling strength based on a hypergraph fault model, and generating a test vector sequence and a memory unit test instruction by adopting a weighted flipping mode according to the hyperedge coupling strength; injecting the test vector sequence into a tested memory chip, executing memory unit test instructions one by one, and capturing a failure unit coordinate and a failure mode category at the same time; constructing a Hall triad based on the failure unit coordinates and the failure mode category, executing theorem proving on the Hall triad by using a theorem proving device to verify the test completeness, generating an increment test vector when the verification fails, executing theorem proving again, and recording the result of the test completeness; according to the method, the hypergraph fault model is established, so that the coverage rate of non-independent faults is increased, the number of redundant test instructions is reduced, the test time and resource consumption are reduced, and the defect detection efficiency is improved.

The invention relates to a clock transfer circuitry for a multi-chip RAM. Apparatus and methods include a first memory chip including a first memory bank, a command input configured to receive a command and a chip identifier, and a decoder configured to determine whether the command is to use a clock on a second memory chip when the command matches a predetermined condition. The apparatus and method also include a second memory chip including a second memory bank and a clock receiver configured to receive the clock from the first memory chip for memory operations on the second memory chip. The first memory chip acts as a base chip for a memory chip stack including the first memory chip and the second memory chip. When the command matches the predetermined condition, the first memory chip is configured to send the chip identifier to the second memory chip to the clock receiver to activate the clock receiver prior to transmitting the command to the second memory chip.

The invention belongs to the technical field of data processing, and particularly discloses a memory chip ECC module adaptive verification method and device, and the method comprises the steps: perceiving the multi-source information of physics, environment and the like in real time through a multi-mode sensor array, generating a dynamic parameter fusion matrix, and analyzing the matrix data through a hybrid intelligent prediction model, prospectively predicting an error trend and generating a pre-selected error correction strategy; according to the prediction result and the environmental parameters, the storage array topology reconstruction is triggered to avoid the risk, and in combination with a digital twin model and a historical error pattern library, graded early warning is generated, the system risk is evaluated, and a differential response strategy is executed, so that the system can utilize system resources to the maximum extent while ensuring the security of core services; by using the block chain evidence storage and incremental federated learning technology, the verification system is endowed with reliable self-evolution ability, so that the whole verification system can adapt to a new threat mode and a continuously evolved application environment.

The utility model provides a BMC module based on a Loongson processor and hardware equipment, and relates to the technical field of computers.The BMC module based on the Loongson processor comprises the Loongson processor, a memory chip, a memory module, an analog-digital conversion module, a network module, a power module and a connector; the Loongson processor is electrically connected with the memory chip, the memory module, the analog-digital conversion module, the network module and the connector. According to the BMC module provided by the invention, based on the Loongson processor, peripherals such as a memory, a display and a network can be integrated in the BMC module, various peripheral interfaces are connected, and the function diversity of the BMC module is improved. Meanwhile, the BMC module is independent of a server mainboard and is interconnected by adopting a connector, so that independent maintenance and management are facilitated; and abundant peripheral interfaces are reserved through the connector, so that secondary development is facilitated, and the universality and practicability of the BMC module are improved.

According to the packaging structure and the forming method of the packaging structure, an electric function chip in the packaging structure is used for electronic signal processing, an optical chip can achieve big data throughput, a storage chip can achieve data storage, and when a second packaging body works, signals can be led out from the electric function chip, so that the second packaging body works. And photoelectric conversion and high-speed optical transmission are carried out through the optical chip, and data are stored by the storage chip, so that big data throughput can be realized. Therefore, the formed second packaging body can realize integration of multiple functions of electronic signal processing, optical signal transmission, data storage and the like, the function density and the integration level of the whole packaging are improved, the requirements of high bandwidth, large-capacity storage and rapid data processing are met, and the performance of the packaging structure is improved.

The invention relates to a system and method for implementing a scalable system. A multi-chip system (100) and structure for modular extension is described. In some embodiments, bonding strips (150) are used to couple adjacent chips (102, 104). For example, a communication bar (150) may be used to couple a logic chip (104), and a memory bar (150) may be used to couple a plurality of memory chips (102) to the logic chip (104).

The invention provides a memory chip, an operation method and a terminal, and the memory chip comprises a data storage circuit and a redundancy control circuit. The data storage circuit comprises a data storage array and is used for at least performing data signal writing and reading on a target storage unit in the data storage array, and the redundancy control circuit is used for receiving an original data signal and a verification data signal and performing similarities and differences verification on the original data signal and the verification data signal; the original data signal is a data signal written into the target storage unit, and the verification data signal is a data signal read from the target storage unit. According to the method and the device, the problems of interaction delay and energy consumption when the fault memory is detected by adopting an external algorithm in the prior art are solved.

The invention relates to the technical field of microelectronics, and discloses a three-dimensional stacked near-memory computing architecture, a chip and a data access method. The memory device comprises at least one computing chip layer and at least one memory chip layer which are stacked along a first direction, a plurality of vertical interconnection channels extending along the first direction; the memory chip layer comprises a plurality of memory banks; the computing chip layer comprises a plurality of computing cluster units; the computing cluster unit comprises at least one storage controller; and the storage controller is connected with at least one of the plurality of storage banks through the vertical interconnection channel and is used for managing data in the correspondingly connected storage banks. The problems that in a three-dimensional stacking computing architecture, storage access delay is high, and the bandwidth expansion capacity is limited are solved.

A memory management communication interface for a network-on-chip and a DDR controller. The memory management communication interface is connected to a host by means of the network-on-chip, and is connected to a DDR memory chip by means of the DDR controller. The memory management communication interface comprises: a request processing module, configured to receive a request packet from the host by means of the network-on-chip, and verify the integrity of the data format of the request packet; a response processing module, configured to send an ID unlocking request to the request processing module; and an output control module, configured to receive a read acknowledgment packet from the request processing module and a response packet from the response processing module, and further configured to handle a situation where the read acknowledgment packet and the response packet are received simultaneously. The memory management communication interface can ensure the security of data during the transmission of requests of multiple hosts over the network-on-chip, thereby improving the performance of a multi-chiplet Internet system.

The invention discloses an aging test system and method for a high-speed dynamic random access memory, and the system comprises a test board which is used for bearing at least one to-be-tested memory chip; the controller is used for generating and outputting a test excitation signal conforming to a corresponding memory technical standard; the power management module is used for providing adjustable power supply voltage for the memory chip to be tested according to the control instruction; the communication interface is used for realizing data interaction between the controller and an upper computer and reading configuration information of the memory chip to be tested; wherein a test parameter template library associated with various memory technical standards and product specifications is preset in the controller, and corresponding test parameter templates are automatically matched and loaded according to chip configuration information read by the communication interface so as to adapt to memory chips with different standards. According to the invention, a single hardware platform can be used for universally and adaptively testing various high-speed dynamic random access memories, and the testing efficiency and the equipment utilization rate are remarkably improved.

The invention discloses a full-data backup method for a fast and slow operation period of an industrial controller. The full-data backup method comprises the following steps: detecting whether a main power supply is powered down or a backup command is received by an FPGA (Field Programmable Gate Array); if yes, the FPGA writes the latest fast-cycle integrity data into the power-down nonvolatile storage chip by comparing the integrity marks and the timestamps of the fast-cycle data of the data A area and the data B area of the memory chip; then, the FPGA writes the completeness data of the latest slow period into the power-down nonvolatile storage chip by comparing the completeness marks and the timestamps of the data of the slow period of the data A area and the data B area of the memory chip; according to the data backup method, data does not need to be selected, one cycle of complete data can be recovered under the condition of power failure or no power failure, common memory chips and power failure non-volatile storage chips are used, and cost and implementation complexity are effectively reduced.

Provided is a semiconductor memory device including a plurality of semiconductor chips stacked on each other and having a novel structure different from the prior art. The semiconductor storage device comprises memory chips 1-1 and 1-2 which are stacked with each other. The memory chips 1-1, 1-2 include circuit elements and wirings arranged in the same layout between the memory chips 1-1, 1-2. The memory chips (1-1, 1-2) each have a front surface and a back surface facing each other, and a plurality of first terminals disposed on the front surface. In each of the memory chips 1-1, 1-2, the plurality of first terminals are arranged in mirror symmetry with respect to a plane of symmetry orthogonal to the front surface and the back surface. The memory chips (1-1, 1-2) are stacked such that the surface of the memory chip (1-1) is in contact with the surface of the memory chip (1-2), and the plurality of first terminals of the memory chip (1-1) are connected to the plurality of first terminals of the memory chip (1-2).