583 results about "Memory chip" patented technology

The embodiment of the invention discloses an internal memory, a chip and related electronic equipment. A target computing unit of the internal memory comprises a plurality of groups of primary multipliers, a plurality of adder trees and a plurality of secondary multipliers, one group of first-level multipliers is connected with one second-level multiplier through one adder tree; the group of first-level multipliers comprises a plurality of pairs of first multipliers, and each adder tree comprises a first adder, a second adder and a third adder; each pair of first multipliers respectively receive data to perform multiplication operation, and respectively input output results into the first adder to perform addition operation; each second adder receives the output results of the plurality of first adders or the second adder at the upper level to carry out addition operation, and respectively inputs the output results to the second adder at the lower level or the third adder; and each third adder receives the output results of the plurality of second adders to carry out addition operation, and inputs the output results to the secondary multiplier to carry out multiplication operation. By implementing the embodiment of the invention, the memory computing capability can be improved.

The invention belongs to the technical field of chip packaging, and particularly relates to a three-dimensional stacked DRAM (Dynamic Random Access Memory) packaging structure based on electro-coppering cylinders. The packaging structure specifically comprises a bottom-layer logic chip, a top-layer DRAM chip, a second-layer DRAM chip, a vertical copper column interconnection region, a bottom-layer packaging body, a top-layer packaging body, a second-layer packaging body, a planar interconnection region, a signal longitudinal transmission path, a C4 bump array and a micro bump array, the bottom-layer packaging body packages the bottom-layer logic chip, the vertical copper cylinder and the planar metal wire interconnection layer together in a plastic mode, and the top-layer packaging body and the second-layer packaging body are similar to the bottom-layer packaging body in function; according to the invention, the TSV is replaced by the off-chip copper cylinder manufactured by electroplating in the packaging stage, so that the longitudinal interconnection of the chip is realized, and the DRAM three-dimensional integration with lower cost and high reliability is further realized; and meanwhile, the design difficulty of a memory chip is reduced, the system storage capacity is improved, and the overall performance of the system is improved.

The invention belongs to the technical field of chip design, and discloses a three-dimensional stacked heterogeneous in-memory computing system and a data interaction processing method thereof.The three-dimensional stacked heterogeneous in-memory computing system comprises a storage chip layer and an AI processing chip layer located below the storage chip layer, the storage chip layer is electrically connected with the AI processing chip layer, and the AI processing chip layer is electrically connected with the storage chip layer. The AI processing chip layer is of a heterogeneous storage and calculation integrated structure integrating an RRAM storage and calculation array and an SRAM storage and calculation array, and the RRAM storage and calculation array is used for storing system configuration data; and the SRAM memory array is used for writing read-write data of the memory chip layer and completing data processing in the array. According to the three-dimensional stacking heterogeneous storage and calculation integrated device, through heterogeneous cooperation of the RRAM and the SRAM storage and calculation integrated array, key problems existing in the prior art are fully balanced and considered, finally, the optimal design of a system architecture level is achieved, and core obstacles are cleared away for large-scale application of the three-dimensional stacking technology in the field of AI chips.

The invention discloses an intelligent memory chip high and low temperature test device and a test tuning method, and relates to the technical field of memory chip testing, the device comprises a test unit used for constructing a cold and hot test environment for a to-be-tested memory chip; the power supply unit is used for providing direct current for each unit; the management unit is used for detecting environment data in real time and uploading the environment data to the data acquisition and analysis server, and regulating and controlling the environment data in a closed-loop manner by combining a test instruction; the excitation generator is used for generating and sending test excitation for the to-be-tested storage chip according to the test instruction, recording test data and feeding back the test data to the data acquisition and analysis server; and the data acquisition and analysis server is used for pre-judging faults of the to-be-tested storage chip based on an AI model according to the real-time environment data and the test data, optimizing test instruction parameters or storage chip FTL algorithm parameters, generating a dynamic regulation and control test instruction and issuing the dynamic regulation and control test instruction. According to the invention, accurate test and optimization of the memory chip in an extreme temperature environment can be realized.

The invention discloses a method for realizing a redundant function memory chip test, which relates to the technical field of memory chip test, and comprises the following steps: calculating hyperedge coupling strength based on a hypergraph fault model, and generating a test vector sequence and a memory unit test instruction by adopting a weighted flipping mode according to the hyperedge coupling strength; injecting the test vector sequence into a tested memory chip, executing memory unit test instructions one by one, and capturing a failure unit coordinate and a failure mode category at the same time; constructing a Hall triad based on the failure unit coordinates and the failure mode category, executing theorem proving on the Hall triad by using a theorem proving device to verify the test completeness, generating an increment test vector when the verification fails, executing theorem proving again, and recording the result of the test completeness; according to the method, the hypergraph fault model is established, so that the coverage rate of non-independent faults is increased, the number of redundant test instructions is reduced, the test time and resource consumption are reduced, and the defect detection efficiency is improved.

The invention relates to the technical field of microelectronics, and discloses a three-dimensional stacked near-memory computing architecture, a chip and a data access method. The memory device comprises at least one computing chip layer and at least one memory chip layer which are stacked along a first direction, a plurality of vertical interconnection channels extending along the first direction; the memory chip layer comprises a plurality of memory banks; the computing chip layer comprises a plurality of computing cluster units; the computing cluster unit comprises at least one storage controller; and the storage controller is connected with at least one of the plurality of storage banks through the vertical interconnection channel and is used for managing data in the correspondingly connected storage banks. The problems that in a three-dimensional stacking computing architecture, storage access delay is high, and the bandwidth expansion capacity is limited are solved.

A memory management communication interface for a network-on-chip and a DDR controller. The memory management communication interface is connected to a host by means of the network-on-chip, and is connected to a DDR memory chip by means of the DDR controller. The memory management communication interface comprises: a request processing module, configured to receive a request packet from the host by means of the network-on-chip, and verify the integrity of the data format of the request packet; a response processing module, configured to send an ID unlocking request to the request processing module; and an output control module, configured to receive a read acknowledgment packet from the request processing module and a response packet from the response processing module, and further configured to handle a situation where the read acknowledgment packet and the response packet are received simultaneously. The memory management communication interface can ensure the security of data during the transmission of requests of multiple hosts over the network-on-chip, thereby improving the performance of a multi-chiplet Internet system.

The invention discloses an aging test system and method for a high-speed dynamic random access memory, and the system comprises a test board which is used for bearing at least one to-be-tested memory chip; the controller is used for generating and outputting a test excitation signal conforming to a corresponding memory technical standard; the power management module is used for providing adjustable power supply voltage for the memory chip to be tested according to the control instruction; the communication interface is used for realizing data interaction between the controller and an upper computer and reading configuration information of the memory chip to be tested; wherein a test parameter template library associated with various memory technical standards and product specifications is preset in the controller, and corresponding test parameter templates are automatically matched and loaded according to chip configuration information read by the communication interface so as to adapt to memory chips with different standards. According to the invention, a single hardware platform can be used for universally and adaptively testing various high-speed dynamic random access memories, and the testing efficiency and the equipment utilization rate are remarkably improved.

A memory device which including a memory chip that includes a memory cell array connected to word lines and bit lines, a test circuit connected to the word lines and the bit lines, and a first bonding metal pattern connected to the word lines and the bit lines, and a peripheral circuit chip that includes a peripheral circuit and a second bonding metal pattern. The test circuit performs a test process on the memory cell array, and the memory chip and the peripheral circuit chip are connected in a bonding method for electrically connecting the first bonding metal pattern and the second bonding metal pattern.

A storage device includes a memory device and a memory controller to control the memory device by communicating with the memory device through a channel. The memory device includes a plurality of memory chips sharing the channel and each of the plurality of memory chips includes a transmission driver and an adaptive body bias generator. A target memory chip selected by the memory controller, among the plurality of memory chips, includes a first adaptive body bias generator and a first transmission driver. The first adaptive body bias generator applies a first body bias to the first transmission driver in a write mode in which the target memory chip receives a write data from the memory controller and applies a second body bias in a read mode in which the target memory chip transmits a read data to the memory controller.

A three-dimensional (3D) stacked memory package is described. The 3D stacked memory package includes a first plurality of stacked memory dies. The 3D stacked memory package also includes a first base die stacked on the first plurality of stacked memory dies. The 3D stacked memory package further includes a package substrate supporting the first plurality of stacked memory dies. The 3D stacked memory package also includes a first plurality of through silicon vias (TSVs) extending between the first plurality of stacked memory dies and a first compute block on the first base die. The 3D stacked memory package further includes a first set of wire-bonds coupled between the package substrate and a first physical IO interface (PHY) on the first base die.

A memory device includes a stacked memory, a plurality of conductive vias, and a memory controller. The stacked memory includes a plurality of memory chips. Each memory chip includes at least one memory cell array, a chip identification device, and a signal path switch. The chip identification device is coupled to the at least one memory cell array. The signal path switch is coupled to the chip identification device. The conductive vias penetrate through the stacked memory. The memory controller is coupled to the stacked memory.

Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, an integrated circuit (IC) base die is disclosed. The IC base die is configured to couple to a stack of memory die and includes a first port including a die-to-die (D2D) interface to couple to an IC device. A second port includes a memory interface to access a memory other than the stack of memory die. Memory control circuitry controls memory access operations directed to the memory other than the stack of memory die.

The invention relates to the technical field of data storage, and discloses an impedance matching test method for a memory chip, which comprises the following steps of: performing different impedance value matching tests on three dimensions of CA-odt, DQ-odt and SOC-odt of the memory chip to obtain different impedance combinations; performing impedance verification on the memory chip according to different impedance combinations; screening the memory chips outside the range of different impedance combinations, and determining the memory chips outside the range of different impedance combinations as the memory chips with obvious impedance differences, namely the memory chips with poor impedance matching; and screening the memory chips in the range of different impedance combinations, recording the impedance combinations passing through all the test items, and determining the effective working range of different impedance values of each dimension. According to the invention, the memory chip is ensured to have enough impedance matching tolerance under specific mainboard design and load conditions, so that the stability of long-term operation of the system is ensured.

The invention relates to the technical field of data storage, and discloses a method and system for optimizing test data collected by a memory chip based on machine learning, and the method comprises the steps: collecting original test data from a test platform of a to-be-tested memory chip; constructing a convolutional neural network model, learning a mapping relationship between test data features and memory defects through the convolutional neural network model, training the convolutional neural network model through the collected original test data, optimizing parameters of the convolutional neural network model according to a training result through a back propagation algorithm, and obtaining memory defects through the optimized parameters. The performance of the convolutional neural network model tends to be stable; converting a parameter vector output by the convolutional neural network model into a test vector executable by ATE; and taking the generated test vector as a new training sample, feeding back the new training sample to an original test data updating data set, and iteratively training and optimizing the convolutional neural network model. According to the invention, intelligentization of the test process is realized, and hidden defects sensitive to voltage and time sequence can be effectively captured.

The invention discloses a high-end memory chip asynchronous test system based on a distributed architecture, which relates to the technical field of chip testing, and comprises a state modeling module, a master control end initialization and test end access, memory chip test task pool construction, test end state analysis in combination with historical test load and historical fault information, and memory chip asynchronous test. Generating an optimized scheduling strategy; the scheduling module is used for performing task division and asynchronous scheduling on the memory chip test task pool by adopting an intelligent scheduling algorithm based on an optimized scheduling strategy to generate an asynchronous data flow queue; according to the issuing module, the test end receives the asynchronous data flow queue in an asynchronous mode to carry out protocol unpacking and task mapping, and a memory chip function test task is obtained and issued; according to the method, the test throughput rate and the resource utilization rate are improved by asynchronously sequencing and scheduling tasks, the task scheduling delay is reduced, the load of each test end is balanced, and meanwhile, the horizontal expansibility and the fault-tolerant capability are enhanced.

The embodiments of the present application provide a memory device and a method for preforming a write operation in a memory device. The memory device comprising: a memory chip comprising a plurality of memory cells made at a first process node; and a control chip comprising a control circuit made at a second process node, wherein the first process node is more advanced than the second process node; wherein the control chip and the memory chip are bonded together to form the memory device, and the control circuit is configured to control an operation of the plurality of the memory cells in the memory chip.

The invention provides a memristor memory chip aging prediction method and a computing device based on artificial intelligence, and belongs to the technical field of integrated circuits, the method comprises the steps of obtaining multi-dimensional device operation data by monitoring a device erasing process when a memristor memory chip executes a reasoning task in a working process, and performing aging prediction on the memristor memory chip; and constructing a data set containing the aging characteristics of the device, and predicting and classifying the aging state of the device based on an artificial intelligence algorithm. The computing device comprises a plurality of memristor storage / storage macros and a global aging prediction control / processing module, the memristor storage / storage macros can be configured as reasoning computing units for aging prediction, and real-time aging state prediction is carried out on other memristor storage / storage macros for processing actual edge AI tasks. And real-time aging state prediction can be carried out by the global aging prediction control / processing module. Through data-driven aging prediction and a systematic load balancing strategy, the overall service life and reliability of the memristor storage system can be effectively improved.

The utility model discloses an integrated solid-state nanopore biological detector, which relates to the technical field of biological detection and comprises a fluid pool shell, a solid-state nanopore silicon nitride chip and a PCB (printed circuit board), a sample injection hole is arranged on the fluid pool shell, the solid-state nanopore silicon nitride chip is arranged in the fluid pool shell, and the solid-state nanopore silicon nitride chip is arranged in the PCB. A silicon nitride window corresponding to the solid-state nanopore silicon nitride chip is formed in the fluid pool shell, a PCB (Printed Circuit Board) is fixed in the fluid pool shell, an RFID (Radio Frequency Identification Device) storage chip, a magnetic connector and silver electrodes are arranged on the PCB, and the silver electrodes are positioned on two sides of the silicon nitride window. According to the utility model, the RFID storage chip is arranged, so that the key information of the biological detector is stored and traced, and the problem of information management disorder in the prior art is solved; the RFID storage chip can store key information of the biological detector for a long time, and the integrity and traceability of the data are ensured.

A semiconductor package and a memory system are provided. The semiconductor package includes: a first device including a plurality of memory chips; and a second device configured to: provide a signal received from the first device through the first channel to an external device through the second channel; and providing a signal received from an external device through a second channel to the first device through the first channel, in which the second device includes: an equalization circuit configured to: equalize the signal received by the second device; a termination circuit configured to: control an electrical connection state of the termination resistor; and a bypass circuit configured to control the bypass switch based on noise of the signals received through the first channel and the second channel.

A method for managing data in a non-volatile memory system includes generating, by a randomizer integrated on a die of a memory device, padding data to close a memory block for a data write operation. The padding data is random data. The method includes programming, by a media controller of the memory device, the padding data into specified memory pages in a data block within the memory device. The data block stores user data for the data write operation and the padding data. The method includes executing, by a memory controller and by the media controller, a data integrity scan on a selected memory page of the specified memory pages of the data block. Execution of the data integrity scan includes re-generating, by the randomizer, the padding data and comparing the re-generated padding data with stored padding data sensed from the selected memory page to identify mismatch data.

The package-on-package (POP) structure includes a first package unit of three-dimensional fan-out memory chips and a SiP package unit of the two-dimensional fan-out peripheral circuit chip. The first package unit includes: memory chips laminated in a stepped configuration; a molded substrate; wire bonding structures; a first rewiring layer; a first encapsulating layer; and first metal bumps, formed on the first rewiring layer. The SiP package unit includes: a second rewiring layer; a peripheral circuit chip; a third rewiring layer, bonded to the circuit chip; first metal connection pillars; a second encapsulating layer for the circuit chip and the first metal connection pillars; and second metal bumps on the second rewiring layer. The first metal bumps are bonded to the third rewiring layer. Integrating the two package units into the POP is enabled by three rewiring layers and the molded substrate which supports the first package unit during wire bonding process.

Disclosed in the embodiments of the present application are an internal memory, a chip and a related electronic device. A target processing unit (202) of an internal memory (102) comprises a plurality of groups of primary multipliers, a plurality of adder trees and a plurality of secondary multipliers, wherein one group of primary multipliers is connected to one secondary multiplier by means of one adder tree; one group of primary multipliers comprises a plurality of pairs of first multipliers; each adder tree comprises a first adder, a second adder and a third adder; each pair of first multipliers separately receives data to perform multiplication operations, and separately inputs output results into one first adder for addition operations; each second adder receives output results of a plurality of first adders or the upper-level second adder, so as to perform addition operations, and separately inputs the output results into the lower-level second adder or one third adder; and each third adder receives output results of a plurality of second adders to perform addition operations, and inputs the output results into one secondary multiplier for multiplication operations. Implementing the embodiments of the present application can improve the processing capability of the internal memory.

This invention belongs to the field of communication automation technology and discloses a system and method for multi-dimensional collaborative optimization of HBM packaging technology for heterogeneous integration. Addressing the pain points of heterogeneous integrated HBM packaging technology, this invention constructs three core modules: precise adaptation of heterogeneous interconnect interfaces, collaborative control of multi-physics fields within the package, and intelligent molding of heterogeneous integrated microcavities. It employs core technologies such as energy spectrum control and contact adaptation of heterogeneous interconnect interfaces, simulation and control of thermal-mechanical-electrical multi-physics field coupling within the package, and precise molding and sealing of heterogeneous integrated microcavities. This overcomes the technical bottlenecks of traditional HBM packaging technology, including poor adaptability of heterogeneous interconnect interfaces, multi-physics field coupling interference within the package, and low molding accuracy of heterogeneous microcavities. It achieves high adaptability of heterogeneous interconnect interfaces, collaborative and stable control of multi-physics fields within the package, and high-precision leak-free molding of heterogeneous integrated microcavities. This significantly improves the interconnect reliability, structural stability, and heterogeneous integration compatibility of heterogeneous integrated HBM, adapting to the high-bandwidth memory chip packaging requirements of HBM6 and subsequent heterogeneous integration with logic chips and RF chips.

The application discloses a sensitive amplifier and a storage chip. The sensitive amplifier comprises a first clamping unit, a second clamping unit, a first current unit and a feedback unit. The control end of the first clamping unit is coupled with a total bit line through the feedback unit, so that the potential change of the total bit line forms a closed-loop control. That is, when the potential of the total bit line rises, the current flowing through the first current unit and the feedback unit is reduced, and the current flowing through the second clamping unit is increased. The potential of the control end of the first clamping unit is reduced, the current flowing through the first clamping unit is also reduced, and the potential of the total bit line is reduced to a preset potential and is kept stable. Conversely, the potential of the total bit line is increased to a preset potential and is kept stable.

A three-dimensional (3D) stacked memory package is described. The 3D stacked memory package includes a first plurality of stacked memory dies. The 3D stacked memory package also includes a first base die stacked on the first plurality of stacked memory dies. The 3D stacked memory package further includes a package substrate supporting the first plurality of stacked memory dies. The 3D stacked memory package also includes a first plurality of through silicon vias (TSVs) extending between the first plurality of stacked memory dies and a first compute block on the first base die. The 3D stacked memory package further includes a first set of wire-bonds coupled between the package substrate and a first physical IO interface (PHY) on the first base die.

The embodiment of the present application discloses a kind of test method and related device of storage chip, it is related to integrated circuit technical field, can test multiple types of storage chip, effectively expand the applicable scope of test object, to greatly reduce test cost.The method comprises: according to the pin type of the preset chip pin in the storage chip to be measured, the data transmission pin of test machine is configured, so that the data transmission pin is adapted to signal transmission with the preset chip pin;Wherein, the pin type includes control class, and the preset chip pin of the control class is used to transmit control class signal;The test machine is used to test the storage chip to be measured.The present application is applicable to the test of storage chip.

A device comprising a memory device comprising: a first memory chip; a second memory chip coupled to the first memory chip, wherein a front side of the first memory chip is coupled to a front side of the second memory chip; a third memory chip coupled to the second memory chip, wherein a back side of the second memory chip is coupled to a back side of the third memory chip through fusion bonding; and a fourth memory chip coupled to the third memory chip, wherein a front side of the third memory chip is coupled to a front side of the fourth memory chip.

This invention relates to the field of projection equipment technology, specifically providing a temperature-adaptive color correction system and method for DLP projection equipment. The system includes an optical temperature monitoring module comprising four temperature sensors for temperature monitoring; a main control processing module using a microcontroller as the core processor, comprising four ADC channels for color compensation calculation; and an execution drive module comprising a first subunit (RGB laser driver circuit connected to the microcontroller), a second subunit (multi-zone fan control circuit), and a third subunit (power management circuit) for heat dissipation control. The microcontroller is connected to an EEPROM memory chip via an I²C bus. A heat dissipation structure module includes four axial fans and corresponding air ducts for each fan. Multiple temperature sensors are placed on key optical components such as the RGB laser and DMD chip to monitor the actual operating temperature of each area in real time.

This application provides a storage circuit, a storage chip, and an electronic device. The storage circuit includes a sub-read circuit, read bit lines, at least one read auxiliary unit, and multiple static random access memory (SRAM) cells. The read bit lines are connected to the sub-read circuit, the at least one read auxiliary unit, and the multiple SRAM cells. The sub-read circuit performs read operations through the multiple SRAM cells. The read auxiliary unit is obtained by updating the circuit connections of the SRAM cells and is used to adjust the potential of the read bit lines. This not only improves the success rate of reading 1 operations and accelerates the speed of reading 0 operations, but also avoids excessive area overhead in the storage circuit.