1375 results about "Memory chip" patented technology

A multi-chip package comprising an interconnection substrate; a first semiconductor IC chip over the interconnection substrate, wherein the first semiconductor IC chip comprises a first silicon substrate, a plurality of first metal vias passing through the first silicon substrate, a plurality of first transistors on a top surface of the first silicon substrate and a first interconnection scheme over the first silicon substrate, wherein the first interconnection scheme comprises a first interconnection metal layer over the first silicon substrate, a second interconnection metal layer over the first interconnection layer and the first silicon substrate and a first insulating dielectric layer over the first silicon substrate and between the first and second interconnection metal layers; a second semiconductor IC chip over and bonded to the first semiconductor IC chip; and a plurality of second metal vias over and coupling to the interconnection substrate, wherein the plurality of second metal vias are in a space extending from a sidewall of the first semiconductor IC chip.

The invention relates to the technical field of electronic information, and discloses a high-reliability storage chip packaging test method and system.The method comprises the steps that firstly, a to-be-tested storage chip and original parameter information of the to-be-tested storage chip are obtained, packaging structure data are collected to construct a three-dimensional model, chip feature data are extracted, then the chip feature data are compared with standard reference data, and potential defect information is mined; suspicious packaging parts are screened, the sensitivity of the suspicious packaging parts to environmental parameters is monitored, then fault risk types are evaluated, weak links are positioned, performance is detected, specific problem points are found out, then a test planning target is formulated, test means and standards are clarified, a test operation instruction is generated, finally, packaging testing is executed, electrical performance data are collected, and stability is verified. And generating a packaging test report. The stability of the memory chip can be improved.

The invention relates to the technical field of chip packaging, and discloses an ultrathin multi-layer storage chip stacking packaging method, which comprises the following steps of: obtaining a storage chip to be packaged, performing chip quality division on the storage chip to be packaged to obtain a target chip, and performing fine classification on the target chip to obtain a plurality of groups of chips; performing thickness optimization on the multiple groups of divided chips to obtain thickness-optimized chips, and performing chip selection on the thickness-optimized chips to obtain selected chips; performing material coating on the selected chip to obtain a coated chip, performing chip curing on the coated chip to obtain a cured chip, and performing chip stacking on the cured chip to obtain a stacked chip; carrying out three-dimensional modeling on the stacked chips so as to carry out dispensing path planning on the stacked chips to obtain a dispensing path, and carrying out chip reinforcement on the stacked chips to obtain reinforced chips; and performing internal interconnection, preliminary packaging and shell injection molding on the reinforced chip to obtain a packaged chip. According to the invention, the packaging quality of the ultrathin multi-layer memory chip can be improved.

The invention discloses an edge end large language model inference system. The system comprises a main computing chip, an LPDDR interconnection resource and a vertically stacked and packaged storage chip stack, the storage chip stack comprises an NAND flash memory chip and a DRAM (Dynamic Random Access Memory) chip, and the NAND flash memory chip and the DRAM chip are paired and share an LPDDR interconnection resource; the NAND flash memory chip comprises a flash memory chip bare chip and a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) chip bare chip which are three-dimensionally interconnected based on hybrid bonding; a flash memory array is arranged on the flash memory chip bare chip; a logic block is arranged on the CMOS chip bare chip; the main calculation chip reads a parameter matrix of a model full connection layer from the NAND flash memory chip and reads other parameters from the DRAM chip for calculation in a pre-filling stage of large language model reasoning; and the NAND flash memory chip performs full connection layer calculation in a decoding stage. The system provided by the invention can improve the external transmission and internal reading bandwidth.

The present application discloses a compute-in-memory chip, an instruction scheduling method, and a related apparatus. The compute-in-memory chip comprises an instruction memory, an instruction scheduler, and at least one compute-in-memory memory; each compute-in-memory memory comprises at least one storage array; the instruction memory is used for acquiring a first tensor instruction to be executed; and the instruction scheduler is used for scheduling, on the basis of the association relationship between the first tensor instruction and a second tensor instruction and the state of a target storage array needing to be operated for executing the first tensor instruction, the first tensor instruction to the compute-in-memory memory to which the target storage array belongs so that the compute-in-memory memory executes the first tensor instruction. According to embodiments of the present application, diversified compute-in-memory computing can be supported, efficient out-of-order execution scheduling of a tensor instruction set is achieved on the basis of the compute-in-memory chip, and the requirements of compute-in-memory technology for high concurrency and high throughput rate are met.

A buffer chip includes a chip select signal reception circuit for receiving one or more system chip select signals transmitted from a memory controller and a chip ID reception circuit for receiving chip ID information transmitted from the memory controller. The buffer chip also includes a chip select signal generation circuit that generates memory chip select signals by using the one or more system chip select signals and the chip ID information and a chip select signal transmission circuit that transmits the memory chip select signals to a plurality of memory chips.

A semiconductor module includes a plurality of memory chips in a memory cube are stacked along a first direction parallel to a plane formed by a second direction and a third direction perpendicular to the first direction. The memory cube includes first and third outermost surfaces in the third direction and second and fourth outermost surfaces in the second direction. Each of the memory chips includes a substrate and a wiring layer. The substrate includes first to fourth side surfaces along each of the first to fourth outermost surfaces. A first insulating film is included between the first to fourth outermost surfaces and the corresponding first to fourth side surfaces. Internal wirings included in the wiring layer are connected to electrodes provided on at least one of the second to fourth outermost surfaces. The memory cube is spaced apart from the semiconductor chips and performs signal transmission.

The invention provides a storage and calculation integrated calculation module based on an OAM (Operation Administration and Maintenance) form, which is used for integrating a plurality of storage and calculation integrated chips of different types and realizing communication between a CPU (Central Processing Unit) and the storage and calculation integrated chips, and is characterized in that an external interface of the calculation module is connected with an external UBB (Universal Business Business) bottom plate by adopting an interface designed by an OAM protocol; the calculation module comprises a power supply interlayer card, a controller card and a memory operator card which are sequentially connected in a stacked mode, and the power supply interlayer card is configured in the mode that a power supply interface designed through an OAM protocol is used for conducting power supply conversion, supplying power to the controller card and the memory operator card and providing a path for data signal transmission between the controller card and a CPU on an external UBB bottom plate; the controller card is configured to perform conversion among different protocols, and communication and data signal transmission between the operator card and a CPU (Central Processing Unit) on the external UBB bottom plate; the storage operator card is configured to store a data signal and provide a chip connection interface for one or more storage and calculation integrated chips; and a data signal is transmitted to the storage and calculation integrated chip connected with the chip connecting interface through the chip connecting interface.

A system in package platform includes a processor chip having a runtime processor core, an accelerator core and a processor-memory interface exposed on a chip-to-chip bonding surface, a first memory chip such as 3D NAND flash memory storing a collection of executable models of inference engines, and a second memory chip storing weights of a selected executable model. The second memory chip can comprise a nonvolatile, random access memory, such as phase change memory. Direct vertical connections such as via-to-via connections, are provided between the processor chip and the second memory chip.

The embodiment of the invention provides a memory chip, a logic chip, a chip stacking structure and a memory, a global signal area of the memory chip is penetrated by a plurality of conductive through hole groups, each conductive through hole group comprises a first redundant conductive through hole group and a second redundant conductive through hole group, the first redundant conductive through hole group comprises a first conductive through hole and a fourth conductive through hole, and the second redundant conductive through hole group comprises a second conductive through hole and a third conductive through hole; the first redundant conductive through hole group is used for transmitting the same first global signal, and the second redundant conductive through hole group is used for transmitting the same second global signal.

Disclosed embodiments include a computational memory system. The computational memory system includes at least one computational memory chip including one or more processor subunits and one or more memory banks formed on a common substrate. The at least one computational memory chip is configured to store one or more portions of an embedding table in the one or more memory banks, the embedding table including one or more feature vectors. The one or more processor subunits are configured to receive a sparse vector indicator from a host external to the at least one computational memory chip and, based on the received sparse vector indicator and the one or more portions of the embedding table, generate one or more vector sums.

Methods and apparatus are disclosed for implementing data augmentation within a storage controller of a data storage device based on machine learning data read from a non-volatile memory (NVM) array of a memory die. Some particular aspects relate to configuring the storage controller to generate augmented versions of training images for use in training a Deep Learning Accelerator of an image recognition system by rotating, translating, skewing, cropping, etc., a set of initial training images obtained from a host device and stored in the NVM array. Other aspects relate to controlling components of the memory die to generate noise-augmented images by, for example, storing and then reading training images from worn regions of the NVM array to inject noise into the images. Data augmentation based on data read from multiple memory dies is also described, such as image data spread across multiple NVM arrays or multiple memory dies.

The invention provides a packaging processing method and system for a storage chip and a medium, and belongs to the technical field of semiconductor packaging. The method comprises the following steps: constructing an initial three-dimensional model of a packaging body, cleaning and detecting a bare chip, and correcting the model after laser cutting; electrical, thermal and stress performances are simulated and optimized, multiple chips are integrated by adopting an SiP technology, and three-dimensional wiring of a substrate is completed; and after three times of cleaning, a molding process is optimized through mold flow simulation, a system-level mainboard is connected by utilizing a BGA technology, and finally, a full-performance test is completed. Through multi-stage simulation and process collaborative optimization, the packaging density, reliability and manufacturing yield of the storage chip are improved, and the method is suitable for industrial production of high-density integrated storage devices.

The present disclosure provides a method, system, device, medium and program product for read-write control of a storage chip, the method comprising: generating a first check code corresponding to first data; writing the first data and the first check code to a target address of the storage chip; reading second data and the second check code from the target address; generating a third check code corresponding to the second data; and performing read-write control on the storage chip based on the second check code and the third check code. The present disclosure reads the second data and the second check code in the target address of the storage chip, generates a third check code according to the second data, and finally performs read-write control on the storage chip according to the second check code and the third check code, thereby realizing the function of self-checking and error correction of the storage chip, and ensuring the reliability of the data stored in the storage chip.

The present disclosure provides a logic chip, a memory chip, a chip stack structure, and a memory. The logic chip is provided with a plurality of channel signal regions, conductive vias in each one of the plurality of channel signal regions are divided into a plurality of repair unit groups, and each one of the plurality of repair unit groups includes four repair units, where a first repair unit and a second repair unit are arranged symmetrically about a first axis, a third repair unit and a fourth repair unit are arranged symmetrically about the first axis, and the first repair unit and the fourth repair unit are arranged symmetrically about a second axis.

The embodiment of the invention discloses an internal memory, a chip and related electronic equipment. A target computing unit of the internal memory comprises a plurality of groups of primary multipliers, a plurality of adder trees and a plurality of secondary multipliers, one group of first-level multipliers is connected with one second-level multiplier through one adder tree; the group of first-level multipliers comprises a plurality of pairs of first multipliers, and each adder tree comprises a first adder, a second adder and a third adder; each pair of first multipliers respectively receive data to perform multiplication operation, and respectively input output results into the first adder to perform addition operation; each second adder receives the output results of the plurality of first adders or the second adder at the upper level to carry out addition operation, and respectively inputs the output results to the second adder at the lower level or the third adder; and each third adder receives the output results of the plurality of second adders to carry out addition operation, and inputs the output results to the secondary multiplier to carry out multiplication operation. By implementing the embodiment of the invention, the memory computing capability can be improved.

The invention belongs to the technical field of chip packaging, and particularly relates to a three-dimensional stacked DRAM (Dynamic Random Access Memory) packaging structure based on electro-coppering cylinders. The packaging structure specifically comprises a bottom-layer logic chip, a top-layer DRAM chip, a second-layer DRAM chip, a vertical copper column interconnection region, a bottom-layer packaging body, a top-layer packaging body, a second-layer packaging body, a planar interconnection region, a signal longitudinal transmission path, a C4 bump array and a micro bump array, the bottom-layer packaging body packages the bottom-layer logic chip, the vertical copper cylinder and the planar metal wire interconnection layer together in a plastic mode, and the top-layer packaging body and the second-layer packaging body are similar to the bottom-layer packaging body in function; according to the invention, the TSV is replaced by the off-chip copper cylinder manufactured by electroplating in the packaging stage, so that the longitudinal interconnection of the chip is realized, and the DRAM three-dimensional integration with lower cost and high reliability is further realized; and meanwhile, the design difficulty of a memory chip is reduced, the system storage capacity is improved, and the overall performance of the system is improved.

A chip test system and method are provided. The chip test system includes a memory chip, a test device, and a test interface. The memory chip has a power pad and a driver pad coupled to the power pad. The test device is configured to provide a test signal. The test interface is configured to provide multiple signal transmission paths. The test device transmits the test signal to the power pad of the memory chip through the test interface, obtains a monitor voltage generated by the driver pad, and adjusts a test voltage value of the test signal according to the monitor voltage. The test device comprises a precise measurement unit configured to measure the monitor voltage, and a switch element coupled to the precise measurement unit, and when the memory chip starts to be tested, the switch element is turned on.

The invention provides a memory testing device, a three-dimensional stacked memory chip, a memory testing method and a memory testing system, a built-in self-test (BIST) testing process, a first configuration register, a second configuration register and a third configuration register are embedded in the memory testing device, so that only specified testing excitation needs to be applied to a testing host, and the testing efficiency is greatly improved. According to the method, the corresponding functional parameters of the three-dimensional stacked memory chip can be automatically tested, and switching of the functional parameters, the test direction and the test mode can be realized only by adjusting the configuration values in the first configuration register, the second configuration register and the third configuration register during testing, so that the test process of the functional parameters of the memory is optimized, and the test efficiency is improved. And the test time and the test cost are greatly saved.

The present disclosure provides an integrated circuit (IC) structure. The IC structure includes an optical interposer having optical waveguides; a plurality of chip stacks disposed over the optical interposer, each of the plurality of chip stacks including a first photonic IC chip and a memory chip over the first photonic IC chip; and a plurality of first laser source chips disposed adjacent to the plurality of chip stacks, respectively, wherein the optical waveguides in the optical interposer are configured as an optical interconnect structure to couple with the memory chip through the first photonic IC chip.

The invention relates to a memory, a control method thereof and electronic equipment, the memory comprises a memory chip and a logic chip, the memory chip and the logic chip are packaged by adopting a three-dimensional stacking process, the memory has a memory mode and a calculation mode, and the memory is configured as follows: in the memory mode, the logic chip is connected with the memory chip; realizing information interaction of the storage chip through a first information interaction path; and in the calculation mode, realizing information interaction of the storage chip through a second information interaction path. According to the application, two information interaction channels are set, and the first information interaction channel enables information interaction to be more efficient; the second information interaction path provides higher data bandwidth for the logic chip; therefore, the memory provided by the invention has the two advantages, one interaction path can be flexibly selected according to requirements, and the application scene of the memory is enriched.

The invention belongs to the technical field of chip design, and discloses a three-dimensional stacked heterogeneous in-memory computing system and a data interaction processing method thereof.The three-dimensional stacked heterogeneous in-memory computing system comprises a storage chip layer and an AI processing chip layer located below the storage chip layer, the storage chip layer is electrically connected with the AI processing chip layer, and the AI processing chip layer is electrically connected with the storage chip layer. The AI processing chip layer is of a heterogeneous storage and calculation integrated structure integrating an RRAM storage and calculation array and an SRAM storage and calculation array, and the RRAM storage and calculation array is used for storing system configuration data; and the SRAM memory array is used for writing read-write data of the memory chip layer and completing data processing in the array. According to the three-dimensional stacking heterogeneous storage and calculation integrated device, through heterogeneous cooperation of the RRAM and the SRAM storage and calculation integrated array, key problems existing in the prior art are fully balanced and considered, finally, the optimal design of a system architecture level is achieved, and core obstacles are cleared away for large-scale application of the three-dimensional stacking technology in the field of AI chips.

Techniques for an on-memory die voltage regulator is disclosed. In the illustrative embodiment, a voltage regulator on a memory die is enabled upon receipt of a memory operation. The illustrative voltage regulator includes an analog controller that controls a shunt current based on a current output voltage of the voltage regulator. The illustrative voltage regulator also includes a digital controller that controls several switches based on the input voltage that control an effective resistance of part of the voltage regulator.

A mixture-of-experts artificial intelligence model according to the present invention comprises: a CXL control unit that manages a CXL protocol; an NDP control unit that includes a memory mapping register set for communicating with a host; a memory unit composed of a plurality of memory chips that provide a memory capacity to the host; and an NDP core unit that processes MoEs existing in the memory unit, wherein the NDP core unit transmits only hot experts to a GPU accelerator while memory-based calculation is performed on cold experts that exist in the memory unit.

A memory media includes a first memory chip stacked over a substrate, a second memory chip stacked over the first memory chip, and a third memory chip stacked over the second memory chip. The first memory chip, the second memory chip, and the third memory chip are stacked in a staircase. Each of the first memory chip, the second memory chip, and the third memory chip includes outer chip pads disposed to form an outer row which is adjacent to a first edge; and inner chip pads disposed to form an inner row which is spaced apart from the first edge. The third memory chip is stacked over the second memory chip to expose the outer chip pads of the second memory chip and to cover the inner chip pads of the second memory chip.

A system includes a controller and a first memory chip associated with a first unique number and including a first set of pads coupled to the controller. The first memory chip is configured to receive a command from the controller through at least one pad of the first set of pads, the command including a target unique number and a target chip address, and the target chip address having a fewer number of bits than a number of bits of the target unique number, and to store the target chip address as a first chip address identifying the first memory chip, in response to the target unique number matching the first unique number.

Disclosed embodiments include a computational memory system. The computational memory system includes at least one computational memory chip including one or more processor subunits and one or more memory banks, formed on a common substrate. The computational memory system also includes at least one local error correction code (ECC) module configured for calculating an original ECC based on received data, at least one local ECC module associated with at least one of the processor subunits and / or at least one of the memory banks.

The invention provides a memory chip, a logic chip, a chip stacking structure and a memory. The memory chip comprises m channels, and the m channels are sequentially arranged in the first direction and are symmetrical about the axis of the chip; each channel is provided with a channel signal region, each channel signal region is divided into 2 * 2 through hole regions which are distributed in an array, the areas of the m channel signal regions are the same, and the distribution positions of the conductive through hole groups in the m channel signal regions are the same.

Provided are a memory chip, a logic chip, a chip stack structure, and a memory. In the memory chip, four first transmission structures are arranged symmetrically about a first axis and a second axis; four second transmission structures in each second transmission structure group are arranged symmetrically about the first axis and the second axis; the memory chip receives one first identification signal from each one of the first transmission structures and generates a chip position identification code based on four first identification signals; the memory chip receives one second identification signal from each second transmission structure group and generates a stack position identification code based on B second identification signals.

The invention discloses a system and a method for testing and analyzing the single event effect of a high-capacity nonvolatile memory. The system comprises an upper computer module, an FPGA (Field Programmable Gate Array) control module and a programmable power supply module. The system is used for testing and analyzing various single event effects of a high-capacity nonvolatile memory chip in a dynamic working mode. And according to the error data read from the memory in the dynamic working mode, presetting error bitmap rules of various single-particle function interruptions in an FPGA test program, carrying out real-time analysis and identification on the various single-particle function interruptions, and discriminating single-particle upset of the memory unit. According to the system, testing and real-time analysis of various complex single event effects of the high-capacity nonvolatile memory can be achieved, then radiation hardening and evaluation can be conducted on the sensitive position of a memory chip, and high pertinence is achieved.