1824 results about "Memory chip" patented technology

The invention relates to the technical field of microelectronic packaging, and discloses a packaging method of a multi-layer stacked memory chip, which comprises the following steps: constructing a 3D packaging structure layout of a memory chip to be packaged; constructing a physical field of the 3D packaging structure layout, and integrating the physical field and the field action relationship into the 3D packaging structure layout to obtain a coupled 3D packaging structure layout; calculating a hot spot, a high stress area and a high electric field area of the coupled 3D packaging structure layout, and optimizing the coupled 3D packaging structure layout to obtain a target packaging structure layout; performing multi-layer stacking on the to-be-packaged storage chip to obtain a multi-layer stacked storage chip; and packaging the multi-layer stacked memory chip to obtain a packaged multi-layer stacked memory chip, activating packaging repair of the self-repair material by using a preset material repair algorithm to obtain a packaging repair material, and performing multi-layer stacked packaging of the to-be-packaged memory chip based on the packaging repair material. According to the invention, the packaging stability of the multi-layer stacked storage chip can be improved.

The invention relates to a high-density memory chip packaging structure design method, device and equipment. The method comprises the steps of performing three-dimensional modeling on a multi-chip stacking structure of a high-density storage chip based on a current packaging structure parameter combination to obtain a packaging structure model; performing finite element analysis to obtain stress distribution data and a stress-strain curve; performing feature extraction and feature fusion to obtain a fused feature vector; training based on a multilayer feedforward neural network to obtain a structure optimization model; performing dependency analysis, constructing a parameter tree structure, and distributing corresponding priority values; and sorting and optimizing the plurality of packaging structure parameters one by one by utilizing a parameter tree structure and the priority values, and processing constraint conditions by adopting a self-adaptive penalty function method to obtain a target packaging structure parameter combination. According to the implementation of the invention, the design efficiency and performance of the high-density memory chip packaging structure are improved.

Systems, methods, and apparatus related to memory devices that perform matrix vector multiplication using memory cells. In one approach, a memory cell array has memory cells used to perform matrix vector multiplication based on summing output currents from the memory cells. A context of memory cells is determined by a controller (e.g., a memory controller internal or external to a memory chip having the array). The context can include, for example, a physical location of memory cells, weight patterns being programmed, and / or neighboring cell interference, etc. Based on the determined context, the controller dynamically determines adjustments (e.g., adjusted target threshold voltages or currents) for programming the memory cells to store weights prior to performing the matrix vector multiplication.

A multi-chip package comprising an interconnection substrate; a first semiconductor IC chip over the interconnection substrate, wherein the first semiconductor IC chip comprises a first silicon substrate, a plurality of first metal vias passing through the first silicon substrate, a plurality of first transistors on a top surface of the first silicon substrate and a first interconnection scheme over the first silicon substrate, wherein the first interconnection scheme comprises a first interconnection metal layer over the first silicon substrate, a second interconnection metal layer over the first interconnection layer and the first silicon substrate and a first insulating dielectric layer over the first silicon substrate and between the first and second interconnection metal layers; a second semiconductor IC chip over and bonded to the first semiconductor IC chip; and a plurality of second metal vias over and coupling to the interconnection substrate, wherein the plurality of second metal vias are in a space extending from a sidewall of the first semiconductor IC chip.

The invention relates to the technical field of electronic information, and discloses a high-reliability storage chip packaging test method and system.The method comprises the steps that firstly, a to-be-tested storage chip and original parameter information of the to-be-tested storage chip are obtained, packaging structure data are collected to construct a three-dimensional model, chip feature data are extracted, then the chip feature data are compared with standard reference data, and potential defect information is mined; suspicious packaging parts are screened, the sensitivity of the suspicious packaging parts to environmental parameters is monitored, then fault risk types are evaluated, weak links are positioned, performance is detected, specific problem points are found out, then a test planning target is formulated, test means and standards are clarified, a test operation instruction is generated, finally, packaging testing is executed, electrical performance data are collected, and stability is verified. And generating a packaging test report. The stability of the memory chip can be improved.

The invention relates to the technical field of chip packaging, and discloses an ultrathin multi-layer storage chip stacking packaging method, which comprises the following steps of: obtaining a storage chip to be packaged, performing chip quality division on the storage chip to be packaged to obtain a target chip, and performing fine classification on the target chip to obtain a plurality of groups of chips; performing thickness optimization on the multiple groups of divided chips to obtain thickness-optimized chips, and performing chip selection on the thickness-optimized chips to obtain selected chips; performing material coating on the selected chip to obtain a coated chip, performing chip curing on the coated chip to obtain a cured chip, and performing chip stacking on the cured chip to obtain a stacked chip; carrying out three-dimensional modeling on the stacked chips so as to carry out dispensing path planning on the stacked chips to obtain a dispensing path, and carrying out chip reinforcement on the stacked chips to obtain reinforced chips; and performing internal interconnection, preliminary packaging and shell injection molding on the reinforced chip to obtain a packaged chip. According to the invention, the packaging quality of the ultrathin multi-layer memory chip can be improved.

The invention discloses an edge end large language model inference system. The system comprises a main computing chip, an LPDDR interconnection resource and a vertically stacked and packaged storage chip stack, the storage chip stack comprises an NAND flash memory chip and a DRAM (Dynamic Random Access Memory) chip, and the NAND flash memory chip and the DRAM chip are paired and share an LPDDR interconnection resource; the NAND flash memory chip comprises a flash memory chip bare chip and a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) chip bare chip which are three-dimensionally interconnected based on hybrid bonding; a flash memory array is arranged on the flash memory chip bare chip; a logic block is arranged on the CMOS chip bare chip; the main calculation chip reads a parameter matrix of a model full connection layer from the NAND flash memory chip and reads other parameters from the DRAM chip for calculation in a pre-filling stage of large language model reasoning; and the NAND flash memory chip performs full connection layer calculation in a decoding stage. The system provided by the invention can improve the external transmission and internal reading bandwidth.

The present application discloses a compute-in-memory chip, an instruction scheduling method, and a related apparatus. The compute-in-memory chip comprises an instruction memory, an instruction scheduler, and at least one compute-in-memory memory; each compute-in-memory memory comprises at least one storage array; the instruction memory is used for acquiring a first tensor instruction to be executed; and the instruction scheduler is used for scheduling, on the basis of the association relationship between the first tensor instruction and a second tensor instruction and the state of a target storage array needing to be operated for executing the first tensor instruction, the first tensor instruction to the compute-in-memory memory to which the target storage array belongs so that the compute-in-memory memory executes the first tensor instruction. According to embodiments of the present application, diversified compute-in-memory computing can be supported, efficient out-of-order execution scheduling of a tensor instruction set is achieved on the basis of the compute-in-memory chip, and the requirements of compute-in-memory technology for high concurrency and high throughput rate are met.

The invention provides a solid state disk channel signal adjusting system and a solid state disk, the system further comprises a main control chip, a memory chip, a real-time monitoring module and a time sequence adjusting module, the real-time monitoring module is used for monitoring a read operation error rate corresponding to a flash memory chip in real time, and when the read operation error rate is larger than a preset threshold value, the time sequence adjusting module is used for adjusting the time sequence of the flash memory chip; working environment parameters of the DQS signal and the DQ signal are obtained and transmitted to the main control chip; the main control chip is used for obtaining a time sequence adjusting signal of a DQS signal and a DQ signal corresponding to the flash memory chip according to the working environment parameters and transmitting the time sequence adjusting signal to the time sequence adjusting module; wherein the time sequence adjusting signal is used for realizing alignment of a DQS signal and a DQ signal corresponding to the flash memory chip; and the time sequence adjusting module adjusts the time sequence of the DQS signal and the DQ signal corresponding to the flash memory chip according to the time sequence adjusting signal. According to the solid state disk channel signal adjusting system and the solid state disk, self-adaptive optimization adjustment of the solid state disk channel signals is achieved, the solid state disk channel signal adjusting system and the solid state disk can adapt to complex and changeable working environments, and the reading performance and the data transmission rate of the solid state disk are remarkably improved.

A buffer chip includes a chip select signal reception circuit for receiving one or more system chip select signals transmitted from a memory controller and a chip ID reception circuit for receiving chip ID information transmitted from the memory controller. The buffer chip also includes a chip select signal generation circuit that generates memory chip select signals by using the one or more system chip select signals and the chip ID information and a chip select signal transmission circuit that transmits the memory chip select signals to a plurality of memory chips.

To reduce Icc spikes during the operation of a non-volatile memory device, a distributed temperature sensing system individually monitors each plane of a memory die during memory operations. Icc levels during a memory operation are temperature dependent. By monitoring the temperature of the individual memory planes during an operation, the bias levels for performing the operation can be changed during the course of that operation in order to reduce Icc spikes during the operation. For example, during a write operation if the temperature increase of a plane exceeds a threshold during earlier programming loops, the bias conditions, such as word line or bit line bias voltages, can be altered for later programming loops of the write operation.

A semiconductor module includes a plurality of memory chips in a memory cube are stacked along a first direction parallel to a plane formed by a second direction and a third direction perpendicular to the first direction. The memory cube includes first and third outermost surfaces in the third direction and second and fourth outermost surfaces in the second direction. Each of the memory chips includes a substrate and a wiring layer. The substrate includes first to fourth side surfaces along each of the first to fourth outermost surfaces. A first insulating film is included between the first to fourth outermost surfaces and the corresponding first to fourth side surfaces. Internal wirings included in the wiring layer are connected to electrodes provided on at least one of the second to fourth outermost surfaces. The memory cube is spaced apart from the semiconductor chips and performs signal transmission.

The invention provides a storage and calculation integrated calculation module based on an OAM (Operation Administration and Maintenance) form, which is used for integrating a plurality of storage and calculation integrated chips of different types and realizing communication between a CPU (Central Processing Unit) and the storage and calculation integrated chips, and is characterized in that an external interface of the calculation module is connected with an external UBB (Universal Business Business) bottom plate by adopting an interface designed by an OAM protocol; the calculation module comprises a power supply interlayer card, a controller card and a memory operator card which are sequentially connected in a stacked mode, and the power supply interlayer card is configured in the mode that a power supply interface designed through an OAM protocol is used for conducting power supply conversion, supplying power to the controller card and the memory operator card and providing a path for data signal transmission between the controller card and a CPU on an external UBB bottom plate; the controller card is configured to perform conversion among different protocols, and communication and data signal transmission between the operator card and a CPU (Central Processing Unit) on the external UBB bottom plate; the storage operator card is configured to store a data signal and provide a chip connection interface for one or more storage and calculation integrated chips; and a data signal is transmitted to the storage and calculation integrated chip connected with the chip connecting interface through the chip connecting interface.

The invention relates to the technical field of display screen detection, and discloses a display screen split screen detection system which comprises a graphics processor, a synchronous step-down converter, a debugging serial port connected with the graphics processor, a liquid crystal screen chip, a first USB interface, a second USB interface, an EDP connector, a memory card, a wireless connection module, a volume adjustment key, a first memory chip, a second memory chip and a third USB interface. The liquid crystal screen chip is connected with a display screen; by using a split screen detection technology, a large-size LCD is partitioned and independently displayed for automatic testing, so that the production testing efficiency of a factory is improved, defective products can be found in time, and the problems that the price of a large screen is relatively high, and more additional overall cost can be increased by building testing equipment and environment are solved; in addition, compared with the traditional test application, the test system has high integration level, and the problems of hidden dark spots, bright spots, dead pixels, uneven color display and the like can be found more easily.

The invention relates to the technical field of chip packaging, and discloses a method and system for packaging a storage chip based on lead bonding, and the method comprises the steps: carrying out the front-end processing of the storage chip, and obtaining a target storage chip; evaluating expected application performance corresponding to the target memory chip, calculating a bonding adaptation coefficient between the target memory chip and the lead bonding material, and screening out a corresponding optimal bonding material from the lead bonding material; collecting a chip initial image corresponding to the target storage chip, identifying a lead bonding original point, a lead bonding end point and a middle welding point in the chip welding points, and calculating the welding point circularity corresponding to the middle welding point; determining optimal welding spots from the middle welding spots, planning a lead bonding path corresponding to the target storage chip, and analyzing a physical representation attribute corresponding to each welding spot in the optimal welding spots; and performing bonding packaging processing on the target storage chip to obtain a packaged storage chip. The invention mainly aims to solve the problem that the packaging quality of the storage chip is reduced.

The embodiment of the invention discloses a memory module, electronic equipment and a signal transmission method. The memory module is a dual-in-line memory module, a fool-proof bayonet and a locking bayonet are arranged on a circuit board of the memory module, and a plurality of memory chips are respectively arranged on two side board surfaces of the circuit board; wherein the plurality of memory chips are connected with the processing chip through a parallel bus, and the processing chip is connected with the golden finger interface through a serial bus. Through the arrangement, the memory module can realize a serial interconnection relation through the connector, the data transmission rate can be reliably improved, crosstalk and synchronous switch noise generated by high-speed transmission based on a parallel bus are avoided, and the SI is effectively improved; the actual occupied area is small, and high-density layout is facilitated. On the whole, technical guarantee is provided for high-density layout and high-performance operation of the architecture. In addition, the physical space occupied by the memory module is roughly the same as that occupied by a traditional memory bank, and structural standardization design of a mainboard is facilitated.

A system in package platform includes a processor chip having a runtime processor core, an accelerator core and a processor-memory interface exposed on a chip-to-chip bonding surface, a first memory chip such as 3D NAND flash memory storing a collection of executable models of inference engines, and a second memory chip storing weights of a selected executable model. The second memory chip can comprise a nonvolatile, random access memory, such as phase change memory. Direct vertical connections such as via-to-via connections, are provided between the processor chip and the second memory chip.

The embodiment of the invention provides a memory chip, a logic chip, a chip stacking structure and a memory, a global signal area of the memory chip is penetrated by a plurality of conductive through hole groups, each conductive through hole group comprises a first redundant conductive through hole group and a second redundant conductive through hole group, the first redundant conductive through hole group comprises a first conductive through hole and a fourth conductive through hole, and the second redundant conductive through hole group comprises a second conductive through hole and a third conductive through hole; the first redundant conductive through hole group is used for transmitting the same first global signal, and the second redundant conductive through hole group is used for transmitting the same second global signal.

The invention provides a multi-chip stacked packaging structure and a manufacturing method thereof, a plurality of packaging units are sequentially stacked on a substrate along the longitudinal direction, and a plastic packaging layer II wraps all the packaging units; each packaging unit comprises a plastic packaging layer I, a memory chip and an interposer chip, the memory chip and the interposer chip are interconnected through a rewiring layer, and the packaging units are electrically connected through connecting bumps. According to the invention, the fan-out packaging technology and the TSV technology are combined, each packaging unit does not need to comprise a substrate, the light and thin packaging structure is realized, signals are vertically transmitted through the interposer chip, and TSV processing on the memory chip is not needed; according to the invention, the number of connection points of the memory chip is increased through the rewiring layer, so that interconnection between the packaging units is easier and faster to realize; moreover, the structure of the NCF is improved, the first film layer with small flowability plays a supporting role and reduces overflow of the adhesive film, and the second film layer with large flowability is melted preferentially, so that the connecting salient points are easier to pass through, and pseudo soldering is reduced.

Disclosed embodiments include a computational memory system. The computational memory system includes at least one computational memory chip including one or more processor subunits and one or more memory banks formed on a common substrate. The at least one computational memory chip is configured to store one or more portions of an embedding table in the one or more memory banks, the embedding table including one or more feature vectors. The one or more processor subunits are configured to receive a sparse vector indicator from a host external to the at least one computational memory chip and, based on the received sparse vector indicator and the one or more portions of the embedding table, generate one or more vector sums.

A non-volatile memory chip comprises a cell region that includes a first surface, a second surface opposite to the first surface, a first cell structure, and a second cell structure spaced apart from the first cell structure; a peripheral circuit region on the first surface of the cell region, and that includes a first peripheral circuit connected to the first cell structure, a second peripheral circuit connected to the second cell structure, and a connection circuit between the first and second peripheral circuits; a through via between the first and second cell structures and that extends from the second surface of the cell region to the connection circuit of the peripheral circuit region; a redistribution layer that covers the through via on the second surface of the cell region, is connected to the through via, and extends along the second surface; and a chip pad connected to the redistribution layer.

The invention discloses a memory chip access control method and device, a storage medium and electronic equipment. Comprising the steps that first delay time for responding to an activation command when a memory chip conducts data access is obtained, and the first delay time is used for representing the time interval between sending of the activation command to the memory chip and responding of the activation command by the memory chip; second delay time for responding to a target command except the activation command when the memory chip performs data access is obtained, and the second delay time is used for representing a time interval between sending of the target command to the memory chip and response of the memory chip to the target command; a first target timing parameter of the memory chip is adjusted based on the first delay time and the second delay time, and the first target timing parameter is used for determining the target time for accessing the memory chip. The technical problem that the data read-write efficiency of an operating system is low due to the fact that the time of the activation command is not adjusted when the line address is checked through the activation command in the prior art is solved.

Methods and apparatus are disclosed for implementing data augmentation within a storage controller of a data storage device based on machine learning data read from a non-volatile memory (NVM) array of a memory die. Some particular aspects relate to configuring the storage controller to generate augmented versions of training images for use in training a Deep Learning Accelerator of an image recognition system by rotating, translating, skewing, cropping, etc., a set of initial training images obtained from a host device and stored in the NVM array. Other aspects relate to controlling components of the memory die to generate noise-augmented images by, for example, storing and then reading training images from worn regions of the NVM array to inject noise into the images. Data augmentation based on data read from multiple memory dies is also described, such as image data spread across multiple NVM arrays or multiple memory dies.

Systems, methods, and apparatus related to memory devices using memory cell pre-compensation for matrix vector multiplication are described. In one method, a memory cell array has memory cells to perform matrix vector multiplication based on summing output currents from the memory cells. The context of the memory cells is determined by a controller (e.g., a memory controller inside or outside a memory chip having the array). The context may include, for example, physical locations of memory cells, programmed weight patterns, and / or neighboring cell interference, etc. Based on the determined context, the controller dynamically determines an adjustment (e.g., an adjusted target threshold voltage or current) for programming the memory cells to store weights prior to performing the matrix vector multiplication.

The invention provides a packaging processing method and system for a storage chip and a medium, and belongs to the technical field of semiconductor packaging. The method comprises the following steps: constructing an initial three-dimensional model of a packaging body, cleaning and detecting a bare chip, and correcting the model after laser cutting; electrical, thermal and stress performances are simulated and optimized, multiple chips are integrated by adopting an SiP technology, and three-dimensional wiring of a substrate is completed; and after three times of cleaning, a molding process is optimized through mold flow simulation, a system-level mainboard is connected by utilizing a BGA technology, and finally, a full-performance test is completed. Through multi-stage simulation and process collaborative optimization, the packaging density, reliability and manufacturing yield of the storage chip are improved, and the method is suitable for industrial production of high-density integrated storage devices.

The present disclosure provides a method, system, device, medium and program product for read-write control of a storage chip, the method comprising: generating a first check code corresponding to first data; writing the first data and the first check code to a target address of the storage chip; reading second data and the second check code from the target address; generating a third check code corresponding to the second data; and performing read-write control on the storage chip based on the second check code and the third check code. The present disclosure reads the second data and the second check code in the target address of the storage chip, generates a third check code according to the second data, and finally performs read-write control on the storage chip according to the second check code and the third check code, thereby realizing the function of self-checking and error correction of the storage chip, and ensuring the reliability of the data stored in the storage chip.

The present disclosure provides a logic chip, a memory chip, a chip stack structure, and a memory. The logic chip is provided with a plurality of channel signal regions, conductive vias in each one of the plurality of channel signal regions are divided into a plurality of repair unit groups, and each one of the plurality of repair unit groups includes four repair units, where a first repair unit and a second repair unit are arranged symmetrically about a first axis, a third repair unit and a fourth repair unit are arranged symmetrically about the first axis, and the first repair unit and the fourth repair unit are arranged symmetrically about a second axis.

The embodiment of the invention discloses an internal memory, a chip and related electronic equipment. A target computing unit of the internal memory comprises a plurality of groups of primary multipliers, a plurality of adder trees and a plurality of secondary multipliers, one group of first-level multipliers is connected with one second-level multiplier through one adder tree; the group of first-level multipliers comprises a plurality of pairs of first multipliers, and each adder tree comprises a first adder, a second adder and a third adder; each pair of first multipliers respectively receive data to perform multiplication operation, and respectively input output results into the first adder to perform addition operation; each second adder receives the output results of the plurality of first adders or the second adder at the upper level to carry out addition operation, and respectively inputs the output results to the second adder at the lower level or the third adder; and each third adder receives the output results of the plurality of second adders to carry out addition operation, and inputs the output results to the secondary multiplier to carry out multiplication operation. By implementing the embodiment of the invention, the memory computing capability can be improved.

The invention discloses a DRAM (Dynamic Random Access Memory) chip capable of preventing a running hammer attack, a test system and a test method, and relates to the technical field of chip security, the DRAM chip is internally provided with one or more DRAM DIE chips, the DRAM chip reads data into a line buffer according to a received access signal, and the DRAM chip comprises a storage chip, a memory chip, a data storage module and a data storage module, the maximum allowable access frequency value stored in each DRAM DIE chip and the corresponding control address are sent; the attack detection control chip forwards a received access signal sent by the outside to the DRAM DIE chip, and sends a refresh signal to refresh a victim row when detecting that the victim row exists in a certain DRAM DIE chip according to the victim detection mode, or sends a refresh signal to refresh the victim row when detecting that the victim row cannot be refreshed, or sends a refresh signal to refresh the victim row when detecting that the victim row cannot be refreshed. And controlling the frequency of an access signal sent to the chip according to the received highest allowable access frequency and the corresponding control address. Therefore, the access frequency is reduced by refreshing or aiming at different self-adaptations, so that the working efficiency of the chip is improved while the chip is prevented from being attacked by a hammer.

The invention belongs to the technical field of chip packaging, and particularly relates to a three-dimensional stacked DRAM (Dynamic Random Access Memory) packaging structure based on electro-coppering cylinders. The packaging structure specifically comprises a bottom-layer logic chip, a top-layer DRAM chip, a second-layer DRAM chip, a vertical copper column interconnection region, a bottom-layer packaging body, a top-layer packaging body, a second-layer packaging body, a planar interconnection region, a signal longitudinal transmission path, a C4 bump array and a micro bump array, the bottom-layer packaging body packages the bottom-layer logic chip, the vertical copper cylinder and the planar metal wire interconnection layer together in a plastic mode, and the top-layer packaging body and the second-layer packaging body are similar to the bottom-layer packaging body in function; according to the invention, the TSV is replaced by the off-chip copper cylinder manufactured by electroplating in the packaging stage, so that the longitudinal interconnection of the chip is realized, and the DRAM three-dimensional integration with lower cost and high reliability is further realized; and meanwhile, the design difficulty of a memory chip is reduced, the system storage capacity is improved, and the overall performance of the system is improved.