Semiconductor memory device

Abstract

Provided is a semiconductor memory device including a plurality of semiconductor chips stacked on each other and having a novel structure different from the prior art. The semiconductor storage device comprises memory chips 1-1 and 1-2 which are stacked with each other. The memory chips 1-1, 1-2 include circuit elements and wirings arranged in the same layout between the memory chips 1-1, 1-2. The memory chips (1-1, 1-2) each have a front surface and a back surface facing each other, and a plurality of first terminals disposed on the front surface. In each of the memory chips 1-1, 1-2, the plurality of first terminals are arranged in mirror symmetry with respect to a plane of symmetry orthogonal to the front surface and the back surface. The memory chips (1-1, 1-2) are stacked such that the surface of the memory chip (1-1) is in contact with the surface of the memory chip (1-2), and the plurality of first terminals of the memory chip (1-1) are connected to the plurality of first terminals of the memory chip (1-2).

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This disclosure claims priority from Japanese Patent Application No. 2025-030357, filed with the Japan Patent Office on February 27, 2025, and entitled “Semiconductor Memory Device,” the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor memory device. Background Art

[0003] In recent years, with the improvement in the performance of GPUs (Graphics Processing Units) and CPUs (Central Processing Units), the demand for large-capacity, high-performance semiconductor memory devices has become increasingly high. However, to meet power supply and / or thermal management constraints within the entire system, it is necessary to achieve low power consumption while maintaining high performance.

[0004] Conventional technology has proposed a semiconductor memory device that uses three-dimensional stacking of semiconductor chips to address this problem. JEDEC (Joint Electron Device Engineering Council) has also standardized the HBM (High Bandwidth Memory) series, and products have already been released to the market.

[0005] For example, Japanese Patent Application Laid-Open No. 2011-166147 discloses a semiconductor memory device including a plurality of semiconductor chips stacked one above the other. Summary of the Invention

[0006] The semiconductor memory device disclosed in Patent Document 1 stacks multiple semiconductor chips by repeatedly connecting the front surface of one semiconductor chip to the back surface of another. This type of semiconductor chip connection is referred to as "F2B (face-to-back) connection" in this document.

[0007] To provide high-capacity, high-performance, and low-power 3D memory at a low price, it is necessary to have semiconductor memory devices of various types, not just F2B connections.

[0008] An object of the present disclosure is to provide a semiconductor memory device including a plurality of semiconductor chips stacked on each other and having a novel structure different from that of the prior art.

[0009] A semiconductor memory device according to one aspect of the present disclosure is a semiconductor memory device including a plurality of semiconductor chips stacked on each other. The plurality of semiconductor chips include circuit elements and wiring arranged in the same layout between the plurality of semiconductor chips, Each of the plurality of semiconductor chips has a first surface and a second surface facing each other, and a plurality of first terminals arranged on the first surface. In each of the plurality of semiconductor chips, the plurality of first terminals are arranged in mirror symmetry with respect to a symmetry plane orthogonal to the first surface and the second surface. The plurality of semiconductor chips include a first semiconductor chip and a second semiconductor chip, The first and second semiconductor chips are stacked such that the first surface of the first semiconductor chip is in contact with the first surface of the second semiconductor chip, and the first terminals of the first semiconductor chip are connected to the first terminals of the second semiconductor chip.

[0010] According to an aspect of the present disclosure, it is possible to provide a semiconductor memory device having a novel structure different from the existing F2B connection. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a plan view showing the terminal layout of the memory chips 1 - 1 and 1 - 2 of the semiconductor memory device according to the first embodiment.

[0012] Figure 2 This is a longitudinal cross-sectional view showing the structure of the semiconductor memory device according to the first embodiment.

[0013] Figure 3 1 is a plan view showing the terminal layout of memory chips 2 - 1 and 2 - 2 in the semiconductor memory device according to the first comparative example.

[0014] Figure 4 It is a longitudinal cross-sectional view showing the structure of a semiconductor memory device according to a first comparative example.

[0015] Figure 5 1 is a plan view showing the terminal layout of memory chips 3 - 1 and 3 - 2 in a semiconductor memory device according to a second comparative example.

[0016] Figure 6 is a longitudinal cross-sectional view showing the structure of a semiconductor memory device according to a second comparative example.

[0017] Figure 7 It is a longitudinal cross-sectional view showing another structure of the semiconductor memory device according to the first embodiment.

[0018] Figure 8 It is a plan view showing the terminal layout of memory chips 4 - 1 to 4 - 4 of the semiconductor memory device according to the second embodiment.

[0019] Figure 9 It shows Figure 8 A longitudinal cross-sectional view of the wiring layout of the memory chip 4-1.

[0020] Figure 10 It is a longitudinal cross-sectional view showing the structure of a semiconductor memory device according to the second embodiment.

[0021] Figure 11 This is a diagram showing multi-point connection of a semiconductor memory device.

[0022] Figure 12 A diagram showing spiral connections in a semiconductor memory device.

[0023] Figure 13 It shows Figure 10 A diagram of the manufacturing process of a semiconductor memory device.

[0024] Figure 14 It is a diagram showing a manufacturing process of a semiconductor memory device according to the third comparative example.

[0025] Figure 15 is a longitudinal sectional view showing the structure of a semiconductor memory device according to a third comparative example.

[0026] Figure 16 It is a plan view showing the terminal layout of memory chips 7 - 1 to 7 - 4 of a semiconductor memory device according to a modification of the second embodiment.

[0027] Reference numerals: 1-1 to 1-4, 4-1, 4-4, 7-1 to 7-4 memory chips; 10-1 to 10-4 semiconductor substrates; 10a-1 to 10a-4 surfaces of semiconductor substrates; 10b-1 to 10b-4 reverse surfaces of semiconductor substrates; 11-1 to 11-4 circuit elements; 21-1 to 28-4 surface terminals; 31-1 to 38-4 surface terminals; 41, 41-1 to 41-4 wiring layers; 42, 42-1 to 42-4 wiring through-holes; 43, 43-1 to 43-4 TSVs (through silicon vias). DETAILED DESCRIPTION

[0028] Hereinafter, a semiconductor memory device according to an embodiment of the present disclosure will be described with reference to the accompanying drawings. In each of the drawings, the same reference numerals denote the same components.

[0029] [First embodiment] Figure 1It is a plan view showing the terminal layout of the memory chips 1 - 1 and 1 - 2 of the semiconductor memory device according to the first embodiment. Figure 2 This is a longitudinal cross-sectional view showing the structure of the semiconductor memory device according to the first embodiment. Figure 1 and Figure 2 The semiconductor memory device includes memory chips 1-1 and 1-2 stacked on each other.

[0030] exist Figure 1 and Figure 2 In the figure, Xa, Ya, and Za represent the local coordinate system of memory chip 1-1, and Xb, Yb, and Zb represent the local coordinate system of memory chip 1-2. Furthermore, X, (Y,) Z represent the global coordinate system of the semiconductor memory device. The other figures also refer to the local and global coordinate systems.

[0031] Memory chips 1-1 and 1-2 are examples of semiconductor chips that include memory circuit elements formed on a semiconductor substrate. Memory chips 1-1 and 1-2 generally have the same structure. At least memory chips 1-1 and 1-2 include circuit elements and wiring arranged in the same layout between memory chips 1-1 and 1-2.

[0032] Please refer to Figure 1 Memory chip 1-1 has a semiconductor substrate with a front surface 10a-1 and a back surface 10b-1 facing each other. Furthermore, memory chip 1-1 has terminals 21-1 to 28-1 arranged on front surface 10a-1, and terminals 31-1 to 38-1 arranged on back surface 10b-1. Terminals 21-1 to 28-1 are arranged in mirror-image symmetry with respect to a symmetry plane perpendicular to front surface 10a-1 and back surface 10b-1. Similarly, terminals 31-1 to 38-1 are arranged in mirror-image symmetry with respect to the same symmetry plane.

[0033] Similarly, memory chip 1-2 has a semiconductor substrate with a front surface 10a-2 and a back surface 10b-2 facing each other. Memory chip 1-2 has terminals 21-2 to 28-2 arranged on front surface 10a-2, and terminals 31-2 to 38-2 arranged on back surface 10b-2. Terminals 21-2 to 28-2 are arranged in mirror-image symmetry about a plane of symmetry perpendicular to front surface 10a-2 and back surface 10b-2. Similarly, terminals 31-2 to 38-2 are arranged in mirror-image symmetry about the same plane of symmetry.

[0034] Herein, the surface of a semiconductor substrate is also referred to as the "first surface," and the reverse surface is also referred to as the "second surface." Furthermore, herein, a terminal disposed on the surface of a semiconductor substrate is also referred to as the "first terminal," and a terminal disposed on the reverse surface of the semiconductor substrate is also referred to as the "second terminal."

[0035] Memory chip 1-1 includes circuit elements 11-1 to 14-1 formed on an internal layer of a semiconductor substrate. Circuit elements 11-1 to 14-1 are associated with predetermined functions of the semiconductor memory device and include, for example, storage elements, input / output circuits, address (e.g., row address) decoders, command decoders, and power supplies. Circuit element 11-1 is connected to terminals 21-1, 22-1, 31-1, and 32-1. Circuit element 12-1 is connected to terminals 23-1, 24-1, 33-1, and 34-1. Circuit element 13-1 is connected to terminals 25-1, 26-1, 35-1, and 36-1. Circuit element 14-1 is connected to terminals 27-1, 28-1, 37-1, and 38-1.

[0036] Similarly, memory chip 1-2 includes circuit elements 11-2 through 14-2 formed on an inner layer of the semiconductor substrate. Circuit elements 11-2 through 14-2 are associated with the predetermined functions of the semiconductor memory device. Circuit element 11-2 is connected to terminals 21-2, 22-2, 31-2, and 32-2. Circuit element 12-2 is connected to terminals 23-2, 24-2, 33-2, and 34-2. Circuit element 13-2 is connected to terminals 25-2, 26-2, 35-2, and 36-2. Circuit element 14-2 is connected to terminals 27-2, 28-2, 37-2, and 38-2.

[0037] like Figure 2 As shown, the memory chips 1-1 and 1-2 are stacked in such a way that the surface 10a-2 of the memory chip 1-2 is in contact with the surface 10a-1 of the memory chip 1-1. As a result, the terminals 21-2 to 28-2 of the memory chip 1-2 are connected to the terminals 21-1 to 28-1 of the memory chip 1-1. Hereinafter, this connection of the memory chips will be referred to as "F2F (face to face) connection". When the memory chips 1-1 and 1-2 are stacked in this way, Figure 1 In the diagram, each pair of terminals assigned the same reference numerals A to H is connected to one another. Terminal 21-1 of memory chip 1-1 is connected to terminal 24-2 of memory chip 1-2 (reference numeral A), and terminal 22-1 of memory chip 1-1 is connected to terminal 23-2 of memory chip 1-2 (reference numeral B). The other terminals are connected in the same manner. Terminal 28-1 of memory chip 1-1 is connected to terminal 25-2 of memory chip 1-2 (reference numeral H).

[0038] exist Figure 1 In the figures, the thick dotted line indicates that two memory chips are stacked in such a manner that the front surfaces or the back surfaces thereof are in contact with each other.

[0039] The memory chip 1-1 has wiring formed on an internal layer of the semiconductor substrate 10-1, and the wiring includes a wiring layer 41-1, a wiring through-hole 42-1, and a TSV (through silicon via) 43-1. The terminal 21-1 is connected to the circuit element 11-1 of the memory chip 1-1 via the wiring layer 41-1, the wiring through-hole 42-1, and the TSV43-1. Similarly, the memory chip 1-2 has wiring formed on an internal layer of the semiconductor substrate 10-2, and the wiring includes a wiring layer 41-2, a wiring through-hole 42-2, and a TSV43-2. ​​The terminal 24-2 is connected to the circuit element 12-2 of the memory chip 1-2 via the wiring layer 41-2, the wiring through-hole 42-2, and the TSV43-2. ​​By connecting the terminals 21-1 and 24-2 to each other, the wiring and circuit elements of different memory chips 1-1 and 1-2 are connected to each other. In order to simplify the drawings, Figure 2 Only portions related to the terminals 21 - 1 and 24 - 2 are shown, and the remaining terminals are similarly connected to the wiring and circuit elements of the memory chips 1 - 1 and 1 - 2.

[0040] Please refer to Figure 1 , among the terminals 21-1 to 28-1 of memory chip 1-1, each pair of terminals arranged in mirror-image symmetry about the symmetry plane is connected to wiring associated with the same function. Similarly, among the terminals 21-2 to 28-2 of memory chip 1-2, each pair of terminals arranged in mirror-image symmetry about the symmetry plane is connected to wiring associated with the same function. The wiring includes data signal lines, address signal lines, command signal lines, power supply lines, and the like.

[0041] For example, assume that circuit elements 11-1 to 14-1 of memory chip 1-1 and circuit elements 11-2 to 14-2 of memory chip 1-2 form a memory array. In this case, terminals 21-1 and 22-1 of memory chip 1-1 are connected to address signal line RA0 and data signal line DQ0 of circuit element 11-1, respectively. Furthermore, terminals 23-1 and 24-1 of memory chip 1-1 are connected to data signal line DQ0 and address signal line RA0 of circuit element 12-1, respectively. Furthermore, terminals 25-1 and 26-1 of memory chip 1-1 are connected to address signal line RA0 and data signal line DQ0 of circuit element 13-1, respectively. Furthermore, terminals 27-1 and 28-1 of memory chip 1-1 are connected to data signal line DQ0 and address signal line RA0 of circuit element 14-1, respectively. Similarly, the terminals 21-2 to 28-2 of the memory chip 1-2 are also connected to the address signal lines and data signal lines of the circuit elements 11-2 to 14-2.

[0042] When memory chips 1-1 and 1-2 are stacked using F2F connections, as previously described, terminal 21-1 of memory chip 1-1 is connected to terminal 24-2 of memory chip 1-2. At this point, both terminals 21-1 and 24-2 are connected to address signal line RA0 of the memory array. Therefore, addresses are transmitted normally via terminals 21-1 and 24-2 and the wiring connecting them. Similarly, addresses and data are transmitted normally via each other pair of terminals connected to each other on memory chips 1-1 and 1-2 and the wiring connecting them.

[0043] Thus, in each of the memory chips 1-1 and 1-2, the terminals connected to the wiring associated with the same function are arranged in a mirror-symmetrical manner with respect to the symmetry plane. Figure 1 Each pair of terminals assigned the same reference numerals A to H in FIG is connected to a wiring associated with the same function.

[0044] The terminals of the memory chips 1-1 and 1-2 are arranged in mirror symmetry with respect to the symmetry plane, but other components of the memory chips 1-1 and 1-2, such as circuit elements and wiring, may not be arranged in mirror symmetry.

[0045] Memory chips 1-1 and 1-2 include circuit elements and wiring arranged in the same layout between memory chips 1-1 and 1-2. Therefore, memory chips 1-1 and 1-2 can be manufactured using substantially the same mask set. "Substantially the same mask set" means that all or part of the mask set used to form each layer of the memory chip is identical. Even if the mask is partially different for all or part of a layer not related to the features of this embodiment, that mask is included in the "substantially the same mask set."

[0046] Here, reference Figures 3 to 6 , a semiconductor storage device according to a comparative example is described.

[0047] Figure 3 1 is a plan view showing the terminal layout of memory chips 2 - 1 and 2 - 2 in the semiconductor memory device according to the first comparative example. Figure 4 It is a longitudinal cross-sectional view showing the structure of a semiconductor memory device according to a first comparative example. Figure 3 and Figure 4 The semiconductor memory device includes memory chips 2-1 and 2-2 stacked on each other.

[0048] The memory chips 2 - 1 , 2 - 2 generally have the same structure as each other.

[0049] Please refer to Figure 3Memory chip 2-1 has a front surface 10a-1 and a back surface 10b-1. Furthermore, memory chip 2-1 has terminals 21-1 to 24-1 arranged on front surface 10a-1, and terminals 31-1 to 34-1 arranged on back surface 10b-1. In addition, memory chip 2-1 has circuit elements 11-1 and 12-1. Similarly, memory chip 2-2 has a front surface 10a-2 and a back surface 10b-2. Memory chip 2-2 has terminals 21-2 to 24-2 arranged on front surface 10a-2, and terminals 31-2 to 34-2 arranged on back surface 10b-2. In addition, memory chip 2-2 has circuit elements 11-2 and 12-2.

[0050] like Figure 4 As shown, the memory chips 2-1 and 2-2 are stacked by F2B connection in such a way that the back surface 10b-2 of the memory chip 2-2 is in contact with the front surface 10a-1 of the memory chip 2-1. As a result, the terminals 31-2 to 34-2 of the memory chip 2-2 are connected to the terminals 21-1 to 24-1 of the memory chip 2-1. When the memory chips 2-1 and 2-2 are stacked in this way, Figure 3 In the embodiment, each pair of terminals assigned the same reference numerals A to D are connected to each other.

[0051] according to Figure 3 and Figure 4 In a semiconductor storage device, by stacking memory chips 2-1 and 2-2 having the same structure using F2B connection, corresponding terminals of the memory chips 2-1 and 2-2 can be easily connected.

[0052] Figure 5 1 is a plan view showing the terminal layout of memory chips 3 - 1 and 3 - 2 in a semiconductor memory device according to a second comparative example. Figure 6 is a longitudinal cross-sectional view showing the structure of a semiconductor memory device according to a second comparative example. Figure 5 and Figure 6 The semiconductor memory device includes memory chips 3-1 and 3-2 stacked on each other.

[0053] Please refer to Figure 5 Memory chip 3-1 has a front surface 10a-1 and a back surface 10b-1. Furthermore, memory chip 3-1 has terminals 21-1 to 24-1 arranged on front surface 10a-1, and terminals 31-1 to 34-1 arranged on back surface 10b-1. Furthermore, memory chip 3-1 has circuit elements 11-1 and 12-1. Similarly, memory chip 3-2 has a front surface 10a-2 and a back surface 10b-2. Memory chip 3-2 has terminals 21-2 to 24-2 arranged on front surface 10a-2, and terminals 31-2 to 34-2 arranged on back surface 10b-2. Furthermore, memory chip 3-2 has circuit elements 11-2 and 12-2.

[0054] like Figure 6 As shown, the memory chips 3-1 and 3-2 are stacked by F2F connection in such a way that the surface 10a-2 of the memory chip 3-2 is in contact with the surface 10a-1 of the memory chip 3-1. As a result, the terminals 21-2 to 24-2 of the memory chip 3-2 are connected to the terminals 21-1 to 24-1 of the memory chip 3-1. When the memory chips 3-1 and 3-2 are stacked in this way, Figure 5 In the embodiment, each pair of terminals assigned the same reference numerals A to D are connected to each other.

[0055] according to Figure 5 and Figure 6 In a semiconductor memory device, stacking memory chips 3-1 and 3-2 using F2F connections to connect corresponding terminals of memory chips 2-1 and 2-2 requires memory chips 3-1 and 3-2 to have terminals arranged in different layouts. Consequently, two mask sets are required, each with at least different portions related to the terminals, increasing manufacturing costs.

[0056] On the other hand, according to Figure 1 and Figure 2 The semiconductor memory device according to the first embodiment shown in the figure is a semiconductor memory device that has a novel structure different from the conventional F2F connection and a conventional F2B connection by stacking memory chips 1-1 and 1-2 having terminals arranged in a mirror-symmetrical manner with respect to a symmetry plane. According to the semiconductor memory device according to the first embodiment, the memory chips 1-1 and 1-2 can be manufactured using substantially the same mask set, and thus, the memory chips 1-1 and 1-2 can be manufactured using substantially the same mask set. Figure 5 and Figure 6 Therefore, according to the semiconductor memory device involved in the first embodiment, a semiconductor memory device with large capacity, high performance and low power consumption can be provided at a low price.

[0057] Next, other connections of the terminals and wiring of the memory chip will be described.

[0058] In each of the memory chips 1-1 and 1-2, each pair of terminals arranged in a mirror-symmetrical configuration about the symmetry plane is not limited to being connected to wiring associated with the same function, but can also be connected to wiring associated with different functions. In this case, in each of the memory chips 1-1 and 1-2, the multiple terminals on the surface 10a-1 include a first terminal group and a second terminal group, and the first terminal group and the second terminal group are arranged in a mirror-symmetrical configuration about the symmetry plane. The first terminal group and the second terminal group are connected to multiple wirings associated with the same functional group. Here, "functional group" refers to multiple bits of address, command, or data, for example, and "multiple wirings associated with the same functional group" refers to multiple signal lines that transmit multiple bits of address, command, or data.

[0059] Please refer to Figure 1 The terminals 21-1 to 28-1 of the memory chip 1-1 include, for example, a first terminal group 21-1, 22-1 and a second terminal group 23-1, 24-1. The first terminal group 21-1, 22-1 and the second terminal group 23-1, 24-1 are arranged in a mirror-symmetrical manner with respect to the symmetry plane. At this time, the first terminal group 21-1, 22-1 can be connected to the address signal lines RA0, RA1 of the circuit element 11-1, respectively, and the second terminal group 23-1, 24-1 can be connected to the address signal lines RA0, RA1 of the circuit element 12-1, respectively. In other words, the first terminal group 21-1, 22-1 and the second terminal group 23-1, 24-1 are connected to multiple wirings associated with the same functional group. Although a pair of terminals 21-1, 24-1 arranged in a mirror-symmetrical manner with respect to the symmetry plane are included in the same functional group, they are respectively connected to wirings associated with different functions, namely, the address signal lines RA0, RA1. Likewise, a pair of terminals 22 - 1 and 23 - 1 arranged in mirror symmetry with respect to the symmetry plane are included in the same functional group but are connected to wirings associated with different functions, ie, address signal lines RA1 and RA0 , respectively.

[0060] Likewise, the terminals 21 - 2 to 28 - 2 of the memory chip 1 - 2 may include a first terminal group and a second terminal group that are arranged in mirror symmetry with respect to the symmetry plane and are connected to a plurality of wirings associated with the same functional group.

[0061] Each pair of terminals, arranged mirror-symmetrically about the plane of symmetry, is connected to a signal line that transmits a different bit of the address, while the first and second terminal groups are connected as a whole to multiple wiring lines associated with the same multiple bits of the address. The address is normally transmitted via the first and second terminal groups as a whole and the wiring lines connected thereto.

[0062] However, when testing a memory array, if the address, command, or data signals do not have a pattern that applies appropriate noise or stress to the memory array, defects in the memory array may not be detected. To account for this, a first terminal group and a second terminal group may be selected that are capable of applying appropriate noise or stress to the memory array during testing.

[0063] Next, another structure of the semiconductor memory device according to the first embodiment will be described.

[0064] Figure 7 It is a longitudinal cross-sectional view showing another structure of the semiconductor memory device according to the first embodiment. Figure 7 The semiconductor memory device includes memory chips 1-1 to 1-4 stacked on each other.

[0065] Figure 7 The structure of memory chips 1-1 to 1-2 is the same as Figure 1 and Figure 2 The memory chips 1-1 and 1-2 are the same.

[0066] The structure of memory chips 1-3 to 1-4 is similar to Figure 1 and Figure 2 Memory chips 1-1 and 1-2 are identical. Memory chips 1-3 and 1-4 are stacked with the surface of memory chip 1-4 touching the surface of memory chip 1-3, i.e., using F2F connection. Thus, the terminals on the surface of memory chip 1-4 are connected to the terminals on the surface of memory chip 1-3.

[0067] Memory chips 1-2 and 1-3 are stacked so that the back side of memory chip 1-3 touches the back side of memory chip 1-2. This connects the terminals on the back side of memory chip 1-3 to the terminals on the back side of memory chip 1-2. This type of memory chip connection is referred to as a "B2B (back-to-back) connection."

[0068] In each of memory chips 1-1 to 1-4, among the multiple terminals arranged on the back surface of the memory chip, each pair of terminals arranged in a mirror-image arrangement about a symmetry plane can be connected to wiring associated with the same function. Furthermore, in each of memory chips 1-1 to 1-4, the multiple terminals arranged on the back surface of the memory chip can include a third terminal group and a fourth terminal group, each of which is arranged in a mirror-image arrangement about the symmetry plane and is connected to multiple wiring associated with the same functional group. The third and fourth terminal groups can be selected to apply appropriate noise or stress to the memory array during memory array testing.

[0069] according to Figure 7In the semiconductor storage device, memory chips 1-1 to 1-4 are stacked alternately by F2F connection and B2B connection. Similarly, more than four memory chips may be stacked alternately by F2F connection and B2B connection.

[0070] [Second embodiment] In the second embodiment, a description will be given of reducing the load on the signal line to which the terminal of the memory chip is connected so as to increase the signal transmission speed.

[0071] Figure 8 It is a plan view showing the terminal layout of memory chips 4 - 1 to 4 - 4 of the semiconductor memory device according to the second embodiment.

[0072] The memory chips 4-1 to 4-4 generally have the same structure as one another. At least the memory chips 4-1 to 4-4 include circuit elements and wiring arranged in the same layout between the memory chips 4-1 to 4-4.

[0073] Memory chip 4-1 has a front surface 10a-1 and a back surface 10b-1. Furthermore, memory chip 4-1 has terminals 21-1 to 28-1 located on front surface 10a-1, and terminals 31-1 to 38-1 located on back surface 10b-1. Terminals 21-1 to 28-1 are arranged in mirror-image symmetry about a plane of symmetry perpendicular to front surface 10a-1 and back surface 10b-1. Similarly, terminals 31-1 to 38-1 are arranged in mirror-image symmetry about the same plane of symmetry.

[0074] Memory chip 4-2 has a front surface 10a-2 and a back surface 10b-2. Memory chip 4-2 has terminals 21-2 to 28-2 located on front surface 10a-2 and terminals 31-2 to 38-2 located on back surface 10b-2. Terminals 21-2 to 28-2 are arranged in mirror-image symmetry about a plane of symmetry perpendicular to front surface 10a-2 and back surface 10b-2. Similarly, terminals 31-2 to 38-2 are arranged in mirror-image symmetry about the same plane of symmetry.

[0075] The memory chip 4-3 has a front surface 10a-3 and a back surface 10b-3. Furthermore, the memory chip 4-3 has terminals 21-3 to 28-3 arranged on the front surface 10a-3, and terminals 31-3 to 38-3 arranged on the back surface 10b-3. The terminals 21-3 to 28-3 are arranged in mirror-image symmetry about a plane of symmetry perpendicular to the front surface 10a-3 and the back surface 10b-3. Similarly, the terminals 31-3 to 38-3 are arranged in mirror-image symmetry about the same plane of symmetry.

[0076] Memory chip 4-4 has a front surface 10a-4 and a back surface 10b-4. Furthermore, memory chip 4-4 has terminals 21-4 to 28-4 located on front surface 10a-4 and terminals 31-4 to 38-4 located on back surface 10b-4. Terminals 21-4 to 28-4 are arranged in mirror-image symmetry about a plane of symmetry perpendicular to front surface 10a-4 and back surface 10b-4. Similarly, terminals 31-4 to 38-4 are arranged in mirror-image symmetry about the same plane of symmetry.

[0077] The memory chip 4-1 includes circuit elements 11-1 and 12-1 formed on an inner layer of a semiconductor substrate. The circuit element 11-1 is connected to terminals 22-1 and 31-1. The circuit element 12-1 is connected to terminals 28-1 and 37-1.

[0078] The memory chip 4-2 includes circuit elements 11-2 and 12-2 formed on an inner layer of a semiconductor substrate. The circuit element 11-2 is connected to terminals 22-2 and 31-2. The circuit element 12-2 is connected to terminals 28-2 and 37-2.

[0079] The memory chip 4-3 includes circuit elements 11-3 and 12-3 formed on an inner layer of a semiconductor substrate. The circuit element 11-3 is connected to terminals 22-3 and 31-3. The circuit element 12-3 is connected to terminals 28-3 and 37-3.

[0080] The memory chip 4-4 includes circuit elements 11-4 and 12-4 formed on an inner layer of a semiconductor substrate. The circuit element 11-4 is connected to terminals 22-4 and 31-4. The circuit element 12-4 is connected to terminals 28-4 and 37-4.

[0081] Figure 9 It shows Figure 8 A longitudinal cross-sectional view of the wiring layout of the memory chip 4-1. The memory chip 4-1 has wiring formed on an internal layer of the semiconductor substrate 10-1, which includes a wiring layer 41, wiring vias 42, and TSVs 43. The terminals 21-1 to 28-1 on the surface 10a-1 are connected to the middle wiring layer 41 via the wiring vias 42. The middle wiring layer 41 is connected to the terminals 31-1 to 38-1 on the back surface 10b-1 via TSVs 43. The wiring vias 42 and TSVs 43 are connected to the wiring layer 41 at different positions that are offset in the horizontal direction.

[0082] The terminals 21-1 to 28-1 on the surface 10a-1 include a first terminal group 21-1 to 24-1 and a second terminal group 25-1 to 28-1, and the first terminal group and the second terminal group are arranged in a mirror-symmetrical manner with respect to the symmetry plane. The terminals 31-1 to 38-1 on the reverse surface 10b-1 include a third terminal group 31-1 to 34-1 and a fourth terminal group 35-1 to 38-1, and the third terminal group and the fourth terminal group are arranged in a mirror-symmetrical manner with respect to the symmetry plane. The first terminal group 21-1 to 24-1 and the third terminal group 31-1 to 34-1 are arranged on the same side of the symmetry plane ( Figure 9 The second terminal group 25-1 to 28-1 and the fourth terminal group 35-1 to 38-1 are also arranged on the same side of the symmetry plane ( Figure 9 on the right side of the ).

[0083] The first terminal group 21-1 to 24-1 and the third terminal group 31-1 to 34-1 are interconnected via a first wiring group. Specifically, terminals 21-1 to 24-1 are connected to terminals 34-1, 31-1, 32-1, and 33-1, respectively. Furthermore, the second terminal group 25-1 to 28-1 and the fourth terminal group 35-1 to 38-1 are interconnected via a second wiring group. Specifically, terminals 25-1 to 28-1 are connected to terminals 38-1, 35-1, 36-1, and 37-1, respectively.

[0084] The first wiring group and the second wiring group have an asymmetric layout relative to the symmetry plane. Figure 9 As shown, the second wiring group has a layout obtained by translating the first wiring group, that is, a layout that is translationally symmetrical to the first wiring group.

[0085] As previously described, circuit element 11-1 is connected to terminals 22-1 and 31-1, and circuit element 12-1 is connected to terminals 28-1 and 37-1. Therefore, only one wiring in the first wiring group, that is, the wiring that connects terminals 22-1 and 31-1, is connected to circuit element 11-1, while the remaining wiring in the first wiring group is not connected to any circuit element. Furthermore, only one wiring in the second wiring group, that is, the wiring that connects terminals 28-1 and 37-1, is connected to circuit element 12-1, while the remaining wiring in the second wiring group is not connected to any circuit element. In memory chip 4-1, wiring that is not connected to either circuit element 11-1 or 11-2 is connected to any circuit element 11-2 through 11-4 in other memory chips 4-2 through 4-3, as described later.

[0086] Figure 8 The structure of memory chips 4-2 to 4-4 is also the same as Figure 9 The memory chips are the same as 4-1.

[0087] Figure 10It is a longitudinal cross-sectional view showing the structure of a semiconductor memory device according to the second embodiment. Figure 10 Simplified illustration Figure 9 Wiring. Figure 10 The semiconductor memory device includes Figure 7 Similarly, the memory chips 4-1 to 4-4 are alternately stacked by F2F connection and B2B connection. When the memory chips 4-1 to 4-4 are stacked in this way, Figure 8 In FIG, terminals assigned the same reference numerals A to H are connected to each other directly or via wirings of the memory chips 4 - 1 to 4 - 4 .

[0088] Please refer to Figure 10 , the terminals assigned with reference numerals A and the wiring connecting them are only connected to circuit element 11-1, and no other circuit elements are connected. In addition, the terminals assigned with reference numerals B and the wiring connecting them are only connected to circuit element 11-2, and no other circuit elements are connected. In addition, the terminals assigned with reference numerals C and the wiring connecting them are only connected to circuit element 11-3, and no other circuit elements are connected. In addition, the terminals assigned with reference numerals D and the wiring connecting them are only connected to circuit element 11-4, and no other circuit elements are connected. Thus, Figure 10 The semiconductor memory device connects the circuit elements 11-1 to 11-4 and the wiring of the memory chips 4-1 to 4-4 in a spiral manner.

[0089] Figure 11 This is a diagram showing multi-point connection of a semiconductor memory device. Figure 11 The semiconductor memory device includes memory chips 5-1 to 5-4 stacked on top of each other. Reference numerals A to D represent signal lines spanning the plurality of memory chips 5-1 to 5-4, which include terminals of each memory chip 5-1 to 5-4 and wiring connecting the terminals to each other. Memory chip 5-1 has four circuit elements 11-1 to 14-1, and each of the other memory chips 5-2 to 5-3 also has four circuit elements. These circuit elements are, for example, transceiver circuits for signals transmitted via signal lines. Four circuit elements 11-1 to 11-4 are connected to signal line A, and four circuit elements are also connected to each of the other signal lines B to D. Figure 11 This diagram illustrates a "multi-drop connection" where multiple circuit elements, including multiple memory chips 5-1 to 5-4, are connected to each signal line. For example, when a semiconductor memory device controller (not shown) communicates with circuit element 11-1 via signal line A, circuit elements 11-2 to 11-4 connected to the same signal line A are inactive, ceasing signal transmission and reception. However, even when circuit elements 11-2 to 11-4 are inactive, they still act as loads for circuit element 11-1. Therefore, multi-drop connections are not suitable for high-speed signal transmission.

[0090] Figure 12 A diagram showing spiral connections in a semiconductor memory device. Figure 12 Equivalently shown Figure 10 The structure of the semiconductor memory device. Figure 12 As shown, signal line A is connected only to circuit element 11-1, with no other circuit elements connected. Furthermore, signal line B is connected only to circuit element 11-2, with no other circuit elements connected. Furthermore, signal line C is connected only to circuit element 11-3, with no other circuit elements connected. Furthermore, signal line D is connected only to circuit element 11-4, with no other circuit elements connected. Figure 12 This diagram shows a "spiral connection" where the connection points between signal lines and circuit elements shift as the memory chip moves. Circuit elements 11-1 through 11-4 can operate in parallel or simultaneously. Signal lines A through D are free of circuit elements that would create an additional load, making them suitable for high-speed signal transmission.

[0091] The memory chips 4-1 to 4-4 include circuit elements and wiring arranged in the same layout between the memory chips 4-1 to 4-4. Therefore, the memory chips 4-1 to 4-4 can be manufactured using substantially the same mask set.

[0092] Figure 13 It shows Figure 10 Figure 1 shows the manufacturing process of a semiconductor memory device. Figure 13 , the spiral connection is achieved by alternately stacking the memory chips 4-1 to 4-4 through F2F connection and B2B connection. As mentioned above, the memory chips 4-1 to 4-4 generally have the same structure as each other, so Figure 13 The memory chips 4-1 and 4-2 also have the same structure. The terminal groups of the memory chips 4-1 and 4-2 are arranged in mirror symmetry with respect to the symmetry plane, and the wiring groups of the memory chips 4-1 and 4-2 have a layout that is mutually translationally symmetric. Therefore, after being rotated 180 degrees, the memory chip 4-2 has basically the same structure as before the rotation. The memory chips 4-1 to 4-4 are alternately stacked by F2F connection and B2B connection, thereby obtaining Figure 10 The semiconductor storage device realizes spiral connection.

[0093] Figure 14 It is a diagram showing a manufacturing process of a semiconductor memory device according to the third comparative example. Figure 15 is a longitudinal sectional view showing the structure of a semiconductor memory device according to a third comparative example. Figure 14 and Figure 15The semiconductor storage device includes memory chips 6-1 to 6-4 stacked on top of each other. Each of the memory chips 6-1 to 6-4 has two wiring groups that are mirror-symmetrical with respect to the symmetry plane. At this time, the memory chip 6-2 ( Figure 14 The terminals 31-2 to 38-2 on the back side 10b-2 of the middle section of the memory chip 6-1 are connected to the terminals 31-1 to 38-1 on the back side 10b-2 of the memory chip 6-1 via wiring. Figure 15 As shown, even if the memory chips 6-1 to 6-4 are alternately stacked by F2F connection and B2B connection, a spiral connection cannot be achieved.

[0094] When the wiring connecting circuit elements 11-1 to 11-4 to the memory chips 4-1 to 4-4 is connected in a spiral pattern, the wiring included in the first wiring group and the second wiring group in each of the memory chips 4-1 to 4-4 can be associated with the same functional group. Furthermore, in each of the memory chips 4-1 to 4-4, the wiring included in the first wiring group can be associated with at least two functions, and the wiring included in the second wiring group can be associated with at least two functions.

[0095] For example, see Figure 10 On surfaces 10a-1 to 10a-4 of each memory chip 4-1 to 4-4, the odd-numbered terminals on the left side of the symmetry plane (e.g., terminals 21-1 and 23-1) and the even-numbered terminals on the right side of the symmetry plane (e.g., terminals 26-1 and 28-1) must have the same function. Similarly, the even-numbered terminals on the left side of the symmetry plane (e.g., terminals 22-1 and 24-1) must have the same function as the odd-numbered terminals on the right side of the symmetry plane (e.g., terminals 25-1 and 27-1). In other combinations, terminals for signals with different functions and / or power levels can be arranged in a mirror-image configuration. For example, assume that terminal 31-1 of memory chip 4-1 is connected to the address decoder, while its mirror-image terminal 38-1 is connected to the input / output circuit. In this case, terminal 28-2 of memory chip 4-2 is connected to a different signal line than terminal 31-1. Therefore, even though they are not associated with the same function, address and signal transmission can still proceed normally. Terminal 21-3 of memory chip 4-3 and terminal 21-1 of memory chip 4-1 have the same coordinates on the XY plane. Therefore, terminal 21-3 is connected to the address decoder. Similarly, terminal 28-4 of memory chip 4-4 is connected to a different signal line than terminal 31-1. Therefore, even though they are not associated with the same function, addresses and signals can be transmitted normally.

[0096] according to Figures 8 to 10The semiconductor memory device according to the second embodiment shown can alternately stack memory chips 4-1 to 4-4 having terminals arranged in a mirror-symmetrical configuration about a symmetry plane through F2F connections and B2B connections. Furthermore, according to the semiconductor memory device according to the second embodiment, by having a terminal group arranged in a mirror-symmetrical configuration about a symmetry plane and a translationally symmetrical wiring group, the memory chips 4-1 to 4-4 can be alternately stacked through F2F connections and B2B connections to achieve a spiral link. Thus, a semiconductor memory device can be provided that has both conventional F2B connections and a novel structure that differs from conventional F2F connections. According to the semiconductor memory device according to the second embodiment, the memory chips 4-1 to 4-4 can be manufactured using essentially the same mask group, thereby reducing manufacturing costs. Therefore, according to the semiconductor memory device according to the second embodiment, a semiconductor memory device with large capacity, high performance, and low power consumption can be provided at a low price.

[0097] The spiral connection means that as the memory chip moves, if the signal line and the circuit element connection point are logically offset, the wiring does not need to have a physical spiral shape.

[0098] Figure 16 This is a plan view showing the terminal layout of memory chips 7-1 to 7-4 of a semiconductor memory device according to a modified example of the second embodiment. The memory chips 7-1 to 7-4 generally have the same structure as each other. At least the memory chips 7-1 to 7-4 include circuit elements and wiring arranged in the same layout between the memory chips 7-1 to 7-4. The memory chips 7-1 to 7-4 have the same structure as the memory chips 7-1 to 7-4. Figure 8 Terminals can be configured in different layouts. Figure 16 The semiconductor memory device is also Figures 8 to 10 Similarly, the semiconductor memory device can realize spiral connection by alternately stacking memory chips 7-1 to 7-4 through F2F connection and B2B connection.

[0099] [Other Implementation Methods] The semiconductor memory device may include more than four memory chips.

[0100] The semiconductor memory device may have a terminal layout different from that described above.

[0101] When F2F connection and / or B2B connection is adopted, the layout of the terminals on the front surface of each memory chip may be different from the layout of the terminals on the back surface.

[0102] [Summary of Implementation Methods] A semiconductor memory device according to a first aspect of the present disclosure is a semiconductor memory device including a plurality of semiconductor chips stacked on top of each other. The plurality of semiconductor chips include circuit elements and wiring arranged in the same layout between the plurality of semiconductor chips, Each of the plurality of semiconductor chips has a first surface and a second surface facing each other, and a plurality of first terminals arranged on the first surface. In each of the plurality of semiconductor chips, the plurality of first terminals are arranged in mirror symmetry with respect to a symmetry plane orthogonal to the first surface and the second surface. The plurality of semiconductor chips include a first semiconductor chip and a second semiconductor chip, The first and second semiconductor chips are stacked such that the first surface of the first semiconductor chip is in contact with the first surface of the second semiconductor chip, and the first terminals of the first semiconductor chip are connected to the first terminals of the second semiconductor chip.

[0103] According to the semiconductor memory device according to the second aspect of the present disclosure, in the semiconductor memory device according to the first aspect, In each of the plurality of semiconductor chips, each pair of first terminals arranged in mirror-symmetry with respect to the symmetry plane is connected to wiring associated with the same function.

[0104] According to the semiconductor memory device according to the third aspect of the present disclosure, in the semiconductor memory device according to the first aspect, In each of the multiple semiconductor chips, the multiple first terminals include a first terminal group and a second terminal group, the first terminal group and the second terminal group are arranged in mirror symmetry with respect to the symmetry plane, and the first terminal group and the second terminal group are connected to multiple wirings associated with the same functional group.

[0105] According to a fourth aspect of the present disclosure, in the semiconductor memory device according to one of the first to third aspects, Each of the plurality of semiconductor chips further includes a plurality of second terminals arranged on the second surface, In each of the plurality of semiconductor chips, the plurality of second terminals are arranged in a mirror-symmetrical manner with respect to the symmetry plane. The plurality of semiconductor chips include a third semiconductor chip and a fourth semiconductor chip, The third semiconductor chip and the fourth semiconductor chip are stacked in such a manner that the first surface of the third semiconductor chip contacts the first surface of the fourth semiconductor chip, and the plurality of first terminals of the third semiconductor chip are connected to the plurality of first terminals of the fourth semiconductor chip. The second semiconductor chip and the third semiconductor chip are stacked such that the second surface of the second semiconductor chip is in contact with the second surface of the third semiconductor chip, and the plurality of second terminals of the second semiconductor chip are connected to the plurality of second terminals of the third semiconductor chip.

[0106] According to the semiconductor memory device according to the fifth aspect of the present disclosure, in the semiconductor memory device according to the fourth aspect, In each of the plurality of semiconductor chips, each pair of second terminals arranged in mirror-symmetry with respect to the symmetry plane is connected to wiring associated with the same function.

[0107] According to the semiconductor memory device according to the sixth aspect of the present disclosure, in the semiconductor memory device according to the fourth aspect, In each of the multiple semiconductor chips, the multiple second terminals include a third terminal group and a fourth terminal group, the third terminal group and the fourth terminal group are configured in a mirror-symmetrical manner with respect to the symmetry plane, and the third terminal group and the fourth terminal group are connected to a group of wirings associated with the same functional group.

[0108] According to the semiconductor memory device according to the seventh aspect of the present disclosure, in the semiconductor memory device according to one of the fourth to sixth aspects, each of the plurality of semiconductor chips The plurality of first terminals include a first terminal group and a second terminal group, wherein the first terminal group and the second terminal group are arranged in a mirror-symmetrical manner with respect to the symmetry plane. The plurality of second terminals include a third terminal group and a fourth terminal group, and the third terminal group and the fourth terminal group are arranged in a mirror-symmetrical manner with respect to the symmetry plane. The first terminal group and the third terminal group are arranged on the same side of the symmetry plane, The first terminal group and the third terminal group are connected to each other via a first wiring group, The second terminal group and the fourth terminal group are connected to each other via a second wiring group, The first wiring group and the second wiring group have an asymmetric layout with respect to the symmetry plane.

[0109] According to the semiconductor memory device according to the eighth aspect of the present disclosure, in the semiconductor memory device according to the seventh aspect, In each of the plurality of semiconductor chips, the second wiring group has a layout that is translationally symmetrical to the first wiring group.

[0110] According to the semiconductor memory device according to the ninth aspect of the present disclosure, in the semiconductor memory device according to the seventh aspect or the eighth aspect, In each of the plurality of semiconductor chips, Only one wiring in the first wiring group is connected to a circuit element, and the remaining wirings in the first wiring group are not connected to a circuit element. Only one wiring in the second wiring group is connected to a circuit element, and the remaining wirings in the second wiring group are not connected to a circuit element.

[0111] According to the semiconductor memory device according to the tenth aspect of the present disclosure, in the semiconductor memory device according to one of the seventh to ninth aspects, In each of the plurality of semiconductor chips, the wirings included in the first wiring group and the second wiring group are associated with the same function.

[0112] According to the semiconductor memory device according to the tenth aspect of the present disclosure, in the semiconductor memory device according to one of the seventh to ninth aspects, In each of the plurality of semiconductor chips, The wirings included in the first wiring group are associated with at least two functions, The wirings included in the second wiring group are associated with the at least two functions.

[0113] [Industrial Availability] According to one aspect of the present disclosure, a semiconductor memory device is provided having a novel structure different from the existing F2B connection.

Claims

1. A semiconductor memory device comprising a plurality of semiconductor chips stacked on top of each other, wherein: The plurality of semiconductor chips include circuit elements and wiring arranged in the same layout between the plurality of semiconductor chips, Each of the plurality of semiconductor chips has a first surface and a second surface facing each other, and a plurality of first terminals arranged on the first surface. In each of the plurality of semiconductor chips, the plurality of first terminals are arranged in mirror symmetry with respect to a symmetry plane orthogonal to the first surface and the second surface. The plurality of semiconductor chips include a first semiconductor chip and a second semiconductor chip, The first and second semiconductor chips are stacked such that the first surface of the first semiconductor chip is in contact with the first surface of the second semiconductor chip, and the first terminals of the first semiconductor chip are connected to the first terminals of the second semiconductor chip.

2. The semiconductor memory device according to claim 1, wherein In each of the plurality of semiconductor chips, each pair of first terminals arranged in mirror-symmetry with respect to the symmetry plane is connected to wiring associated with the same function.

3. The semiconductor memory device according to claim 1, wherein In each of the multiple semiconductor chips, the multiple first terminals include a first terminal group and a second terminal group, the first terminal group and the second terminal group are arranged in mirror symmetry with respect to the symmetry plane, and the first terminal group and the second terminal group are connected to multiple wirings associated with the same functional group.

4. The semiconductor memory device according to claim 1, wherein Each of the plurality of semiconductor chips further includes a plurality of second terminals arranged on the second surface, In each of the plurality of semiconductor chips, the plurality of second terminals are arranged in a mirror-symmetrical manner with respect to the symmetry plane. The plurality of semiconductor chips include a third semiconductor chip and a fourth semiconductor chip, The third semiconductor chip and the fourth semiconductor chip are stacked in such a manner that the first surface of the third semiconductor chip contacts the first surface of the fourth semiconductor chip, and the plurality of first terminals of the third semiconductor chip are connected to the plurality of first terminals of the fourth semiconductor chip. The second semiconductor chip and the third semiconductor chip are stacked such that the second surface of the second semiconductor chip is in contact with the second surface of the third semiconductor chip, and the plurality of second terminals of the second semiconductor chip are connected to the plurality of second terminals of the third semiconductor chip.

5. The semiconductor memory device according to claim 4, wherein: In each of the plurality of semiconductor chips, each pair of second terminals arranged in mirror-symmetry with respect to the symmetry plane is connected to wiring associated with the same function.

6. The semiconductor memory device according to claim 4, wherein: In each of the multiple semiconductor chips, the multiple second terminals include a third terminal group and a fourth terminal group, the third terminal group and the fourth terminal group are configured in a mirror-symmetrical manner with respect to the symmetry plane, and the third terminal group and the fourth terminal group are connected to a group of wirings associated with the same functional group.

7. The semiconductor memory device according to claim 4, wherein: In each of the plurality of semiconductor chips, The plurality of first terminals include a first terminal group and a second terminal group, wherein the first terminal group and the second terminal group are arranged in a mirror-symmetrical manner with respect to the symmetry plane. The plurality of second terminals include a third terminal group and a fourth terminal group, and the third terminal group and the fourth terminal group are arranged in a mirror-symmetrical manner with respect to the symmetry plane. The first terminal group and the third terminal group are arranged on the same side of the symmetry plane, The first terminal group and the third terminal group are connected to each other via a first wiring group, The second terminal group and the fourth terminal group are connected to each other via a second wiring group, The first wiring group and the second wiring group have an asymmetric layout with respect to the symmetry plane.

8. The semiconductor memory device according to claim 7, wherein: In each of the plurality of semiconductor chips, the second wiring group has a layout that is translationally symmetrical to the first wiring group.

9. The semiconductor memory device according to claim 8, wherein: In each of the plurality of semiconductor chips, Only one wiring in the first wiring group is connected to a circuit element, and the remaining wirings in the first wiring group are not connected to a circuit element. Only one wiring in the second wiring group is connected to a circuit element, and the remaining wirings in the second wiring group are not connected to a circuit element.

10. The semiconductor memory device according to claim 9, wherein: In each of the plurality of semiconductor chips, the wirings included in the first wiring group and the second wiring group are associated with the same functional group.

11. The semiconductor memory device according to claim 9, wherein: In each of the plurality of semiconductor chips, The wirings included in the first wiring group are associated with at least two functions, The wirings included in the second wiring group are associated with the at least two functions.

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