Impedance matching test method for memory chip

Abstract

The invention relates to the technical field of data storage, and discloses an impedance matching test method for a memory chip, which comprises the following steps of: performing different impedance value matching tests on three dimensions of CA-odt, DQ-odt and SOC-odt of the memory chip to obtain different impedance combinations; performing impedance verification on the memory chip according to different impedance combinations; screening the memory chips outside the range of different impedance combinations, and determining the memory chips outside the range of different impedance combinations as the memory chips with obvious impedance differences, namely the memory chips with poor impedance matching; and screening the memory chips in the range of different impedance combinations, recording the impedance combinations passing through all the test items, and determining the effective working range of different impedance values of each dimension. According to the invention, the memory chip is ensured to have enough impedance matching tolerance under specific mainboard design and load conditions, so that the stability of long-term operation of the system is ensured.

Description

Technical Field

[0001] This invention relates to the field of data storage technology, and in particular to an impedance matching test method for memory chips. Background Technology

[0002] Impedance matching testing of memory chips is a core technology for ensuring signal integrity in high-speed digital systems. With data transfer rates exceeding 6400MT / s for memory technologies such as DDR5 and LPDDR5, signal integrity has become a critical factor affecting system stability and performance. Impedance mismatch can lead to signal reflection, ringing, and timing deviations, severely impacting system reliability. In modern servers, high-performance computing, and mobile devices, accurate impedance matching testing is not only a necessary step in product verification but also a fundamental guarantee for achieving high-quality signal transmission.

[0003] The impedance of existing memory chips is set according to the average impedance of a certain number of chips (e.g., 5000 chips of the same capacity). However, some memory chips have special impedances, resulting in poor impedance matching. Existing technology cannot quickly, accurately, and effectively eliminate memory chips with poor impedance matching. Summary of the Invention

[0004] This invention provides an impedance matching test method for memory chips, which can solve the technical problem that existing technologies cannot quickly, accurately, and effectively eliminate memory chips with poor impedance matching.

[0005] To solve the above-mentioned technical problems, one technical solution adopted by the present invention is: to provide an impedance matching test method for a memory chip, the method comprising: Different impedance matching tests were performed on the memory chip in three dimensions: CA-odt, DQ-odt, and SOC-odt, to obtain different impedance combinations. Impedance verification of memory chips is performed based on different impedance combinations; Screen memory chips outside the range of different impedance combinations to identify those with significant impedance differences, i.e., memory chips with poor impedance matching. Screen memory chips within a range of different impedance combinations, record the impedance combinations that pass all test items, and determine the effective operating range of different impedance values ​​for each dimension.

[0006] The beneficial effects of the present application are: by actively and systematically exploring the boundary of memory interface impedance matching, instead of only verifying a set of nominal values. Through multi-dimensional parameter scanning and functional testing, the safe working area of impedance is accurately defined. It can effectively identify those chips with subtle impedance defects that may be missed in simple testing. Ensure that the memory chip has sufficient impedance matching tolerance under specific motherboard design and load conditions, thereby ensuring the stability of the system during long-term operation. Accumulated large amount of test data can provide valuable reference for the design of ODT circuit and PCB of the next generation of memory interface. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is a flowchart of the impedance matching test method of the memory chip of the first embodiment of the present application. DETAILED DESCRIPTION

[0008] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0009] The terms "comprising" and "having" and any variations thereof in the present application are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but can optionally include steps or units not listed, or can optionally include other steps or units inherent to the process, method, product or device.

[0010] In this document, the term "embodiment" means that the specific features, structures or characteristics described in connection with the embodiment can be included in at least one embodiment of the present application. The phrase appears at various places in the specification does not necessarily all refer to the same embodiment, nor is it necessarily mutually exclusive of other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0011] Figure 1 is a flowchart of the impedance matching test method of the memory chip of the first embodiment of the present application. As shown in Figure 1 , the method comprises: Step S1, match test on CA-odt (command pin of the chip, the master sends data through the command pin), DQ-odt (data pin end (close), SOC-odt (referring to the SOC end of the CPU) three dimensions of the memory chip with different impedance values (impedance values include 40, 48, 60, 80, 120, 240 ohms (standard impedance) and the like), and different impedance combinations are obtained; Step S2, impedance verification is performed on the memory chip according to different impedance combinations respectively; Step S3, screen the memory chips outside the range of different impedance combinations, and determine the memory chips outside the range of different impedance combinations as the memory chips with obvious impedance difference, i.e. the memory chips with poor impedance matching; Step S4, screen the memory chips within the range of different impedance combinations, record the impedance combinations that pass all test items, and determine the effective working range of different impedance values of each dimension (for example, DQ-ODT can work normally between 48 ohms and 80 ohms).

[0012] Impedance matching is performed on CA-odt (command pin of the chip, the master sends data through the command pin), DQ-odt (data pin end (close), SOC-odt (referring to the SOC end of the CPU) and the like three dimensions of the memory chip, impedance values include 40, 48, 60, 80, 120, 240 ohms (standard impedance) and the like, each dimension changes the impedance value for testing, and different impedance combinations are obtained, for example, the impedances corresponding to the three dimensions are 40 ohms, 48 ohms and 60 ohms, after the impedance setting is completed, read and write test is performed on the memory chip, whether the memory chip works normally is detected, all impedance combinations that make the memory chip work normally are obtained, for example, the first impedance combination of the three dimensions is 40, 48 and 60, the second impedance combination is 48, 60 and 80, and the third impedance combination is 80, 120 and 24, and then the range of impedance of each dimension is determined, so as to determine the range of impedance combination, and the chip is verified by using the range of impedance combination, the chip not in the range of impedance combination can be screened out, so as to determine the chip with obvious impedance difference, i.e. the chip with poor impedance matching.

[0013] In LPDDR5 memory systems, CA-odt, DQ-odt, and SOC-odt form a complete impedance matching system. CA-odt (Chip Command On-Die Termination) corresponds to the impedance of the chip's command address pin, through which the host sends control commands and address information. In LPDDR5, the CA bus uses the LVSTL (Low Voltage Short Stubs Termination Logic) standard, with a VDDQ voltage of 0.5V and a maximum VOH of about 300mV in the write direction. DQ-odt (Data Pin On-Die Termination) refers to the impedance of the data pin, responsible for data signal transmission. LPDDR5 interface contains 32 DQ pins, with 8 bits per group, each group with two differential lines RDQS and WCK. SOC-odt (System-on-Chip On-Die Termination) is the SOC end impedance of the CPU, representing the interface characteristics between the system-on-chip and the memory.

[0014] According to JEDEC standards, the target impedance requirements for LPDDR5 are: DQ / CA / CS signals 40Ω, DQS / CLK differential signals 75Ω, and WCK signals 65Ω. These standard values are determined based on signal integrity theory, aiming to ensure optimal power transmission and minimal reflection during signal transmission. The basic principle of impedance matching is to make the characteristic impedance of the transmission line equal to the load impedance, so as to achieve complete signal transmission and avoid energy reflection.

[0015] In actual testing, the impedance characteristics of these three dimensions interact with each other, forming a complex coupling relationship. For example, when the CA-odt impedance changes, it will not only affect the transmission quality of the command signal, but also affect the adjacent data signal through electromagnetic coupling. Therefore, a single-dimensional test method cannot fully evaluate the impedance characteristics of the memory chip, and a three-dimensional collaborative test method must be used.

[0016] The test scheme selects 40, 48, 60, 80, 120, and 240 ohms, which cover the commonly used impedance range of memory chips. The basis for selecting these specific values includes: 40Ω is the standard single-ended impedance requirement of LPDDR5; 48, 60, and 80 ohms represent a typical variation range around the standard value, which can simulate the effects of manufacturing process deviations and environmental temperature changes; 120 and 240 ohms represent larger impedance deviations, used to test the working ability of the chip under extreme conditions.

[0017] The test matrix adopts a full combination design, that is, 6 impedance values of each dimension are combined with each other to form 6x6x6=216 different impedance configurations. The advantage of this design method is that it can comprehensively cover all possible impedance combinations, ensuring the completeness and reliability of the test. In actual testing, each combination needs to be tested independently, and the corresponding signal quality parameters are recorded.

[0018] The construction of the test matrix also needs to consider the actual electrical connection topology. In the LPDDR5 system, common topologies include Star type, Fly-by type and hybrid type. For Star type topology, theoretically, it needs to satisfy the impedance relationship Z2=2xZ1, and in actual engineering implementation, the Driver impedance is 34Ω, the SOC package impedance is 40Ω±10%, the PCB main impedance is 30Ω±15%, and the PCB branch impedance is 60Ω±10%. Fly-by topology has relatively uniform overall impedance due to short branches, and usually uses Driver impedance of 34Ω, SOC package impedance of 45Ω±10%, and PCB impedance of 45Ω±10%.

[0019] The accuracy of impedance testing directly affects the reliability of test results, so precise test equipment needs to be used. The core test equipment includes a vector network analyzer (VNA), such as Keysight E5071C, which covers a frequency range of 9kHz to 8.5GHz, provides 8-bit precision, and can meet various testing needs from low to high frequencies. Time domain reflectometer (TDR) such as T3SP series has a typical rise time of 30ps, supports S parameter measurement up to 15GHz, and has a 50,000-point memory capacity to test devices up to 50 meters.

[0020] For dedicated testing of memory chips, high-speed memory test systems such as Advantest T5835 also need to be configured, which support data rates up to 5.4Gbps, can test 768 devices simultaneously, and have overall timing accuracy of ±50ps. These devices can simulate real memory working environment and accurately measure signal quality under different impedance configurations.

[0021] Controlling the testing environment is crucial to ensuring the accuracy of test results. According to industry standards, the testing environment should be controlled at a temperature of 23±2℃ and a relative humidity of 50±5% RH. For automotive-grade chips, the testing temperature range needs to be extended to -40℃ to 125℃. The importance of environmental control lies in the fact that for every 10℃ increase in temperature, the mean time between failures (MTBF) of electronic components decreases by 30%-50%, and chip performance degrades by 25%. Simultaneously, excessively low humidity (<30% RH) can lead to electrostatic discharge (ESD) accumulation exceeding 10kV, potentially damaging sensitive components such as MOSFETs.

[0022] The design of the test fixture also needs to meet stringent technical requirements. The impedance of the test point must match the transmission line; LPDDR4X typically uses a 40Ω or 48Ω single-ended impedance. The capacitance introduced by the test point should be less than 0.5pF, and the inductance less than 1nH to avoid affecting signal integrity. In terms of physical layout, miniature test points (diameter ≤ 0.6mm) should be used. The test points should be connected to the signal lines via short stakes with a length ≤ 50mil (1.27mm), and teardrop pads should be used to reduce impedance abrupt changes.

[0023] ZQ calibration is a core technology in memory chip impedance testing. Its purpose is to adjust the internal pull-up and pull-down resistor values ​​to match a specific standard impedance using an external, precise 240Ω standard resistor. In DDR3 and DDR4, the ZQ pin of each DRAM is connected to an external 240Ω resistor with an accuracy of ±1%. The calibration process is achieved by comparing the VOH signal with an internally generated reference voltage (VDDQ / 2). P-channel tuners are individually tuned using the VOH signal until the XRES voltage equals the reference voltage.

[0024] In LPDDR5, ZQ calibration technology has been further developed. The ZQCAL (Impedance Calibration) process for LPDDR5X memory is used to calibrate the impedance of the output driver and on-chip termination (ODT) of the memory interface. After calibration, the internal register stores the calibration result and uses this value for impedance control of the output driver and ODT. This calibration mechanism can compensate for the effects of process, voltage, and temperature (PVT) variations on impedance characteristics, ensuring optimal signal integrity under different operating conditions.

[0025] Impedance measurement adopts four-wire method test, which eliminates the influence of contact resistance through four-wire system, and the precision can reach ±0.1 mΩ, especially suitable for low resistance value solder joint detection, such as the power pin of LPDDR chip. For high-speed signals, TDR (time domain reflectometer) is also needed to measure the transmission line impedance, which requires an accuracy of 50Ω±5%, and can identify impedance mutation points. The calibration of test equipment also has strict requirements, TDR is calibrated every 6 months, network analyzer is calibrated every 3 months, and the calibration items include "impedance accuracy", "time reference" and "frequency accuracy". After calibration, the standard impedance board is used for verification to ensure that the test value deviates from the standard value by ≤±1Ω.

[0026] Impedance verification not only includes the measurement of electrical parameters, but also needs to conduct comprehensive functional test to verify the actual working performance of memory chips under different impedance combinations. Functional test verifies the logic function and protocol compatibility of memory chips under normal working conditions, such as eMMC5.1 protocol of eMMC, JEDEC standard of LPDDR5, etc.

[0027] The test system adopts ATE (automatic test equipment), integrates multi-channel signal source and high-speed digital interface, supports parallel test, and the throughput can reach 1000+ chips / hour. Protocol analyzer is used to verify high-speed interface, such as 11.6Gbps rate of UFS 3.1, to detect bit error rate (BER<10^-12) and timing tolerance. These test equipment can simulate the real system working environment and comprehensively evaluate the functional integrity of memory chips under different impedance configurations.

[0028] Functional verification test includes multiple key items. First, signal integrity test, which evaluates signal quality through eye diagram analysis. The larger the "eye" of the eye diagram, the better the signal quality. Eye width represents the effective timing margin, and the receiver needs to sample data within the eye opening time window; eye height represents the effective voltage margin, and higher eye means that there is a larger difference between the logic high and low levels of the signal.

[0029] Second, timing characteristic test, including the measurement of key timing parameters such as tRP (row precharge time), tRCD (row-to-column address delay), tWR (write recovery time), tRAS (row activation time), etc. These parameters directly affect the access speed of memory and system performance, and need to be accurately measured and optimized under different impedance configurations.

[0030] To ensure the reliability and repeatability of test results, a standardized test procedure needs to be established. The test procedure includes five main stages: initial calibration, parameter setting, data acquisition, result analysis, and report generation. The initial calibration stage connects an external 240Ω resistor through the ZQ pin to calibrate the driver output impedance, with the formula Z_driver = R_ext × N, where N is the calibration code scaling factor.

[0031] The parameter setting stage requires configuring the impedance values of CA-odt, DQ-odt, and SOC-odt according to the test matrix. Each impedance combination test includes: measuring the actual impedance value of each pin to verify whether it is within the allowed deviation range of the target value (usually ±5%); performing signal integrity tests, including eye diagram quality, jitter, noise, and other parameter measurements; executing functional tests to verify basic functions such as data read / write, refresh, self-refresh, etc.; recording power consumption, temperature, and other working parameters.

[0032] In terms of quality control, multiple verification mechanisms need to be established. First, device calibration verification ensures the accuracy and stability of the test equipment. Second, environmental monitoring monitors temperature, humidity, voltage, and other environmental parameters in real time to ensure that the test conditions meet the requirements. Third, data verification analyzes the collected data in real time, identifies outliers, and performs repeated tests. Finally, cross-validation uses different test equipment to independently measure key parameters to ensure the consistency of the results.

[0033] The determination of out-of-range chips is based on multiple technical standards, mainly including impedance deviation, signal integrity, and functional performance. In terms of impedance deviation, according to JEDEC standards and engineering practices, when the measured impedance value deviates from the target value by more than ±5%, it can be determined as an impedance anomaly. For example, for a standard impedance of 40Ω, the measured value should be within the range of 38Ω to 42Ω, and exceeding this range is determined as an out-of-range chip.

[0034] The determination standard of signal integrity is more complex, mainly through eye diagram analysis and bit error rate testing. When the eye height is lower than 155mV (JEDEC standard requirement) or the eye width is less than the specified timing margin, it indicates that there is a problem with signal quality. In terms of bit error rate, when the BER (bit error rate) exceeds 10^-12, it can be determined as a functional anomaly. In addition, the influence of signal reflection needs to be considered, when the reflection coefficient exceeds the tolerance threshold of -15dB, it indicates that there is a serious impedance mismatch problem.

[0035] In actual testing, the impact of temperature and voltage changes on impedance characteristics also needs to be considered. According to the 10℃ rule, the performance of electronic components decreases by 25% for every 10℃ increase in temperature. Therefore, when testing at different temperature conditions (such as 25℃, 85℃, -40℃), the judgment criteria need to be adjusted accordingly. For automotive-grade chips, since the operating temperature range is wider (-40℃~125℃), the judgment criteria need to be more stringent.

[0036] Through analysis of a large amount of test data, out-of-range chips can be classified into several typical abnormal patterns. The first type is single-dimensional abnormality, i.e., only one dimension of CA-odt, DQ-odt, or SOC-odt has impedance deviation. For example, the CA-odt of a certain chip is 45Ω (deviation +12.5%), while DQ-odt and SOC-odt are within the normal range. This situation is usually caused by manufacturing process deviations, such as uneven metal layer thickness, contact resistance changes, etc.

[0037] The second type is two-dimensional abnormality, i.e., two dimensions have impedance deviation at the same time. Common combinations include CA-odt and DQ-odt being simultaneously high or low, which may be related to the overall design or process control of the chip. Through correlation analysis, it is found that there is a certain positive correlation between CA-odt and DQ-odt, with a correlation coefficient of about 0.6~0.8, indicating that they may be affected by common factors.

[0038] The third type is three-dimensional abnormality, i.e., all three dimensions deviate from the normal range. This situation is less common but the most serious, usually indicating that the chip has systemic defects, such as design errors, material problems, or manufacturing process out of control, etc.

[0039] In addition to impedance deviation, the functional performance characteristics of abnormal chips also need to be analyzed. For example, some chips may have data read / write errors under certain impedance combinations, showing fixed pattern errors; others may have timing violations, such as tRCD or tRP exceeding the specification requirements; and some may have stability problems under high load conditions, such as frequent refresh failures or self-refresh errors, etc.

[0040] For the out-of-range chips screened out, in-depth fault localization and root cause analysis are needed. First, the impedance abnormal point is precisely located by TDR test. The picosecond-level pulse of TDR can precisely locate the impedance abnormal point, such as the impedance jump at the connection between the golden finger and the PCB. It is often found in actual measurement that the impedance value deviates from the nominal 50Ω±10%, which will cause the signal reflection to exceed the tolerance threshold of -15dB.

[0041] During the failure localization process, the connection quality inside the chip package, including the length, width, and contact resistance of the bonding wires; the impedance continuity of the PCB traces, especially at via, pad, and trace width changes; the connector contact quality, such as the plating thickness, surface roughness, and contact pressure of the gold fingers; and the power integrity, including the configuration of decoupling capacitors, the impedance of the power plane, and the noise level.

[0042] The root cause analysis employs the FMEA (Failure Mode and Effect Analysis) method, combined with advanced techniques such as neural networks and genetic algorithms. Studies have shown that by integrating the FMEA, Taguchi method, neural networks, and genetic algorithm optimization framework (FMEA-TSTM-NNGA), it is possible to effectively identify and optimize key factors that affect impedance characteristics. The analysis process includes: identifying potential failure modes, evaluating the severity, probability of occurrence, and detection difficulty of failures; determining key process parameters through the Design of Experiment (DOE) method; establishing a prediction model to optimize the process parameter combination.

[0043] Determining the effective working range of each dimension requires the use of multi-dimensional statistical analysis methods. First, calculate the stability parameters of each impedance combination, including the proportion of unqualified samples, the total number of samples, the impedance mean, and the impedance variance. Among them, the impedance mean μ reflects the average level of the chip impedance under this combination, and the impedance variance reflects the dispersion degree of the impedance value.

[0044] The calculation formula of the quality evaluation coefficient λ is: λ = μ × (1-f) / σ , where f is the proportion of unqualified samples. This coefficient considers three factors: the impedance mean, the pass rate, and the dispersion degree, which can comprehensively evaluate the advantages and disadvantages of the impedance combination. When the λ value is high, it indicates that the impedance combination has good working performance.

[0045] Correlation analysis can reveal the relationship between different dimensions. Correlation analysis provides a numerical measure to measure the degree to which the change of one variable can be attributed to another variable. Studies have shown that the correlation coefficient between CA-odt and DQ-odt is about 0.7, indicating a strong positive correlation between the two; while the correlation between SOC-odt and the other two dimensions is relatively weak, with a correlation coefficient of about 0.3~0.4, indicating that SOC-odt is mainly affected by system design.

[0046] When determining the effective working range, the impact of production yield also needs to be considered. By analyzing the yield distribution under different impedance combinations, the optimal impedance range can be determined. For example, when DQ-odt is between 48 ohms and 80 ohms, the yield is over 95%, while outside this range, the yield drops sharply.

[0047] Based on the yield-based threshold method, set the yield ≥ 95% as the lower limit of the effective working range. By analyzing the yield distribution under different impedance values, the effective interval of each dimension can be determined. For example, when DQ-odt is between 48 ohms and 80 ohms, the yield reaches 96.5%, while below 48 ohms or above 80 ohms, the yield drops to 85% and 88% respectively.

[0048] Based on the signal integrity-based performance method, by analyzing key performance indicators such as eye diagram quality, bit error rate, timing margin, etc., to determine the impedance range that meets the design requirements. For example, when DQ-odt is between 50 ohms and 70 ohms, the eye height reaches 180mV or more, meeting the JEDEC standard requirements; while outside this range, the eye height drops to below 155mV, close to the critical value.

[0049] Based on the production process capability-based process method, by analyzing the capability index (Cp and Cpk) of the manufacturing process, to determine the impedance range that the process can stably control. When Cp≥1.33 and Cpk≥1.0, it indicates that the process capability is sufficient, and the corresponding impedance range can be determined as the effective working range.

[0050] For the DQ-odt dimension, comprehensive analysis shows that its effective working range is 48 ohms to 80 ohms. This range not only guarantees good signal integrity and functional performance, but also takes into account the realizability of the production process, with high engineering practical value.

[0051] Utilize the parallel processing capability of modern test equipment to test multiple chips or multiple channels simultaneously. For example, Teradyne's Magnum V system can provide up to 20,480 digital channels, each with 1600 Mbps processing capability. Through parallel testing, the test time can be shortened to 1 / 10 or even 1 / 100 of the original.

[0052] By analyzing the historical data of the test equipment, predict the equipment failure and performance degradation trend, and carry out maintenance and calibration in advance. This not only reduces the equipment downtime, but also ensures the long-term stability of the test results.

[0053] Based on machine learning technology, develop algorithms that can dynamically adjust the test strategy according to the test results. For example, when it is found that the yield of a certain impedance combination is very high, the test frequency of this combination can be reduced; conversely, when abnormal patterns are found, the test density of related combinations can be increased.

[0054] Step S1 includes: Test configuration and initialization on automatic test equipment (ATE) or specific system level test (SLT) platforms; CA-ODT and DQ-ODT are dynamically configured by writing mode register (MRS) of memory chips, and SOC-ODT value is set by configuring internal register of CPU. (JEDEC standards (such as DDR4 / 5) define optional ODT resistance value gears, such as 40, 48, 60, 80, 120, 240 ohms, etc., and modern memory controllers and chips support dynamic switching of these gears.) The above three odt dimensions correspond to three key interface interfaces in the cooperative work of memory subsystem. The goal of impedance matching is to ensure that the signal is effectively absorbed at the end of the transmission path, preventing signal distortion caused by reflection. CA-ODT (command / address bus termination resistance): CA bus is unidirectional, issued by memory controller (usually integrated in SOC of CPU) and sent to memory chip. ODT resistance is usually placed inside the CA pin on the memory chip side. Its role is to ensure that the command and address signals are cleanly terminated at the memory chip end, preventing reflected signals from interfering with subsequent commands. Matching points: CA bus usually uses Fly-by topology to connect multiple memory chips, and the time of signal reaching different chips is slightly different. Therefore, the optimization of CA-ODT is crucial to ensure that all chips can correctly receive instructions. DQ-ODT (data bus termination resistance): DQ bus is bidirectional and used for read and write data transmission. ODT resistance is on the memory chip side. When writing data, the memory controller sends data, at which time the DQ-ODT on the memory chip side should be enabled to optimize the quality of received signals. Matching points: DQ signal has the highest speed and is most sensitive to integrity. Improper DQ-ODT value setting can cause data eye closure and increase error rate. SOC-ODT (memory controller termination resistance): This ODT is located on the data pin inside the CPU / SOC. It mainly functions when reading data, at which time the memory chip becomes the sending end and the CPU is the receiving end. Enabling SOC-ODT can effectively terminate the data signal from the memory chip and improve reading stability.

[0055] ATE platform (such as Advantest T5835, Teradyne UltraFLEX) needs to be connected with memory chips through special test fixtures. The key configuration points include: accurately corresponding the digital channel, analog measurement channel of ATE with the CA (command address) pin, DQ (data) pin, ZQ (calibration) pin, and power supply pin (VDD, VDDQ) of the memory chip, with an error of within ±0.1 mm, to avoid signal attenuation caused by contact offset. Calibration is performed to ensure that the deviation of channel output impedance from the target impedance of the memory chip is ≤±1%, for example, when testing 40Ω OD T, the ATE channel impedance needs to be stable at 40±0.4Ω. According to the JEDEC standard, the power supply parameters of the memory chip are set (DDR5 standard VDD=1.1V, VDDQ=1.1V), and the delay of the command / data signal is calibrated through the timing generator of ATE (tCK clock period deviation ≤±5ps), to ensure the matching of timing characteristics with the memory chip.

[0056] The SLT platform is built based on an actual system motherboard (such as a motherboard with Intel 12th generation Core or AMD Ryzen processor). The key configuration points include: installing the memory chip to be tested into the motherboard memory slot, ensuring that the gold finger contact pressure meets the specifications (usually 20-30N), while connecting the CPU power supply, motherboard power supply, and debugging interface (such as JTAG, SPI), to ensure that the system can start normally and enter the test mode. Access the high-speed signal acquisition card (such as Keysight UXR series) through the PCIe interface to monitor the signal waveform of the CA, DQ bus in real time; at the same time, connect the power supply monitoring module to record the power consumption change of the memory chip during the test, to avoid the influence of power supply fluctuation on impedance test results. The SLT platform needs to be placed in a constant temperature and humidity chamber, with a temperature of 23±2℃ and a humidity of 50±5% RH (vehicle test needs to be extended to -40℃~125℃), and the BIOS of the motherboard is closed to dynamic frequency adjustment (such as Intel XMP, AMD EXPO), to ensure that the memory works at a fixed frequency (such as DDR5-4800), to exclude the interference of frequency fluctuation on impedance characteristics.

[0057] Whether it is ATE or SLT platform, it needs to complete the test protocol loading and initialization through the software level to ensure that it can interact with the memory chip in compliance with the instructions: load JEDEC DDR4 / 5 test protocol stack, send "reset instruction (RESET#)" through the test program of ATE (such as Advantest TestBuilder) to make the memory chip enter the initialization state; then execute ZQ calibration instruction (ZQCL) to calibrate the internal ODT resistance network of the chip through the external 240Ω standard resistor (accuracy ±1%) to lay the foundation for subsequent dynamic configuration. Enter "test mode" through the motherboard BIOS or special debugging tool (such as Intel Platform Debug Toolkit) to disable the memory management function of the operating system and directly send initialization instructions through the memory controller of the CPU; at the same time, configure the "memory controller mode register" of the CPU to switch the ODT control authority of the SOC end to "manual configuration mode" to avoid the interference of automatic adjustment of the system. After initialization, confirm the chip state by reading the "status register (SR)" of the memory chip - for example, the SR [0] bit of the DDR5 chip is "0" indicating that the initialization is successful, and the SR [5] bit is "1" indicating that the ZQ calibration is completed; if the state is abnormal, the reset and calibration process needs to be executed again until the test requirements are met.

[0058] According to the JEDEC DDR4 / 5 standard, the resistance values of CA-ODT and DQ-ODT are configured through the mode register (MRS) of the memory chip, and the resistance value of SOC-ODT is configured through the internal register of the CPU. All of them support dynamic switching of standard gears such as 40, 48, 60, 80, 120, and 240Ω. The configuration process needs to follow strict instruction timing and bit definition rules.

[0059] The mode register (MRS) of the memory chip is the core of controlling the ODT resistance value. Different types of MRS correspond to different functions, among which MRS1 is responsible for CA-ODT configuration, and MRS2 is responsible for DQ-ODT configuration. The configuration process needs to be executed after the initialization of the memory chip is completed.

[0060] Taking the DDR5 memory chip as an example, the format of MRS instruction is composed of "command cycle (CMD) + address cycle (ADDR)", in which the specific bits of address line (A0-A17) are used to define the ODT resistance value, and the core bit definition is as follows: CA-ODT configuration (MRS1): define the resistance value through A10 and A11 two bits combination, and the correspondence between bit combination and resistance value conforms to JEDEC JESD79-5 standard: DQ-ODT configuration (MRS2): define resistance value by A4, A5, A6 three-bit combination, support more rich gear selection: MRS configuration execution process: on ATE and SLT platform, MRS configuration execution needs to follow strict timing requirements (DDR5 standard tMRD (MRS instruction period) ≥ 4 tCK), specific steps as follows: ATE / SLT platform test software generates corresponding MRS instruction (including CMD and ADDR signals) according to target resistance value, for example, when configuring DQ-ODT to 40Ω, MRS2 instruction A6=1, A5=0, A4=1, other irrelevant address bits are set to default value (such as A0-A3=0). The platform synchronizes with the memory chip through the clock signal (CK / CK#) to ensure that the MRS instruction is sent at the rising edge of CK, and the instruction duration meets the tMRD requirement (such as tCK=0.416ns of DDR5-4800, tMRD≥1.664ns, i.e. at least 4 CK periods). Send MRS command (CMD line output "0011", DDR5 standard) first, then send corresponding ADDR signal in subsequent address period to complete MRS register write. After configuration is completed, confirm whether the resistance value takes effect through "read MRS register" instruction (supported by some chips, or through indirect impedance measurement verification) — for example, on ATE platform, measure the actual impedance of DQ pin through impedance analyzer, the deviation from target value should be ≤±5%, otherwise re-execute configuration process.

[0061] SOC-ODT resistance value is controlled by CPU's internal memory controller register, different manufacturers (Intel, AMD) have different register address and bit definition, but they all follow JEDEC standard resistance value gear requirements, configuration needs to be realized through special debugging interface or software tool.

[0062] Each memory channel corresponds to an independent ODT control register, where Bit3-Bit0 defines the resistance value of SOC-ODT. Connect the CPU's JTAG interface through the Intel Platform Debug Toolkit (PDT) to enter the "Memory Controller Configuration Mode", as follows: select the target memory channel (e.g. Channel 0), and locate the ODT Control Register (address 0x400). According to the target resistance value (e.g. 40Ω), set Bit3-Bit0 to "0110", and leave other irrelevant bits (e.g. Bit4-Bit31) at their default values (0). After writing the register, execute the "Register Synchronization" instruction to ensure that the configuration takes effect. Use the "Impedance Measurement Tool" in the PDT to read the actual impedance at the SOC end, and verify whether it is consistent with the target value (deviation ≤±5%).

[0063] The SOC-ODT register configuration of AMD CPU (take Ryzen 7000 series as an example), the memory controller of AMD Ryzen 7000 series (Zen 4) controls SOC-ODT through the "DRAM ODT Control" register (address: 0xC0010050-0xC001005F), and the core configuration points are as follows: Register bit definition: Bit5-Bit2 defines the SOC-ODT resistance, supporting JEDEC standard resistance: Configure through AMD Debug Tool (ADT) or the "Advanced Memory Settings" interface of the motherboard BIOS, as follows: enter the "M.I.T. (Memory Intelligent Tweaker)" menu in the BIOS, select "DRAM ODT Configuration". Disable the "Auto ODT" function and switch to "Manual" mode, select the target resistance value (e.g. 40Ω) in the "SOC ODT Resistance" option. Save the BIOS settings and restart the system, and after entering the SLT test mode, measure the impedance at the output end of the CPU memory controller through a high-speed signal acquisition card to verify the effectiveness of the configuration.

[0064] In actual testing, the configurations of CA-ODT, DQ-ODT and SOC-ODT need to be executed in coordination to ensure that the impedance combination of the three meets the requirements of the test matrix. The core control logic is as follows: first, configure SOC-ODT (CPU register), then configure CA-ODT (MRS1), and finally configure DQ-ODT (MRS2) - this sequence can avoid signal reflection caused by unstable SOC end impedance, and ensure signal integrity during configuration. When switching impedance combinations (such as from "CA=40Ω+DQ=48Ω+SOC=60Ω" to "CA=48Ω+DQ=60Ω+SOC=80Ω"), the "ODT disable instruction" (such as setting DQ-ODT to Hi-Z in MRS2) needs to be sent first, then the configurations of each dimension are updated in turn, and finally the ODT is re-enabled to avoid impedance conflicts during switching. If a register write fails during configuration (such as the ATE platform returning "instruction timeout"), a "register reset" (send the RESET# instruction to reinitialize) needs to be performed to exclude problems caused by hardware interference or timing deviation and ensure that each impedance combination configuration is effective.

[0065] The impedance of the CA, DQ pins and the SOC end is directly measured by the built-in impedance analyzer (such as Keysight E4990A), and the deviation between the actual value and the target value is recorded. The deviation needs to be ≤±5% (JEDEC standard requirement), for example, when the target is 40Ω, the actual value needs to be within the range of 38-42Ω. The time domain reflection (TDR) waveform of the CA, DQ bus is collected by a high-speed signal acquisition card, the relationship between the reflection coefficient (Γ) and the impedance (Z=Z0×(1+Γ) / (1-Γ), Z0 is the characteristic impedance of the transmission line, usually 50Ω) is analyzed, and the actual impedance value is calculated and compared with the target value.

[0066] If an instruction error occurs during configuration (such as MRS register write failure), the delay of the instruction sending (tCMD (command delay), tADDR (address delay)) needs to be adjusted by the timing generator of the ATE / SLT platform to ensure that the timing requirements of the DDR4 / 5 standard (such as tCMD≥2tCK for DDR5) are met. For the long transmission line of the SLT platform (such as the CA bus length on the motherboard ≥10cm), the "signal equalization" function (such as CTLE continuous time linear equalization) can be configured through the motherboard BIOS to reduce signal attenuation and ensure stable transmission of MRS instructions and register configuration signals.

[0067] Step S2 comprises: All impedance combinations (e.g. 40-48-60, 48-60-80, etc.) of CA-ODT, DQ-ODT and SOC-ODT are traversed according to the preset order of the test procedure. For each impedance combination (R_ca, R_dq, R_soc), a rigorous read-write test is performed.

[0068] The traversal order is set according to the test target, and common preset rules include "dimension priority traversal", "value increasing traversal" and "random traversal", which can be flexibly selected through test procedure parameters: Dimension priority traversal: Set a certain dimension as the "main dimension", and fix the main dimension resistance value first, then traverse the other two dimensions. For example, take R_ca as the main dimension, first fix R_ca=40Ω, then traverse all combinations of R_dq (40→48→60→80→120→240Ω) and R_soc (40→48→60→80→120→240Ω); then R_ca is switched to 48Ω, and the above process is repeated until all combinations are covered. This rule is suitable for analyzing the impact of impedance of a certain dimension on test results, for example, when the system compatibility under different CA-ODT resistance values needs to be verified, this traversal method can be selected.

[0069] Value increasing traversal: Traverse the three dimensions in order from small to large, and the combination order is (40, 40, 40)→(40, 40, 48)→(40, 40, 60)→…→(40, 40, 240)→(40, 48, 40)→(40, 48, 48)→…→(240, 240, 240). This rule is simple in logic, easy to write test procedures and trace combinations, suitable for regular batch testing scenarios, ensuring that all combinations are traversed according to a uniform rule to avoid omissions.

[0070] Random traversal: Through the random number generation algorithm of the test procedure, the order of the 216 combinations is shuffled for traversal. This rule can avoid the cumulative effect of chip heating caused by continuous testing of the same dimension high resistance value combination, reduce system error, and is suitable for high-precision verification scenarios with extremely high requirements for test environment stability (such as car-grade memory chip testing).

[0071] Regardless of which traversal rule is selected, automatic traversal must be implemented through the test procedure of the ATE / SLT platform, and the process consists of five steps: "combination generation - impedance configuration - pre-check - test execution - data recording", as follows: Combination generation: The test program generates an ordered list of 216 impedance combinations according to the preset traversal rules, each combination containing the target resistance values of R_ca, R_dq, and R_soc, such as the list item format "R_ca=40Ω, R_dq=48Ω, R_soc=60Ω", and assigns a unique ID (such as ID=001 to ID=216) to each combination for subsequent data tracing.

[0072] Impedance configuration: The program reads the combination information in list order, calls the "MRS register configuration module" and "CPU internal register configuration module" described above, and automatically completes the resistance configuration of R_ca (MRS1), R_dq (MRS2), and R_soc (CPU register). During the configuration process, the register write state is monitored in real time. If a write timeout occurs (such as more than 100ms without response), the "register reset - reconfiguration" process is automatically executed to ensure successful configuration.

[0073] Pre-check: After configuration is completed, two key checks are performed: one is to measure the actual impedance value through the impedance measurement tool (ATE built-in impedance analyzer / SLT signal acquisition card) to confirm that the deviation of R_ca, R_dq, and R_soc from the target value is ≤±5% (JEDEC standard); the second is to read the memory chip status register (SR) to confirm that there is no abnormal status code (such as DDR5 SR

[12] bit "0" indicating no read / write error). Both checks must pass before entering the test execution phase, otherwise the combination is marked as "configuration exception" and skipped for testing and recording of the exception reason.

[0074] Test execution: For combinations that pass the pre-check, the read / write test process is automatically started, and the preset test items (such as all 0 / 1 write, random data write, continuous read / write cycle, etc.) are executed. Key parameters (such as read / write delay, error rate, power consumption) are collected in real time during the test process.

[0075] Data recording: After the test is completed, the combination ID, target impedance value, actual impedance value, test item result, key parameter data, and other information are recorded in a unified format (such as CSV or database table) to the test log, with the combination test status marked ("pass", "fail", "configuration exception"). This provides data support for subsequent screening of effective impedance ranges.

[0076] In the traversal process, different impedance combinations are switched, which is easy to cause signal reflection due to impedance mutation, affecting the stability of the test, and the following conflict avoidance strategies need to be taken: impedance gradual switching: when switching R_ca or R_dq, first adjust the current dimension impedance to the "disabled (Hi-Z)" state (such as setting R_dq=Hi-Z in MRS2), and then switch to the target resistance value, to avoid the signal impact generated by directly switching from a low resistance value (such as 40Ω) to a high resistance value (such as 240Ω); when switching R_soc, first disable SOC-ODT through the CPU register, then write the target resistance value, and finally re-enable it to ensure smooth switching process. Timing interval control: set an interval of at least 100ms between two combination switches to give the memory chip and CPU memory controller enough time to respond to impedance changes and stabilize the working state; at the same time, perform "power voltage monitoring" during the interval to ensure that the VDD and VDDQ voltage fluctuations are ≤±2%, avoiding the impact of unstable power supply and impedance switching on test results. Abnormal combination skipping: through early test data statistics, a "high-risk combination list" (such as R_ca=240Ω+R_dq=40Ω+R_soc=240Ω, such combination impedance difference is too large, easy to cause signal integrity problem) is preset, if the combination in the list is encountered during the traversal process, it is automatically marked as "high risk" and skipped, saving test time, while avoiding chip damage caused by extreme combinations.

[0077] For each impedance combination (R_ca, R_dq, R_soc), perform "basic read-write verification - stability test - extreme stress test" three-level test to comprehensively verify the read-write function integrity, stability and reliability of the memory chip under the impedance configuration, and the test items and execution steps need to meet the requirements of JEDEC DDR4 / 5 standard (such as DDR5 JESD79-5A).

[0078] The core goal of basic read-write verification is to confirm that the memory chip can normally complete data writing and reading under the current impedance combination, without fixed errors or hardware failures, and the test items include three types of "full mode write-read", "address mapping verification" and "data retention test": Full mode write-read test: Write different modes of data to all address spaces of the memory chip (such as DDR5-16GB chip, address range 0x00000000-0x3FFFFFFF), then read and compare data consistency to verify error-free data transmission. Test steps: All 0 write and read: Write 0x00 data to all addresses of the memory through the test program, wait for 10ms after writing is completed (to ensure stable data storage), then read the data by address, compare the read value with the written value for consistency, and record the error address and error data (if any). All 1 write and read: Repeat the above process, write 0xFF data (8-bit wide) or 0xFFFFFFFF data (32-bit wide, adjust according to memory bus width), and compare consistency after reading. Alternating mode write and read: Write alternating data "0x01010101" "0x10101010" to cover every bit of the memory, verify the correctness of bit-level read and write, and avoid local errors caused by a bit fault. Judgment criteria: The error rate of the three types of write-read test should be 0 (i.e. no data inconsistency), if there is an error, mark the combination "basic read-write failure" and record the error type (such as fixed bit error, random error).

[0079] Address mapping verification test: Verify the mapping relationship between the address lines and storage units of the memory chip to ensure that there is no address conflict or address jump error, which is the basis for all subsequent tests. Test steps: Address incremental write: Start from the starting address (0x00000000), write the same data as the address value in the address incremental order (each time + 1) (such as address 0x00000001 writes 0x00000001), covering 10% of the address space (balance test time and coverage). Random address read: Generate 1000 random addresses (all within the address range of the written data) through a random number generator, read the data at each address, and verify that the read value matches the address value. Address reverse read: Read data in address descending order (from the maximum address of the written data to the starting address), compare consistency, and verify that the address decoding logic has no direction-dependent error. Judgment criteria: The error rate of random read and reverse read should be ≤10^-9 (i.e. a maximum of 1 occasional error in 1000 reads), if the error rate exceeds the threshold, it is determined that the "address mapping is abnormal", and the impedance combination should be checked to determine if the address signal transmission is incorrect.

[0080] Data retention test: Verify the stability of data storage under current impedance combination, i.e. after writing data, the data can still be correctly maintained after a certain time, without loss or tampering. Test steps: Data block writing: Select the middle address region of the memory (such as 0x10000000-0x1000FFFF), write a 32KB data block randomly generated, and record the checksum (such as CRC32 checksum) of the written data. Wait and refresh: Set the waiting time according to the JEDEC standard (the refresh period of DDR5 standard is 3.9us, set to wait for 100 refresh periods, i.e. 390us), during which no read or write operation is performed, only the chip performs automatic refresh. Data reading and verification: Read the 32KB data block written, recalculate the checksum, and compare whether the two checksums are consistent to verify that the data is error-free. Judgment standard: The checksum is completely consistent, and there is no data change. If the checksum does not match, it is determined that the "data retention fails", which may be caused by abnormal transmission of refresh signals due to the current impedance combination, affecting the stability of data storage.

[0081] The goal of stability testing is to confirm that the memory chip is error-free under the current impedance combination for a long time of continuous read and write operation, to verify the continuous reliability of the system, and the test items include "continuous read and write cycle test" "multi-thread concurrent test" "temperature drift test" (only SLT platform supports): Continuous read and write cycle test: Simulate the continuous read and write operation of the memory in the actual application scenario, and expose potential intermittent errors (such as occasional signal reflection caused read and write errors) through long time cycle operation. Test parameters: number of cycles: 1000 (each cycle includes "write 1MB data -> read and verify -> clear data" three steps); data type: random data (generated by pseudo-random number generator to ensure that the data is different each time); read and write rate: execute according to the nominal rate of the memory chip (such as DDR5-4800, read and write rate 4800MT / s), do not overclock. Test steps: initialize the cycle counter (count=0) and error counter (error=0); generate 1MB random data and write it to the specified address block of the memory (such as 0x20000000-0x200FFFFF); read the data of the address block and compare it with the written random data. If they are not consistent, the error counter is incremented by 1, and the error address and data are recorded; clear the data of the address block (write 0x00), and the count counter is incremented by 1; repeat steps 2-4 until the count reaches 1000, and the test is ended. Judgment standard: 1000 cycle error counter error=0, if error occurs, it is determined that the "continuous read and write is unstable", whether the current impedance combination causes the signal integrity to deteriorate over time needs to be analyzed.

[0082] Multi-thread concurrent test (SLT platform exclusive): SLT platform is based on actual system, which can simulate the scene of multi-CPU core concurrent access to memory, verify the response ability of memory to multi-thread read-write request under the current impedance combination, and there is no conflict or deadlock. Test steps: start 4 concurrent threads (corresponding to 4-core CPU, which can be adjusted according to the number of CPU cores) in the test system (such as Linux system) of SLT platform; thread 1-3: perform continuous write-read (data type is random number) to different address blocks of memory (thread 1: 0x10000000-0x1FFFFFFF; thread 2: 0x20000000-0x2FFFFFFF; thread 3: 0x30000000-0x3FFFFFFF); thread 4: perform "address cross read-write", that is, randomly access the address blocks of threads 1-3, read data and immediately write new data, simulate memory sharing access scene; run concurrently for 30 minutes, monitor the read-write error rate of each thread and whether the system appears deadlock (such as thread unresponsive for more than 10s) in real time. Judgment standard: all threads have no read-write error, the system has no deadlock, and the CPU occupancy rate is stable at 80%-90% (no abnormal surge), if thread error or deadlock occurs, it is determined that "multi-thread concurrent fails", which may be caused by the current impedance combination leading to memory controller scheduling conflict.

[0083] Temperature drift test (car-grade / industrial-grade chip test) is for car-grade (-40℃~125℃) or industrial-grade (-40℃~85℃) memory chips, under the current impedance combination, through temperature box to adjust the environmental temperature, verify the read-write stability of the chip at different temperatures, simulate the temperature change scene in actual application. Test steps: place the SLT platform in the temperature box, set the temperature from -40℃, increase by 10℃ per step, until 125℃, keep each temperature point for 30 minutes (let the chip temperature and the environment temperature balance); at each temperature point, perform "continuous read-write cycle test" (500 cycles), record the error rate and read-write delay at different temperatures; after the temperature rising test is completed, decrease the temperature by the same step to -40℃, repeat the test at each temperature point, verify the influence of temperature cycle on read-write performance. Judgment standard: the error rate at all temperature points is 0, the read-write delay fluctuation is ≤±10% (relative to the delay at 25℃ normal temperature), if error or delay fluctuation exceeds the standard at a certain temperature point, it is determined that "temperature drift is unstable", the impedance combination needs to be adjusted to optimize temperature adaptability.

[0084] Extreme pressure test: under the current impedance combination, through high load and high frequency read-write operation, verify the extreme working ability of memory chip, expose potential hardware weakness or design defects, test items include "high bandwidth read-write test" "burst read-write test" "error injection test": High bandwidth read-write test: let the memory chip work at the highest nominal frequency (such as DDR5-6400), perform high-bandwidth continuous read-write operations, verify whether the current impedance combination can support signal transmission under the limit bandwidth, without data loss or error. Test steps: set the working frequency of the memory chip to the highest nominal frequency (such as DDR5-6400, tCK=0.3125ns) through the test program, and confirm that the CPU memory controller has been synchronized to this frequency; start the high-bandwidth test tool (such as the "Bandwidth Test Module" of the ATE platform or "memtest86+" of the SLT platform), set the read-write bandwidth to 90% of the nominal bandwidth of the memory (such as the nominal bandwidth of DDR5-6400 is 51.2GB / s, set the test bandwidth to 46.08GB / s); test continuously for 2 hours, monitor the bandwidth utilization, error rate, chip temperature and power supply current in real time during the test, and record abnormal data (such as sudden decrease in bandwidth, surge in current). Judgment criteria: the bandwidth utilization is stable within ±5% of the set value, the error rate is 0, the chip temperature is ≤105℃ (the upper limit of DDR5 standard), the power supply current fluctuation is ≤±5%, if the bandwidth decreases, errors or temperature / current exceed the standard, it is judged as "unstable limit bandwidth".

[0085] Burst read-write test: simulate the burst read-write scene in actual application (such as CPU cache refresh, video card data transmission), send short length, high frequency burst read-write instructions to the memory under the current impedance combination, verify the response speed and data processing ability of the chip to burst requests. Test steps: set the burst length (BL, Burst Length) according to JEDEC standard, DDR4 supports BL=4 / 8, DDR5 supports BL=8 / 16, select the maximum burst length (such as DDR5's BL=16); send 10000 burst write instructions to the same address block of the memory (write 16 data blocks each time, a total of 16x8=128 bytes), then send 10000 burst read instructions, compare the consistency of read and write data; record the response time of each burst read-write (from instruction sending to data transmission completion), analyze the stability of response time. Judgment criteria: the error rate of burst read-write is 0, the response time fluctuation is ≤±5%, there is no response timeout (timeout is defined as more than 3 times the average response time), if there is error or response timeout, it is judged as "burst read-write failure", and the impedance combination needs to be optimized to improve the burst signal integrity.

[0086] Error Injection Test: Inject controllable errors (e.g. single-bit error, multi-bit error) into memory chips through test programs, verify whether the error detection and correction (ECC, Error-Correcting Code) function of the chip is normal under the current impedance combination, suitable for server-level memory chips supporting ECC. Test steps: Confirm that the ECC function of the memory chip is enabled (enable the ECC bit through the MRS register), and verify that the ECC circuit is working properly; Inject 1 single-bit error into the specified address of the memory through the "Error Injection Module" of the ATE platform (change the data of a certain bit from 0 to 1), then read the data at that address, verify whether the ECC successfully corrects the error and the system does not crash; Inject 1 multi-bit error (e.g. change 2 bits at the same time), verify whether the system can detect the error and trigger an error interrupt (e.g. "Machine Check Exception" of the CPU), to avoid the propagation of error data. Judgment criteria: Single-bit error can be successfully corrected by ECC, multi-bit error can be accurately detected and trigger interrupt, system does not crash or data pollution, if ECC function fails, determine as "error handling failure", need to check whether the impedance combination affects the transmission of ECC signal.

[0087] The step of performing rigorous read-write tests for each impedance combination (R_ca, R_dq, R_soc) includes: Write specific data patterns and read back verification, where the specific data patterns include at least all 0, all 1, interleaved 01, Walking 1 / 0; Apply stress on voltage and timing to test the stability of the memory chip's test signals under non-ideal conditions during read-write tests; Measure the eye height and eye width of the memory chip's test signals to quantitatively evaluate the signal quality.

[0088] For the four types of specific data patterns "all 0, all 1, interleaved 01, Walking 1 / 0", specific write logic and verification processes need to be designed to cover the bit-level, byte-level and block-level storage units of the memory chip, and to expose impedance matching problems under different data patterns (e.g. interleaved 01 pattern easily amplifies signal crosstalk, Walking 1 / 0 pattern can detect single-bit faults).

[0089] Definition and generation rules of the four types of data patterns: For each impedance combination, the four types of data patterns are tested on the ATE platform: The address space of the memory chip is divided into 1MB-sized continuous data blocks (such as a DDR5-16GB chip is divided into 16384 data blocks), and each data block corresponds to a unique block address (such as Block 0: 0x00000000-0x000FFFFF, Block 1: 0x00100000-0x001FFFFF).

[0090] All 0 / All 1 mode: write the same mode data to a single data block (such as all 0 mode writes "0x00000000"), continuously write all addresses of the data block (a total of 262144 32-bit addresses), and the write rate is performed at 50% of the nominal rate of the memory (such as DDR5-4800 at 2400MT / s, to avoid writing too fast and causing data overwrite errors). Interleaved 01 mode: alternately write "0x55555555" and "0xAAAAAAAA" to the same data block, that is, write "0x55555555" to address 0x00000000, write "0xAAAAAAAA" to address 0x00000004, and so on, covering the entire data block. Walking 1 / 0 mode: write different walking data to each address of a single data block, such as writing "0x00000001" to address 0x00000000, writing "0x00000002" to address 0x00000004, and so on until writing "0x80000000" to address 0x000FFFFC to complete the Walking 1 test; the Walking 0 test is the same, writing "0xFFFFFFFE", "0xFFFFFFFD", and other data.

[0091] After writing is completed, wait for 50 ms (far more than the JEDEC standard data retention minimum time), during which other read-write operations are prohibited, and only the power voltage is monitored (ensure that the VDDQ fluctuation is less than or equal to ±1%) to avoid external interference affecting data storage. Hierarchical read-back verification: block-level verification: read all addresses of the entire data block, compare the read data with the written data for consistency, and count the block-level error rate (number of error addresses / total number of addresses). Byte-level verification: randomly select 1000 addresses from the data block without errors in the block-level verification, split the data by bytes (for example, 32-bit data is split into 4 8-bit bytes), compare byte by byte, and locate byte-level errors (for example, bit3 error in a certain byte). Bit-level verification: further split the data by bits for the addresses found to have errors in the byte-level verification, record the position of the error bits (for example, bit5 changes from 1 to 0), form an "error bit distribution map", and analyze whether there is a concentrated bit fault area (if a certain bit is wrong in multiple impedance combinations, it may be that the pin impedance is abnormal). Multi-block coverage: repeat steps 2-4 to test at least 10 different data blocks (covering different physical areas of the memory, such as the beginning, middle, and end areas), to avoid test bias caused by local storage unit defects, and to ensure the representativeness of the verification results.

[0092] The block-level error rate of the four types of data patterns should all be 0, the byte-level error rate should be less than or equal to 10^-10, and the bit-level error should only occur occasionally (no more than 1 bit error in a single impedance combination and not reproducible); if the error rate exceeds the standard, mark the impedance combination as "specific data pattern verification failed". If errors occur in the all 0 / 1 pattern, prioritize checking the stability of the power voltage (such as whether the low level is lower than 0.1V and whether the high level is higher than 0.9V) and impedance matching (such as high resistance combinations are prone to high level attenuation); if errors occur in the staggered 01 pattern, focus on analyzing signal crosstalk (verified through subsequent eye diagram testing); if fixed bit errors occur in the Walking1 / 0 pattern, check the contact resistance and impedance value of the corresponding pin (such as through the pin impedance measurement function of ATE).

[0093] Voltage stress testing should cover "power supply voltage offset" and "dynamic voltage switching" scenarios, with parameter settings referring to the limit range of the JEDEC standard, while also considering extreme cases in actual applications (such as voltage fluctuations in automotive scenarios). For the core power supply (VDD) and I / O power supply (VDDQ) of the memory chip, set three types of voltages: lower than the nominal value, higher than the nominal value, and the nominal value, test the read-write stability under different voltage offsets, with specific parameters as follows (take DDR5 as an example, nominal VDD=1.1V, VDDQ=1.1V): Simulate the rapid change of voltage in actual application (such as mobile phone switching from charging state to battery power supply), set the voltage to dynamically switch between different gears, test the adaptability of impedance combination to voltage mutation, the specific steps are: design the voltage switching sequence as "VDD=0.99V→1.10V→1.21V→1.10V→0.99V", each voltage gear keeps for 5 minutes, and the switching time is ≤100μs (simulate the actual power supply switching speed). During the voltage switching process, the "interleaved 01 mode read-write cycle" is executed synchronously (once every 2 minutes), avoiding executing read-write at the moment of voltage switching (set 10ms before and after switching as "read-write inhibition window", prevent data error caused by voltage mutation). Real-time record the voltage switching time: data error rate (error number within 5 seconds before and after switching, normal should be ≤0); power supply current change (current fluctuation should be ≤±20% during switching, avoid exceeding the maximum rated current of the chip); chip temperature (temperature rise should be ≤5℃ / min during switching process, prevent thermal stress damage).

[0094] Timing stress test is aimed at the key timing parameters of memory chip (such as tRCD, tRP, tWR, tRAS), set timing offset deviating from the nominal value, verify the read-write stability of impedance combination under timing tight or loose conditions, expose the problem of insufficient timing margin caused by impedance mismatch. Take the DDR5 standard timing parameters (nominal tRCD=18ns, tRP=18ns, tWR=12ns, tRAS=36ns) as an example, set "negative offset (timing tight)" "nominal" "positive offset (timing loose)" three types of gears, as follows: Timing pressure test execution process: Through the timing generator of the ATE / SLT platform, set the timing registers of the memory chip according to the above gear setting (such as the MRS3 register of DDR5 controls tRCD, and the MRS4 controls tRP), read the timing state register after configuration, and confirm that the parameters have taken effect (such as the configuration value of tRCD and the read value deviation ≤±0.5ns). First, perform the nominal timing test (10 minutes, full mode read and write), record the baseline error rate (should be 0); switch to negative offset timing, perform 30 minutes of "full mode read and write cycle" (50 cycles per mode), focus on monitoring the CA bus error (such as command address decoding error) under tRCD, tRP negative offset, and the DQ bus error (such as data write error) under tWR, tRAS negative offset; switch to positive offset timing, perform 30 minutes of testing, verify whether there are errors caused by signal retention under timing relaxation (such as positive offset tWR easily leading to write data overlap); during the test, record the actual value of the timing parameter every 5 minutes (measured by a timing analyzer), ensure that the timing offset is stable (the actual value and the set value deviation ≤±0.3ns). After the test is completed, calculate the timing margin of each impedance combination —— take tRCD as an example, margin = (maximum error-free tRCD - minimum error-free tRCD) / 2, the larger the margin, the stronger the timing adaptability of the impedance combination; if the error rate of a certain impedance combination increases sharply under negative offset timing, it means that its timing margin is insufficient and needs to be excluded from the effective combination.

[0095] By measuring the eye diagram of the test signal, the signal quality is quantitatively evaluated (eye height reflects signal amplitude margin, and eye width reflects timing margin), the correlation between impedance combination and signal quality is established, and the effective impedance range screening provides more accuracy. Eye diagram measurement needs to be realized through a high-speed oscilloscope (bandwidth ≥ 3 times the highest frequency of the memory signal, such as DDR5-6400 requires an oscilloscope bandwidth ≥ 19.2GHz) and a special probe (such as a differential probe, input impedance 50Ω, bandwidth ≥ 20GHz), the hardware configuration and parameter setting are as follows: Oscilloscope parameter settings (take DDR5 DQ signal as an example): Vertical settings: range: 500mV / div (cover the 0-1V amplitude range of DDR5 DQ signal); offset: 0V (take signal ground as reference); coupling mode: AC coupling (block DC component, highlight AC signal change). Horizontal settings: time base: 100ps / div (tCK=0.416ns of DDR5-4800, time base setting ensures that at least 5 clock cycles are included in a single acquisition); trigger mode: edge trigger (take the rising edge of WCK clock as trigger source, trigger level 0.5V); acquisition duration: 1ms (ensure enough signal periods are acquired to generate statistically meaningful eye diagrams, usually need to acquire ≥10^6 periods). Eye diagram analysis software settings: eye diagram template: load JEDEC DDR5 eye diagram template (such as the eye diagram template defined in JESD79-5A); measurement parameters: enable automatic measurement of four key parameters: "eye height", "eye width", "eye jitter", and "signal-to-noise ratio"; statistical method: use "cycle average" mode to exclude the influence of abnormal pulses on measurement results.

[0096] Eye height and eye width measurement process: for each impedance combination, measure the eye diagrams of CA signals (command address signals) and DQ signals (data signals) under "normal conditions" (nominal voltage, nominal timing) and "stress conditions" (voltage -10%, timing -10%) respectively. The specific process is as follows: connect the differential probe to the target pin of the memory chip (such as A0-A3 in the CA pin, DQ0-DQ3 in the DQ pin), and ensure that the probe ground is tightly connected to the chip ground (ground wire length ≤10mm, reduce ground loop interference); start the oscilloscope and synchronize the clock source, perform "probe calibration" (use the calibration signal provided by the oscilloscope to ensure that the probe gain error is ≤±2%); configure the memory chip to enter "signal test mode" (disable automatic refresh through MRS register to avoid refresh signal interference with eye diagram acquisition).

[0097] Set the memory power supply to the nominal value (VDD=1.1V, VDDQ=1.1V) and the timing to the nominal value (tRCD=18ns, tRP=18ns); start "all 0 + all 1 mode read-write cycle" (each mode lasts for 10 seconds, alternating); trigger the oscilloscope to acquire CA / DQ signal waveform; the oscilloscope automatically generates an eye diagram, records the values of eye height (V_eye) and eye width (T_eye) - for example, the eye height of DQ signal under all 0 mode is 0.8V, and the eye width is 0.3ns; repeat the acquisition 3 times, take the average value as the eye height / eye width value under normal conditions for this impedance combination, to reduce the influence of random noise.

[0098] Adjust the supply to VDD=0.99V (-10%), timing to tRCD=15ns (-16.7%); perform "interleaved 01 mode read-write cycle" (for 10 seconds), collect CA / DQ signal waveform and generate eye diagram; record eye height / eye width values under stress conditions, calculate the change rate from normal conditions (such as eye height from 0.8V to 0.65V, the change rate is -18.75%); focus on whether the eye diagram under stress conditions appears "closed eye" (eye height <0.2V or eye width <0.1ns), if it appears, mark the impedance combination signal quality as unqualified.

[0099] For CA signals, at least the eye diagrams of A0, A1, A2, A3 four key address pins are measured; for DQ signals, at least the eye diagrams of DQ0, DQ1, DQ2, DQ3 four data pins are measured; calculate the standard deviation of eye height / eye width of the same signal type (such as CA), and the standard deviation ≤5% indicates that the signal quality is uniform under this impedance combination, and there is no obvious difference between pins.

[0100] Practical application of screening bad chips: the direct value of this method is to efficiently screen out chips with abnormal impedance characteristics. Screening defective chips: some chips have manufacturing process deviations, and their internal ODT circuit actual resistance may deviate from the nominal value (for example, set to 60 ohms, the actual resistance may be as high as 100 ohms or as low as 30 ohms). Such chips can only pass a very small number of tests or even no tests. Therefore, they can be quickly screened out because "no stable impedance working point can be found". Compatibility verification: even if a single chip impedance is normal, when it is matched with a specific motherboard (whose PCB trace characteristics are fixed), it needs to be confirmed that there is enough impedance matching margin. This test can verify the reliability of a specific "motherboard + memory" combination.

[0101] This embodiment actively and systematically explores the boundaries of memory interface impedance matching, rather than just verifying a set of nominal values. Through multi-dimensional parameter scanning and functional testing, the safe working area of impedance is accurately defined. It can effectively identify those chips with slight impedance defects that may be missed in simple tests. It ensures that the memory chip has enough impedance matching tolerance under the specific motherboard design and load conditions, thereby ensuring the stability of the system during long-term operation. A large amount of test data can provide valuable reference for the design of ODT circuit and PCB of the next generation of memory interface.

[0102] In several embodiments provided by the present application, it should be understood that the disclosed system, device and method can be implemented in other manners. For example, the division of the units is only a logical function division, and there can be another division manner in actual implementation. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections between the units can be indirect couplings or communication connections through some interfaces, devices or units, and can be in electrical, mechanical or other forms.

[0103] In addition, each function unit in the various embodiments of the present application can be integrated into a processing unit, or each unit can exist physically, or two or more units can be integrated into one unit. The integrated unit can be implemented in the form of hardware or software function unit.

[0104] The above are only some embodiments of the present application, and do not limit the patent scope of the present application. Any equivalent structure or equivalent flow transformation made by using the content of the present application specification and drawings, or directly or indirectly applied to other related technical fields, is also included in the patent protection scope of the present application.

Claims

1. A method of impedance matching test of a memory chip, characterized by, The method comprises: The CA-odt, DQ-odt and SOC-odt dimensions of the memory chip are tested for matching of different impedance values, and different impedance combinations are obtained; Impedance verification is performed on the memory chip according to different impedance combinations; Memory chips outside the range of different impedance combinations are screened, and the memory chips outside the range of different impedance combinations are determined as memory chips with obvious impedance difference, i.e. memory chips with poor impedance matching; Memory chips within the range of different impedance combinations are screened, and impedance combinations that pass all test items are recorded, and the effective working range of different impedance values in each dimension is determined.

2. The impedance matching test method of a memory chip according to claim 1, wherein, The step of testing the CA-odt, DQ-odt and SOC-odt dimensions of the memory chip for matching of different impedance values to obtain different impedance combinations comprises: Test configuration and initialization on an automatic test equipment or a specific system-level test platform; The resistance values of CA-ODT and DQ-ODT are dynamically configured by writing the mode register of the memory chip, and the SOC-ODT value is set by configuring the internal register of the CPU.

3. The impedance matching test method of memory chips as claimed in claim 1, wherein, The step of performing impedance verification on the memory chip according to different impedance combinations comprises: According to the preset order of the test program, all impedance combinations of the CA-ODT, DQ-ODT and SOC-ODT dimensions are traversed; For each impedance combination, a strict read-write test is performed.

4. The impedance matching test method of memory chips as claimed in claim 3, wherein, The step of performing a strict read-write test for each impedance combination comprises: Write a specific data pattern and read back for verification, wherein the specific data pattern at least includes all 0, all 1, staggered 01 and Walking 1 / 0; Pressure is applied on voltage and timing to test the stability of the test signals of the memory chip under non-ideal conditions during the read-write test; The eye height and eye width of the test signals of the memory chip are measured, and the signal quality is quantitatively evaluated.

Images