Storage circuits, memory chips and electronic devices

Abstract

This application provides a storage circuit, a storage chip, and an electronic device. The storage circuit includes a sub-read circuit, read bit lines, at least one read auxiliary unit, and multiple static random access memory (SRAM) cells. The read bit lines are connected to the sub-read circuit, the at least one read auxiliary unit, and the multiple SRAM cells. The sub-read circuit performs read operations through the multiple SRAM cells. The read auxiliary unit is obtained by updating the circuit connections of the SRAM cells and is used to adjust the potential of the read bit lines. This not only improves the success rate of reading 1 operations and accelerates the speed of reading 0 operations, but also avoids excessive area overhead in the storage circuit.

Description

Technical Field

[0001] This application relates to the field of static random access memory technology, and more particularly to a storage circuit, a storage chip, and an electronic device. Background Technology

[0002] Static Random Access Memory (SRAM) is a type of random access memory that can retain its internal data without requiring a refresh circuit. It has high performance and can be widely used in the production process of chips and electronic devices.

[0003] Figure 1 This is a schematic diagram of an SRAM storage circuit in the prior art. Please refer to [link / reference]. Figure 1 The storage circuit includes a sub-read circuit, read bit lines RBL, and multiple SRAM cells. The read bit lines RBL are connected to both the sub-read circuit and the multiple SRAM cells; the sub-read circuit can be used to perform read operations through the multiple SRAM cells. Figure 1 In a given SRAM cell, when a 1 is stored and a 1 needs to be read from that SRAM cell, the read bit line RBL must be kept at a high potential. However, multiple SRAM cells connected to the read bit line may store 0s, and the read port circuits of these SRAM cells storing 0s will generate leakage current. When there are enough SRAM cells storing 0s, the cumulative leakage current will cause the read bit line RBL to gradually drop from a high potential to an intermediate potential, thus causing the sub-read circuit to fail when reading a 1 from an SRAM cell storing 1s.

[0004] In related technologies, the stability of read-1 operations can be improved by adding auxiliary circuitry outside the storage circuit to keep the read bit line consistently at a high potential. For example, multiple N-metal-oxide-semiconductor (NMOS) transistors can be connected in series in the storage circuit to reduce leakage current and thus stabilize the read bit line at a high potential. However, in this process, as the auxiliary circuitry is added, the driving capability of the storage circuitry weakens. Although this improves the stability of read-1 operations, it slows down read-0 operations. Furthermore, the increase in auxiliary units leads to an increase in edge units, resulting in excessive area overhead for the storage circuitry. Summary of the Invention

[0005] This application provides a storage circuit, a storage chip, and an electronic device. By setting a read auxiliary unit, the potential of the read bit line can be adjusted, improving the success rate of read 1 operations and accelerating the speed of read 0 operations. Furthermore, the read auxiliary unit is obtained by updating the circuit connection relationship of SRAM cells. The read auxiliary unit is compatible with the SRAM layout rules, eliminating the need to insert edge cells between the read auxiliary unit and the SRAM cells, thus avoiding excessive area overhead of the storage circuit.

[0006] In a first aspect, embodiments of this application provide a storage circuit, including a sub-readout circuit, read bit lines, at least one read auxiliary unit, and a plurality of static random access memory (SRAM) cells, wherein...

[0007] The read bit lines are respectively connected to the sub-readout circuit, the at least one read auxiliary unit, and the plurality of SRAM units;

[0008] The sub-readout circuit is used to perform read operations through the plurality of SRAM cells;

[0009] The read assist unit is obtained by updating the circuit connection relationship of the SRAM cell, and the read assist unit is used to adjust the potential of the read bit line.

[0010] In one possible implementation, the read assist unit is used to pull up the potential of the read bit line, or the read assist unit is used to pull down the potential of the read bit line.

[0011] In one possible implementation, the read auxiliary unit is used to pull up the potential of the read bit line; the read auxiliary unit includes a first unit, the first unit including a first switch unit and a second switch unit, wherein...

[0012] The first switching unit and the second switching unit are connected in series;

[0013] The first switch unit is connected to the read bit line, and the first switch unit is also used to connect to the read character line;

[0014] The second switching unit is also used to connect to the word reading line and the first power supply, the voltage provided by the first power supply being greater than 0.

[0015] In one possible implementation, the first switching unit is a first NMOS transistor, and the second switching unit is a second NMOS transistor, wherein...

[0016] The gate of the first NMOS transistor is connected to the read word line, the source of the first NMOS transistor is connected to the read bit line, and the drain of the first NMOS transistor is connected to the drain of the second NMOS transistor.

[0017] The gate of the second NMOS transistor is used to connect to the read word line, and the source of the second NMOS transistor is used to connect to the first power supply.

[0018] In one possible implementation, the read assistance unit further includes a second unit, wherein the second unit includes a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a first PMOS transistor, and a second PMOS transistor, wherein...

[0019] The source terminals of the first PMOS transistor and the second PMOS transistor are respectively connected to the second power supply.

[0020] The gate of the first PMOS transistor, the gate of the third NMOS transistor, the drain of the second PMOS transistor, the drain of the fourth NMOS transistor, and the drain of the fifth NMOS transistor are connected.

[0021] The drain of the first PMOS transistor, the drain of the third NMOS transistor, and the drain of the sixth NMOS transistor are connected.

[0022] The source of the sixth NMOS transistor is used to connect to the first write bit line, and the gate of the sixth NMOS transistor is used to connect to the third power supply.

[0023] The gate of the second PMOS transistor, the gate of the fourth NMOS transistor, the drain of the first PMOS transistor, the drain of the third NMOS transistor, and the drain of the sixth NMOS transistor are connected.

[0024] The gate of the fifth NMOS transistor is used to connect to the third power supply, and the source of the fifth NMOS transistor is used to connect to the second write bit line.

[0025] The source terminals of the third NMOS transistor and the fourth NMOS transistor are respectively connected to the third power supply.

[0026] In one possible implementation, the read auxiliary unit is used to pull down the potential of the read bit line; the read auxiliary unit includes a first unit and a second unit, the first unit including a first switch unit and a second switch unit, wherein...

[0027] The first switching unit and the second switching unit are connected in series;

[0028] The first switch unit is connected to the read bit line, and the first switch unit is also used to connect to the read word line, or the first switch unit is also used to connect to the second unit;

[0029] The second switching unit is also used to connect to the second unit and the third power supply, respectively.

[0030] In one possible implementation, the first switching unit is further configured to connect to a read word line; the first switching unit is a first NMOS transistor, and the second switching unit is a second NMOS transistor, wherein...

[0031] The gate of the first NMOS transistor is connected to the read word line, the source of the first NMOS transistor is connected to the read bit line, and the drain of the first NMOS transistor is connected to the drain of the second NMOS transistor.

[0032] The gate of the second NMOS transistor is used to connect to the second cell, and the source of the second NMOS transistor is used to connect to the third power supply.

[0033] In one possible implementation, the first switching unit is further configured to connect to the second unit; the first switching unit is a first NMOS transistor, and the second switching unit is a second NMOS transistor, wherein...

[0034] The gate of the first NMOS transistor is connected to the gate of the second NMOS transistor and the second cell, respectively; the source of the first NMOS transistor is connected to the read bit line; and the drain of the first NMOS transistor is connected to the drain of the second NMOS transistor.

[0035] The gate of the second NMOS transistor is used to connect to the second cell, and the source of the second NMOS transistor is used to connect to the third power supply.

[0036] In one possible implementation, the second unit includes a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a first PMOS transistor, and a second PMOS transistor, wherein...

[0037] The source terminals of the first PMOS transistor and the second PMOS transistor are respectively connected to the second power supply.

[0038] The gate of the first PMOS transistor, the gate of the third NMOS transistor, the drain of the second PMOS transistor, the drain of the fourth NMOS transistor, the drain of the fifth NMOS transistor, and the gate of the second NMOS transistor are connected.

[0039] The drain of the first PMOS transistor, the drain of the third NMOS transistor, and the drain of the sixth NMOS transistor are connected.

[0040] The source of the sixth NMOS transistor is used to connect to the first write bit line, and the gate of the sixth NMOS transistor is used to connect to the third power supply.

[0041] The gates of the second PMOS transistor and the fourth NMOS transistor are respectively connected to the read bit line;

[0042] The gate of the fifth NMOS transistor is used to connect to the third power supply, and the source of the fifth NMOS transistor is used to connect to the second write bit line.

[0043] The source terminals of the third NMOS transistor and the fourth NMOS transistor are respectively connected to the third power supply.

[0044] In one possible implementation, the storage circuit further includes a first edge unit and a second edge unit corresponding to the sub-readout circuit, wherein,

[0045] The first edge unit is connected to the sub-read circuit, and the first edge unit is used to isolate the sub-read circuit from the SRAM cells adjacent to the sub-read circuit;

[0046] The second edge unit is connected to the SRAM cell disposed at the edge of the storage circuit.

[0047] In one possible implementation, the number of the at least one read assist unit is 1.

[0048] Secondly, embodiments of this application provide a memory chip, which includes the memory circuit described in the first aspect.

[0049] Thirdly, embodiments of this application provide an electronic device, which includes a memory chip as described in the second aspect.

[0050] The storage circuit, storage chip, and electronic device provided in this application include a sub-read circuit, read bit lines, at least one read auxiliary unit, and multiple SRAM cells. The read bit lines are connected to the sub-read unit, at least one read auxiliary unit, and multiple SRAM cells. The sub-read circuit performs read operations through the multiple SRAM cells. The read auxiliary unit is obtained by updating the circuit connections of the SRAM cells and is used to adjust the potential of the read bit lines. In the above storage circuit, when a read 1 operation is required in an SRAM cell, the potential of the read bit lines is pulled up by the read auxiliary unit. This avoids the read bit lines being pulled down too low by other SRAM cells storing 0 connected to the read bit lines, thus improving the success rate of the read 1 operation. When a read 0 operation is required in an SRAM cell, the potential of the read bit lines is pulled down by the read auxiliary unit, which speeds up the pull-down of the read bit line potential, thereby speeding up the read 0 operation. Furthermore, the read auxiliary unit is obtained by updating the circuit connection relationship of the SRAM cell. The read auxiliary unit is compatible with the SRAM layout rules, and there is no need to insert edge cells between the read auxiliary unit and the SRAM cell, thus avoiding excessive area overhead of the storage circuit. Attached Figure Description

[0051] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0052] Figure 1 This is a schematic diagram of an SRAM storage circuit in the prior art;

[0053] Figure 2 A schematic diagram of a storage circuit provided in an embodiment of this application;

[0054] Figure 3 A schematic diagram of the structure of a standard SRAM cell provided in an embodiment of this application;

[0055] Figure 4 This is a schematic diagram of the structure of a read assistance unit provided in an embodiment of this application;

[0056] Figure 5 A schematic diagram comparing the waveforms of a conventional SRAM storage circuit provided in the embodiments of this application and the SRAM storage circuit proposed in this application during the read process;

[0057] Figure 6 A schematic diagram of another read auxiliary unit provided in an embodiment of this application;

[0058] Figure 7 Another schematic diagram of another structure of a read auxiliary unit provided in an embodiment of this application;

[0059] Figure 8 A schematic diagram comparing the waveforms of a conventional SRAM storage circuit provided in the embodiments of this application and the SRAM storage circuit proposed in this application during the read-0 process;

[0060] Figure 9 A memory circuit structure diagram of a memory chip provided in an embodiment of this application;

[0061] Figure 10A This is a schematic diagram of the layout architecture of a traditional SRAM memory chip with multiple readout circuitry.

[0062] Figure 10B This is a schematic diagram of the layout architecture of the SRAM memory chip proposed in this application;

[0063] Figure 11 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0064] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0065] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0066] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0067] In related technologies, the stability of read-1 operations can be improved by adding auxiliary circuitry outside the storage circuit to keep the read bit line at a stable high potential. For example, multiple NMOS transistors can be connected in series with the storage circuit to reduce leakage current and thus stabilize the read bit line at a high potential. However, in the above process, as the auxiliary circuitry is added, the driving capability of the storage circuitry weakens. Although this can improve the stability of read-1 operations, it slows down the speed of read-0 operations. Furthermore, the increase in auxiliary units will lead to an increase in edge units, resulting in excessive area overhead for the storage circuitry.

[0068] This application provides a storage circuit including a sub-read circuit, read bit lines, at least one read auxiliary unit, and multiple static random access memory (SRAM) cells. The read bit lines are connected to the sub-read unit, at least one read auxiliary unit, and multiple SRAM cells, respectively. The sub-read circuit is used to perform read operations through multiple SRAM cells. The read auxiliary unit is obtained by updating the circuit connection relationship of the SRAM cells and is used to adjust the potential of the read bit lines.

[0069] In the aforementioned storage circuit, the read auxiliary unit can adjust the potential of the read bit line. Specifically, the read auxiliary unit is used to pull up or pull down the potential of the read bit line. When performing a read 1 operation in the SRAM cell, pulling up the potential of the read bit line through the read auxiliary unit can prevent the potential of the read bit line from being pulled down too low by other SRAM cells storing 0 connected to the read bit line, thus improving the success rate of the read 1 operation. When performing a read 0 operation in the SRAM cell, pulling down the potential of the read bit line through the read auxiliary unit can speed up the pull-down speed of the read bit line potential, thereby speeding up the read 0 operation. Furthermore, the read auxiliary unit is obtained by updating the circuit connection relationship of the SRAM cell, and the read auxiliary unit is compatible with the SRAM layout rules. There is no need to insert edge cells between the read auxiliary unit and the SRAM cell, avoiding excessive area overhead of the storage circuit.

[0070] It should be noted that the storage circuit provided in this application embodiment can be applied not only to the field of static random access memory technology, but also to the fields of chip and electronic device manufacturing.

[0071] The storage circuit shown in this application will now be described through specific embodiments. It should be noted that the following embodiments may exist independently or in combination with each other; identical or similar content will not be repeated in different embodiments.

[0072] Figure 2 This is a schematic diagram of a storage circuit provided in an embodiment of this application. Please refer to [link / reference]. Figure 2 The storage circuit may include: a sub-read circuit, a read bit line RBL, at least one read auxiliary unit, and multiple static random access memory (SRAM) cells.

[0073] like Figure 2 As shown, the read bit line RBL is connected to a sub-read circuit, at least one auxiliary unit, and multiple SRAM cells. The sub-read circuit can be used to perform read operations through multiple SRAM cells. The read auxiliary unit is obtained by updating the circuit connection relationship of the SRAM cells, and is used to adjust the potential of the read bit line RBL. Optionally, the number of at least one read auxiliary unit is one.

[0074] Optionally, the storage circuit may further include a first edge unit and a second edge unit corresponding to the sub-read circuit. The first edge unit is connected to the sub-read circuit and is used to isolate the sub-read circuit from adjacent SRAM cells; the second edge unit is connected to SRAM cells disposed at the edge of the storage circuit.

[0075] Below, in conjunction with Figure 3 The structure of any one of the SRAM cells mentioned above will be introduced.

[0076] Figure 3 This is a schematic diagram of a standard SRAM cell provided in an embodiment of this application. Please refer to... Figure 3 The SRAM cell is an 8T-SRAM cell, which includes 6 NMOS transistors (NM1 to NM6) and 2 PMOS transistors (PM1 and PM2).

[0077] like Figure 3 As shown, this 8T-SRAM cell is a two-port SRAM cell with independent read and write port circuits, enabling simultaneous reading and writing. The read port circuit includes NMOS transistors NM5 and NM6, used to read signal 1 or signal 0. The write port circuit includes NMOS transistors NM1-NM4 and PMOS transistors PM1 and PM2, used to write signal 1 or signal 0. NMOS transistors NM1 and PM1 form an inverter, and NMOS transistors NM2 and PM2 form another inverter; these two inverters together form a latch for storing data.

[0078] The drains of PMOS transistor PM1, NMOS transistor NM1, and NMOS transistor NM4 intersect at node Q, and the drains of PMOS transistor PM2, NMOS transistor NM2, and NMOS transistor NM3 intersect at node Qb. If the voltage at node Q is high and the voltage at node Qb is low, the SRAM cell stores a value of 1; if the voltage at node Q is low and the voltage at node Qb is high, the SRAM cell stores a value of 0.

[0079] This application proposes a read auxiliary unit. By setting this read auxiliary unit to pull up the potential of the read bit line, when the sub-read circuit performs a read 1 operation in the SRAM cell, it can avoid the read bit line potential being pulled down too low by other SRAM cells storing 0 connected to the read bit line, thereby improving the success rate of the read 1 operation. Below, in conjunction with... Figures 4-5 The reading auxiliary unit will be described in detail.

[0080] Figure 4 This is a schematic diagram of a read assistance unit provided in an embodiment of this application. Please refer to [link / reference]. Figure 4 This read-aid unit is achieved through... Figure 3 The circuit connections of the standard SRAM cells shown are updated to obtain the potential for pulling up the read bit lines. This read auxiliary unit includes a first unit and a second unit, wherein:

[0081] The first unit may include a first switch unit and a second switch unit, which are connected in series. The first switch unit is connected to the read bit line and is also used to connect to the read character line; the second switch unit is also used to connect to the read character line and a first power supply, the voltage provided by the first power supply being greater than 0.

[0082] The first switching unit is a first NMOS transistor, and the second switching unit is a second NMOS transistor. Figure 4 In the diagram, the first NMOS transistor is NMOS transistor NM6, and the second NMOS transistor is NMOS transistor NM5.

[0083] As can be seen, the gate of the first NMOS transistor NM6 is connected to the read word line RWL, the source of the first NMOS transistor NM6 is connected to the read bit line RBL, and the drain of the first NMOS transistor NM6 is connected to the drain of the second NMOS transistor NM5. The gate of the second NMOS transistor NM5 is connected to the read word line RWL, and the source of the second NMOS transistor NM5 is connected to the first power supply VRBL.

[0084] Optionally, the voltage provided by the first power supply VRBL can be a preset voltage. For example, the preset voltage can be the operating voltage VDD of the SRAM cell, or the operating voltage of the external read circuit of the SRAM cell.

[0085] The second unit may include a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a first PMOS transistor, and a second PMOS transistor. Figure 4 In the diagram, the third NMOS transistor is NMOS transistor NM1, the fourth NMOS transistor is NMOS transistor NM2, the fifth NMOS transistor is NMOS transistor NM3, the sixth NMOS transistor is NMOS transistor NM4, the first PMOS transistor is PMOS transistor PM1, and the second PMOS transistor is PMOS transistor PM2.

[0086] The source of the first PMOS transistor PM1 and the source of the second PMOS transistor PM2 are respectively connected to the second power supply VDD. The second power supply VDD can be the operating voltage of the SRAM cell.

[0087] The gate of the first PMOS transistor PM1, the gate of the third NMOS transistor NM1, the drain of the second PMOS transistor PM2, the drain of the fourth NMOS transistor NM2, and the drain of the fifth NMOS transistor NM3 are connected.

[0088] The drain of the first PMOS transistor PM1, the drain of the third NMOS transistor NM1, and the drain of the sixth NMOS transistor NM4 are connected; the source of the sixth NMOS transistor NM4 is connected to the first write bit line BL, and the gate of the sixth NMOS transistor NM4 is connected to the third power supply VSS. The third power supply VSS is grounded.

[0089] The gates of the second PMOS transistor PM2 and the fourth NMOS transistor NM2 are connected to the read bit line RBL, respectively.

[0090] The gate of the fifth NMOS transistor NM3 is connected to the third power supply VSS, and the source of the fifth NMOS transistor NM3 is connected to the second write bit line BLB.

[0091] The source terminals of the third NMOS transistor NM1 and the fourth NMOS transistor NM2 are connected to the third power supply VSS.

[0092] The following is a brief explanation of the process by which the sub-read circuit performs read operations through the SRAM cell.

[0093] Case 1: Read 0 from SRAM cell.

[0094] When reading 0 through an SRAM cell that is currently 0, the read word line RWL is charged to a high potential, causing the gate of NMOS transistor NM6 to be high and turning on. At the same time, the voltage at node Qb is high, causing the gate of NMOS transistor NM5 to be high and turning on as well. Since both NMOS transistors NM5 and NM6 are on, a loop is formed consisting of the read word line RBL, NMOS transistors NM5 and NM6, and the power supply VSS. This loop generates leakage current flowing from the read word line RBL to the power supply VSS, pulling down the potential of the read word line RBL until it reaches a low potential, thus reading 0.

[0095] Case 2: Read 1 through SRAM cell.

[0096] When a 1 is read from an SRAM cell that is currently stored as 1, the read word line RWL is charged to a high potential, causing the gate of NMOS transistor NM6 to be high and turning on. At the same time, the voltage at node Qb is low, causing the gate of NMOS transistor NM5 to be low and turning off. Because NMOS transistor NM5 is off and NMOS transistor NM6 is on, a loop consisting of the read bit line RBL, NMOS transistors NM5 and NM6, and the power supply VSS is not formed, preventing the potential of the read bit line RBL from being pulled down.

[0097] However, during the process of reading 1 from SRAM, other SRAM cells that are stored as 0 and connected to the read bit line RBL will generate leakage current, causing the potential of the read bit line RBL to be pulled down.

[0098] When the read word line RWL is high, the gates of the first NMOS transistor NM6 and the second NMOS transistor NM5 in the read auxiliary unit are both high, meaning both NMOS transistors NM6 and NM5 are turned on. At this time, the read bit line RBL, the first NMOS transistor NM6 and the second NMOS transistor NM5 in the read auxiliary unit, and the first power supply VRBL can form a loop. This loop generates a pull-up current flowing from the first power supply VRBL to the read bit line RBL. This pull-up current can be used to pull up the potential of the read bit line RBL, mitigating the potential drop caused by other SRAM cells storing 0. By using the pull-up current generated by the read auxiliary unit to compensate for the leakage current generated by other SRAM cells storing 0, the read bit line RBL can be stabilized at a high potential, ultimately achieving a stable read of 1.

[0099] The storage circuit provided in this application includes a sub-read circuit, read bit lines, at least one read auxiliary unit, and multiple static random access memory (SRAM) cells. The read bit lines are connected to the sub-read unit, the at least one read auxiliary unit, and the multiple SRAM cells. The sub-read circuit performs read operations through the multiple SRAM cells. The read auxiliary unit is obtained by updating the circuit connections of the SRAM cells and is used to adjust the potential of the read bit lines. In this storage circuit, since the read auxiliary unit can be used to pull up the potential of the read bit lines, when performing a read 1 operation in the SRAM cells, it can avoid the read bit lines being pulled down too low by other SRAM cells storing 0 connected to them, thus improving the success rate of the read 1 operation.

[0100] Below, in conjunction with Figure 5 For the read process, the waveforms of the traditional SRAM storage circuit and the SRAM storage circuit proposed in the embodiments of this application are compared and analyzed.

[0101] Figure 5 A schematic diagram comparing the waveforms of a conventional SRAM storage circuit and the SRAM storage circuit proposed in this application during the read process.

[0102] Please see Figure 5 For traditional SRAM storage circuits, when performing a read 1 operation in an SRAM cell, when the read word line RWL reaches a high potential at time T1, multiple other SRAM cells connected to the read bit line that are storing 0 will generate leakage current, causing the potential of the read bit line RBL to be pulled down, thus causing the read 1 operation to fail.

[0103] The SRAM storage circuit provided in this application embodiment can prevent the potential of the read bit line from being pulled down too low due to other SRAM cells storing 0 connected to the read bit line during the read 1 operation. This allows the read bit line RBL to be kept at a stable high potential, thus improving the success rate of the read 1 operation.

[0104] Below, in conjunction with Figures 6-8 This application proposes another read auxiliary unit, which can be used to pull down the potential of the read bit line, thereby accelerating the speed at which the read bit line potential drops, thus speeding up the sub-read circuit to perform read 0 operation in the SRAM cell and effectively saving the time of read 0 operation.

[0105] Figure 6 This is a schematic diagram of another read assistance unit provided in an embodiment of this application. Please refer to... Figure 6 This read-aid unit is achieved through... Figure 3 The circuit connection relationship of the standard SRAM cell shown is updated, and the read auxiliary unit can be used to pull down the potential of the read bit line.

[0106] The read auxiliary unit includes a first unit and a second unit. The first unit includes a first switch unit and a second switch unit, which are connected in series. The first switch unit is connected to the read bit line RBL and is also used to connect to the read word line RWL. The second switch unit is also used to connect to the second unit and a third power supply.

[0107] exist Figure 6 In this configuration, the first switching unit is a first NMOS transistor NM6, and the second switching unit is a second NMOS transistor NM5. The gate of the first NMOS transistor NM6 is connected to the read word line RWL, the source of the first NMOS transistor NM6 is connected to the read bit line RBL, and the drain of the first NMOS transistor NM6 is connected to the drain of the second NMOS transistor NM5. The gate of the second NMOS transistor NM5 is connected to the second unit, and the source of the second NMOS transistor NM5 is connected to the third power supply.

[0108] The second unit may include a third NMOS transistor NM1, a fourth NMOS transistor NM2, a fifth NMOS transistor NM3, a sixth NMOS transistor NM4, a first PMOS transistor PM1, and a second PMOS transistor PM2.

[0109] in:

[0110] The source of the first PMOS transistor PM1 and the source of the second PMOS transistor PM2 are respectively connected to the second power supply VDD.

[0111] The gate of the first PMOS transistor PM1, the gate of the third NMOS transistor NM1, the drain of the second PMOS transistor PM2, the drain of the fourth NMOS transistor NM2, the drain of the fifth NMOS transistor NM3, and the gate of the second NMOS transistor NM5 are connected.

[0112] The drain of the first PMOS transistor PM1, the drain of the third NMOS transistor NM1, and the drain of the sixth NMOS transistor NM4 are connected; the source of the sixth NMOS transistor NM4 is used to connect to the first write bit line BL, and the gate of the sixth NMOS transistor is used to connect to the third power supply VSS.

[0113] The gates of the second PMOS transistor PM2 and the fourth NMOS transistor NM2 are connected to the read bit line RBL, respectively.

[0114] The gate of the fifth NMOS transistor NM3 is connected to the third power supply VSS, and the source of the fifth NMOS transistor NM3 is connected to the second write bit line BLB.

[0115] The source terminals of the third NMOS transistor NM1 and the fourth NMOS transistor NM2 are connected to the third power supply VSS.

[0116] exist Figure 6 Based on this, below, combined with Figure 7 This application may also propose another structure for another read auxiliary unit.

[0117] Figure 7 This is a schematic diagram of another structure of a read assistance unit provided in an embodiment of this application. Please refer to... Figure 7 This read auxiliary unit can, through the... Figure 6 The connection relationship of the read auxiliary unit in the embodiment is updated to obtain the result. It can be seen that, compared to... Figure 6 The read auxiliary unit proposed in the embodiment has been updated in the following way: the gate of the first NMOS transistor NM6 is disconnected from the read word line RWL, and the gate of the first NMOS transistor NM6 is connected to the gate of the second NMOS transistor NM5 and the second unit respectively.

[0118] When a read 0 operation is performed, the gate of the second NMOS transistor NM5 is at a high potential, and the gate of the first NMOS transistor NM6 is also at a high potential. The second NMOS transistor NM5 and the first NMOS transistor NM6 are turned on, and the potential of the read bit line RBL can be pulled down through the series circuit between the first NMOS transistor NM6 and the second NMOS transistor NM5, thereby accelerating the speed at which the potential of the read bit line RBL is pulled down during the read 0 operation.

[0119] As you can see, Figure 7 The read assistance unit provided in the embodiment is compared to Figure 6The read auxiliary unit proposed in this embodiment is simpler to control. During the read 0 operation, the read auxiliary unit does not need to be connected to the read word line RWL. When the second NMOS transistor NM5 is turned on, the first NMOS transistor NM6 is also turned on, which can accelerate the pull-down speed of the read bit line RBL, thereby speeding up the read 0 operation.

[0120] The storage circuit provided in this application includes a sub-read circuit, read bit lines, at least one read auxiliary unit, and multiple static random access memory (SRAM) cells. The read bit lines are connected to the sub-read unit, the at least one read auxiliary unit, and the multiple SRAM cells. The sub-read circuit performs read operations through the multiple SRAM cells. The read auxiliary unit is obtained by updating the circuit connections of the SRAM cells and is used to adjust the potential of the read bit lines. In this storage circuit, since the read auxiliary unit can be used to pull down the potential of the read bit lines, the pull-down speed of the read bit line potential can be accelerated when performing a read 0 operation in the SRAM cells, thereby speeding up the read 0 operation and effectively saving the read 0 operation time.

[0121] Below, in conjunction with Figure 8 For the read 0 operation, the waveforms of the traditional SRAM storage circuit and the SRAM storage circuit proposed in the embodiments of this application are compared and analyzed.

[0122] Figure 8 A waveform comparison diagram showing the traditional SRAM storage circuit provided in the embodiments of this application and the SRAM storage circuit proposed in this application during the read-zero process. Please refer to... Figure 8 At time T1, the read word line RWL is turned on. When reading 0 through an SRAM cell that is currently 0, since the Qb node is 1, the first NMOS transistor NM6 and the second NMOS transistor NM5 are turned on, and the potential of the read bit line RBL is pulled down. At this time, since the read bit line RBL is still at a high potential, the fourth NMOS transistor NM2 in the read auxiliary cell is turned on and the second PMOS transistor PM2 is turned off, making the Qb node 0, which in turn causes the second NMOS transistor NM5 to turn off. Since the gate of the first NMOS transistor NM6 is connected to the read word line RWL at a high level, the first NMOS transistor NM6 is turned on. Therefore, the series path formed by the first NMOS transistor NM6 and the second NMOS transistor NM5 will not pull down the potential of the read bit line RBL.

[0123] At time T2, it can be seen that the potential of the read bit line RBL is pulled down to the middle state, the fourth NMOS transistor NM2 in the read auxiliary unit starts to turn off and the second PMOS transistor PM2 starts to turn on, so the potential of the Qb node starts to be pulled up.

[0124] At time T3, the potential of node Qb is pulled up to a high potential. At this time, the first NMOS transistor NM6 and the second NMOS transistor NM5 in the read auxiliary unit are turned on. Then, the series circuit formed by the first NMOS transistor NM6 and the second NMOS transistor NM5 pulls down the potential of the read bit line RBL.

[0125] Depend on Figure 8 As can be seen, between time T1 and time T3, only the first NMOS transistor NM6 and the second NMOS transistor NM5 of the SRAM cell storing 0 pull down the potential of the read bit line RBL; while after time T3, the first NMOS transistor NM6 and the second NMOS transistor NM5 in the read auxiliary cell also pull down the potential of the read bit line RBL, which speeds up the pull-down speed of the read bit line RBL, thereby speeding up the read 0 operation.

[0126] The storage circuit provided in this application embodiment can accelerate the pull-down speed of the read bit line potential by using the read auxiliary unit to pull down the potential of the read bit line when performing a read 0 operation in the SRAM cell, thereby speeding up the read 0 operation and effectively saving the read 0 operation time.

[0127] Based on the above embodiments, this application embodiment can also provide a memory circuit structure diagram of a memory chip.

[0128] Figure 9 This is a memory circuit structure diagram of a memory chip provided in an embodiment of this application. Please refer to... Figure 9 The memory chip 10 is provided with a memory circuit, which includes a sub-read circuit, a read bit line RBL, multiple SRAM arrays, multiple read auxiliary cell rows, multiple first edge cells corresponding to the sub-read circuits, and multiple second edge cells.

[0129] An SRAM array may include multiple SRAM cells, and the structure of the SRAM cells may be as follows: Figure 3 The SRAM cell structure shown in the embodiment.

[0130] A row of read auxiliary units may include multiple read auxiliary units, and the structure of the read auxiliary unit can be any of the read auxiliary unit structures shown in the above embodiments.

[0131] The first edge unit is connected to the sub-read circuit and can be used to isolate the sub-read circuit from adjacent SRAM arrays. The second edge unit is connected to the SRAM array located at the edge of the storage circuit.

[0132] For traditional SRAM memory chips, the stability of read-1 operations or the speed of read-0 operations is typically improved by reducing the number of SRAM arrays connected to a set of sub-read circuits. When there are many SRAM arrays, multiple sets of sub-read circuits are needed to separate these SRAM arrays. However, in SRAM memory chip layout design, a first edge cell is usually added between the SRAM array and the sub-read circuits. In a layout design with multiple sub-read circuits, the number of first edge cells in the SRAM memory chip will increase, resulting in an increase in the area overhead of the first edge cells, and consequently, an increase in the area overhead of the SRAM memory chip.

[0133] The SRAM memory chip proposed in this application can improve the stability of read 1 operations or speed up read 0 operations by adjusting the potential of the read bit lines through the addition of read auxiliary units. Therefore, a set of sub-read circuits can connect to more SRAM arrays. Furthermore, the read auxiliary units proposed in this application are obtained by updating the circuit connection relationship of SRAM cells, and are compatible with SRAM layout rules, eliminating the need to insert edge cells between the read auxiliary units and SRAM cells. Thus, for the same capacity SRAM array, the SRAM memory chip proposed in this application can reduce the number of sub-read circuits and first edge cells compared to traditional SRAM memory chips, thereby avoiding excessive area overhead in the SRAM memory chip.

[0134] Below, in conjunction with Figure 10A and Figure 10B The layout architecture of a traditional SRAM memory chip with multiple readout circuits is compared and analyzed with the layout architecture of the SRAM memory chip proposed in the embodiments of this application.

[0135] Figure 10A This is a schematic diagram of the layout architecture of a traditional multiple-subject readout (MSR) memory chip. Please refer to [link / reference]. Figure 10A In the layout architecture of this traditional SRAM memory chip with multiple readout circuits, there are 4 SRAM arrays, 2 sets of readout circuits, 2 sets of second edge cells and 4 sets of first edge cells.

[0136] Figure 10B This is a schematic diagram of the layout architecture of the SRAM memory chip proposed in this application. Please refer to... Figure 10BThe layout architecture of the SRAM memory chip proposed in this application includes four SRAM arrays, one set of sub-read circuits, two sets of read auxiliary cell rows, two sets of second edge cells, and two sets of first edge cells. Since the read auxiliary cells proposed in this application are obtained by modifying some connection relationships of standard SRAM cells, the layout architecture design of the SRAM memory chip still meets the specific layout design rules of traditional SRAM memory chips. That is, the read auxiliary cells and standard SRAM cells can be placed adjacent to each other, while the sub-read circuits need to be isolated from adjacent standard SRAM cells through the first edge cells.

[0137] By comparison Figure 10A and Figure 10B As can be seen, the SRAM memory chip proposed in this application has the same number of SRAM arrays as the traditional SRAM memory chip with multiple sub-read circuits, meaning that the two SRAM memory chips have the same capacity. However, compared to the traditional SRAM memory chip with multiple sub-read circuits, the SRAM memory chip proposed in this application reduces one set of sub-read circuits and two sets of first edge cells, and increases two sets of read auxiliary cell rows. Since the height of the read auxiliary cell rows is usually smaller than the height of the sub-read circuits or first edge cells in the layout architecture, the SRAM memory chip proposed in this application has a smaller height compared to the traditional SRAM memory chip with multiple sub-read circuits, thereby avoiding excessive area overhead of the memory chip.

[0138] Figure 11 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Please refer to... Figure 11 The electronic device 20 is equipped with a memory chip, which is... Figure 9 The memory chip provided in the embodiments has a similar implementation principle and beneficial effects, and will not be described again here.

[0139] It is understood that the various numerical designations used in the embodiments of this application are merely for descriptive convenience and are not intended to limit the scope of the embodiments of this application.

[0140] It should also be noted that the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. In this application, "multiple" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0141] The above description is merely an embodiment of this application and is not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A storage circuit, characterized in that, It includes a sub-readout circuit, read bit lines, at least one read auxiliary unit, and multiple static random access memory (SRAM) cells, wherein, The read bit lines are respectively connected to the sub-readout circuit, the at least one read auxiliary unit, and the plurality of SRAM units; The sub-readout circuit is used to perform read operations through the plurality of SRAM cells; The read assist unit is obtained by updating the circuit connection relationship of the SRAM cell, and the read assist unit is used to adjust the potential of the read bit line; The read auxiliary unit is used to pull up the potential of the read bit line; the read auxiliary unit includes a first unit, which includes a first switch unit and a second switch unit, wherein... The first switching unit and the second switching unit are connected in series; The first switch unit is connected to the read bit line, and the first switch unit is also used to connect to the read character line; The second switching unit is also used to connect to the word reading line and the first power supply, the voltage provided by the first power supply being greater than 0.

2. The circuit according to claim 1, characterized in that, The first switching unit is a first NMOS transistor, and the second switching unit is a second NMOS transistor, wherein... The gate of the first NMOS transistor is connected to the read word line, the source of the first NMOS transistor is connected to the read bit line, and the drain of the first NMOS transistor is connected to the drain of the second NMOS transistor. The gate of the second NMOS transistor is used to connect to the read word line, and the source of the second NMOS transistor is used to connect to the first power supply.

3. The circuit according to claim 1 or 2, characterized in that, The read assistance unit further includes a second unit, wherein the second unit includes a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a first PMOS transistor, and a second PMOS transistor, wherein... The source terminals of the first PMOS transistor and the second PMOS transistor are respectively connected to the second power supply. The gate of the first PMOS transistor, the gate of the third NMOS transistor, the drain of the second PMOS transistor, the drain of the fourth NMOS transistor, and the drain of the fifth NMOS transistor are connected. The drain of the first PMOS transistor, the drain of the third NMOS transistor, and the drain of the sixth NMOS transistor are connected. The source of the sixth NMOS transistor is used to connect to the first write bit line, and the gate of the sixth NMOS transistor is used to connect to the third power supply. The gate of the second PMOS transistor, the gate of the fourth NMOS transistor, the drain of the first PMOS transistor, the drain of the third NMOS transistor, and the drain of the sixth NMOS transistor are connected. The gate of the fifth NMOS transistor is used to connect to the third power supply, and the source of the fifth NMOS transistor is used to connect to the second write bit line. The source terminals of the third NMOS transistor and the fourth NMOS transistor are respectively connected to the third power supply.

4. The circuit according to claim 1, characterized in that, The storage circuit further includes a first edge unit and a second edge unit corresponding to the sub-readout circuit, wherein, The first edge unit is connected to the sub-read circuit, and the first edge unit is used to isolate the sub-read circuit from the SRAM cells adjacent to the sub-read circuit; The second edge unit is connected to the SRAM cell disposed at the edge of the storage circuit.

5. The circuit according to claim 1, characterized in that, The number of the at least one read auxiliary unit is 1.

6. A storage circuit, characterized in that, It includes a sub-readout circuit, read bit lines, at least one read auxiliary unit, and multiple static random access memory (SRAM) cells, wherein, The read bit lines are respectively connected to the sub-readout circuit, the at least one read auxiliary unit, and the plurality of SRAM units; The sub-readout circuit is used to perform read operations through the plurality of SRAM cells; The read assist unit is obtained by updating the circuit connection relationship of the SRAM cell, and the read assist unit is used to adjust the potential of the read bit line; The read auxiliary unit is used to pull down the potential of the read bit line; the read auxiliary unit includes a first unit and a second unit, the first unit including a first switch unit and a second switch unit, wherein... The first switching unit and the second switching unit are connected in series; The first switch unit is connected to the read bit line, and the first switch unit is also used to connect to the read word line, or the first switch unit is also used to connect to the second unit; The second switching unit is also used to connect to the second unit and the third power supply, respectively.

7. The circuit according to claim 6, characterized in that, The first switching unit is also used to connect to a read word line; the first switching unit is a first NMOS transistor, and the second switching unit is a second NMOS transistor, wherein... The gate of the first NMOS transistor is connected to the read word line, the source of the first NMOS transistor is connected to the read bit line, and the drain of the first NMOS transistor is connected to the drain of the second NMOS transistor. The gate of the second NMOS transistor is used to connect to the second cell, and the source of the second NMOS transistor is used to connect to the third power supply.

8. The circuit according to claim 6, characterized in that, The first switching unit is further configured to connect to the second unit; the first switching unit is a first NMOS transistor, and the second switching unit is a second NMOS transistor, wherein... The gate of the first NMOS transistor is connected to the gate of the second NMOS transistor and the second cell, respectively; the source of the first NMOS transistor is connected to the read bit line; and the drain of the first NMOS transistor is connected to the drain of the second NMOS transistor. The gate of the second NMOS transistor is used to connect to the second cell, and the source of the second NMOS transistor is used to connect to the third power supply.

9. The circuit according to any one of claims 6-8, characterized in that, The second unit includes a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a first PMOS transistor, and a second PMOS transistor, wherein... The source terminals of the first PMOS transistor and the second PMOS transistor are respectively connected to the second power supply. The gate of the first PMOS transistor, the gate of the third NMOS transistor, the drain of the second PMOS transistor, the drain of the fourth NMOS transistor, the drain of the fifth NMOS transistor, and the gate of the second NMOS transistor are connected. The drain of the first PMOS transistor, the drain of the third NMOS transistor, and the drain of the sixth NMOS transistor are connected. The source of the sixth NMOS transistor is used to connect to the first write bit line, and the gate of the sixth NMOS transistor is used to connect to the third power supply. The gates of the second PMOS transistor and the fourth NMOS transistor are respectively connected to the read bit line; The gate of the fifth NMOS transistor is used to connect to the third power supply, and the source of the fifth NMOS transistor is used to connect to the second write bit line. The source terminals of the third NMOS transistor and the fourth NMOS transistor are respectively connected to the third power supply.

10. The circuit according to claim 6, characterized in that, The storage circuit further includes a first edge unit and a second edge unit corresponding to the sub-readout circuit, wherein, The first edge unit is connected to the sub-read circuit, and the first edge unit is used to isolate the sub-read circuit from the SRAM cells adjacent to the sub-read circuit; The second edge unit is connected to the SRAM cell disposed at the edge of the storage circuit.

11. The circuit according to claim 6, characterized in that, The number of the at least one read auxiliary unit is 1.

12. A memory chip, characterized in that, It includes at least one storage circuit as described in any one of claims 1-11.

13. An electronic device, characterized in that, Includes the memory chip as described in claim 12.

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