Interface circuit, memory chip and data access method of memory

Abstract

The application discloses an interface circuit, a storage chip and a data access method of a memory. The interface circuit comprises a control circuit, a standard interface and a protocol conversion circuit. The control circuit is connected with a storage array of the memory. The data end, the address end and the instruction end of each storage unit of the storage array are respectively connected with different ports of the control circuit. The standard interface is used for accessing external data and outputting read data. The protocol conversion circuit is connected with the control circuit and the standard interface. The protocol conversion circuit converts the format of the external data to obtain write data conforming to the interface protocol of the storage array. The control circuit writes the write data converted by the protocol into the storage unit. The control circuit obtains read data from the storage unit. The protocol conversion circuit is used for converting the format of the read data to make the standard interface output read data conforming to the standard interface protocol. The interface circuit provided by the application can improve the access efficiency of the memory.

Description

Technical Field

[0001] This application relates to the field of data transmission technology, and in particular to an interface circuit, a memory chip, and a data access method for a memory. Background Technology

[0002] Traditional Dynamic Random Access Memory (DRAM) accesses its internal memory array through the JEDEC standard DRAM interface. Generally, the internal array of DRAM can be divided into multiple memory cells. However, due to the limitations of interface bit width and interface speed, all memory cells share the interface bus in a time-sharing manner. The system can only access one memory cell of DRAM at a time, resulting in low access efficiency and failure to fully utilize the performance of DRAM.

[0003] Non-standard memory array chips on the market have independent control lines, address lines, and data line interfaces for each memory cell, which greatly improves data bandwidth, but is incompatible with standard protocols and has poor user integration flexibility. Summary of the Invention

[0004] The main technical problem addressed by this application is to provide an interface circuit, a memory chip, and a data access method for the memory, which can improve the access efficiency of the memory.

[0005] To solve the above-mentioned technical problems, one technical solution adopted in this application is: providing an interface circuit, which includes a control circuit, a standard interface, and a protocol conversion circuit. The control circuit is connected to the storage array of the memory, and the data terminal, address terminal, and instruction terminal of each storage cell of the storage array are respectively connected to different ports of the control circuit. The standard interface is used to access external data and output read data. The protocol conversion circuit is connected to both the control circuit and the standard interface. The protocol conversion circuit performs format conversion on the external data to obtain write data that conforms to the interface protocol of the storage array. The control circuit writes the protocol-converted write data into the storage cell. The control circuit also retrieves read data from the storage cell, and the protocol conversion circuit performs format conversion on the read data so that the standard interface outputs read data that conforms to the standard interface protocol.

[0006] To solve the above-mentioned technical problems, another technical solution adopted in this application is to provide a memory chip, which includes the above-mentioned interface circuit and memory array. The interface circuit is used to access external data and perform read and write operations on the memory array based on the external data.

[0007] To address the aforementioned technical problems, another technical solution adopted in this application is: providing a data access method for a memory, wherein the memory's interface circuit includes a control circuit, a standard interface, and a protocol conversion circuit. The control circuit is connected to the conversion circuit and the memory's storage array, respectively. The data terminal, address terminal, and instruction terminal of each storage cell in the storage array are connected to different ports of the control circuit. The data access method includes: the standard interface receiving external data; the protocol conversion circuit performing format conversion on the external data to obtain write data; the control circuit writing the write data to the storage cell; and the control circuit obtaining read data from the storage cell and feeding it back to the protocol conversion circuit, which performs format conversion on the read data so that the standard interface outputs read data conforming to the standard interface protocol.

[0008] Beneficial Technical Effects: The interface circuit provided in this application, by setting up a protocol conversion circuit, a standard interface, and a control circuit, and connecting the data terminal, address terminal, and command terminal of each storage cell of the memory array to different ports of the control circuit, allows the control circuit to write data conforming to the interface protocol of the memory array, obtained by the protocol conversion circuit from external data accessed through the standard interface, to the storage cell. Alternatively, the control circuit can retrieve read data from the storage cell and transmit it to the protocol conversion circuit. After the protocol conversion circuit performs format conversion on the read data, the standard interface can output read data conforming to the standard interface protocol, thereby ensuring that the memory is compatible with standard protocols and improving the flexibility of user integration. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:

[0010] Figure 1 This is a schematic diagram of the structure of an embodiment of the interface circuit provided in this application;

[0011] Figure 2 yes Figure 1 A schematic diagram of the implementation of the standard interface and protocol conversion circuit in the embodiment;

[0012] Figure 3 This is a schematic diagram of an embodiment of the interconnection between the interface circuit and the memory in this application;

[0013] Figure 4 yes Figure 2 A schematic diagram of one embodiment of the control circuit is shown in the example.

[0014] Figure 5 yesFigure 4 A schematic diagram of one embodiment of the NOC circuit in the examples;

[0015] Figure 6 yes Figure 2 A schematic diagram of another embodiment of the control circuit in the example;

[0016] Figure 7 This is a schematic diagram of the structure of a memory chip according to an embodiment of this application;

[0017] Figure 8 This is a schematic flowchart of an embodiment of the memory data access method provided in this application;

[0018] Figure 9 This is a flowchart illustrating another embodiment of the memory data access method provided in this application. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0020] In the description of the embodiments of this application, it should be noted that, unless otherwise explicitly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this application based on the specific circumstances.

[0021] In the embodiments of this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0022] See Figure 1 , Figure 1 This is a schematic diagram of an embodiment of the interface circuit provided in this application. Figure 1As shown, the interface circuit 100 includes a protocol conversion circuit 110, a standard interface 130, and a control circuit 120. The control circuit 120 is connected to both the protocol conversion circuit 110 and the memory array (not shown). The data terminal, address terminal, and instruction terminal of each memory cell (not shown) in the memory array are connected to different ports of the control circuit 120. The standard interface 130 is used to receive external data and output read data. The protocol conversion circuit 110 is connected to both the control circuit 120 and the standard interface 130. It is used to convert the format of external data to obtain write data conforming to the interface protocol of the memory array. The control circuit 120 writes the protocol-converted write data to the memory cell; or the control circuit 120 retrieves read data from the memory cell, and the protocol conversion circuit 110 converts the format of the read data so that the standard interface 130 outputs read data conforming to the standard interface 130 protocol. The memory can be a random access memory (RAM).

[0023] The interface circuit 100 provided in this application, through the configuration of a protocol conversion circuit 110, a standard interface 130, and a control circuit 120, connects the data terminal, address terminal, and instruction terminal of each storage cell in the memory array to different ports of the control circuit 120. The control circuit 120 can be used to write data conforming to the interface protocol of the memory array, obtained by the protocol conversion circuit 110 converting the external data accessed through the standard interface 130, to the storage cell. Alternatively, the control circuit 120 can retrieve read data from the storage cell and transmit it to the protocol conversion circuit 110. After the protocol conversion circuit 110 converts the read data, the standard interface 130 can output read data conforming to the standard interface 130 protocol, thereby enabling the memory to be compatible with standard protocols and improving the flexibility of user integration.

[0024] Optionally, see Figures 2-3 , Figure 2 yes Figure 1 A schematic diagram of the implementation of the standard interface and protocol conversion circuit 110 in this embodiment; Figure 3This is a schematic diagram of an embodiment of the interconnection between the interface circuit and the memory in this application. As shown in the figure, the standard interface 130 may include any one or both of the following: bus interface 131 and DDR interface 132. The protocol conversion circuit 110 is based on the standard interface 130 and is configured accordingly. When the standard interface 130 includes the bus interface 131, the protocol conversion circuit 110 includes a bus protocol conversion circuit 111, which is connected to both the control circuit 120 and the bus interface 131. The bus protocol conversion circuit 111 is used to convert the format of external data to obtain write data, write address, and write command conforming to the interface protocol of the memory array. The control circuit 120 writes the write data to the memory cell corresponding to the write address based on the write command. The bus protocol conversion circuit 111 is also used to convert external data to obtain a read address and read command that conforms to the interface protocol of the storage array. The control circuit 120 reads the read data from the storage cell corresponding to the read address based on the read command and feeds it back to the bus protocol conversion circuit 111. The bus protocol conversion circuit 111 performs format conversion on the read data so that the bus interface 131 outputs read data that conforms to the bus interface 131 protocol. The protocol of the bus protocol conversion circuit 111 can be the Advanced Microcontroller Bus Architecture (AMBA) protocol, Wishbone, Core Connect, or other mainstream SOC system bus protocols.

[0025] When the standard interface 130 includes a DDR interface 132, the protocol conversion circuit 110 also includes a DDR protocol conversion circuit 112. The DDR protocol conversion circuit 112 is connected to both the control circuit 120 and the DDR interface 132, and is used to convert the format of external data to obtain write data, write address, and write command conforming to the interface protocol of the storage array. The control circuit 120 writes the write data to the storage cell corresponding to the write address based on the write command. The DDR protocol conversion circuit 112 also converts external data to obtain read address and read command conforming to the interface protocol of the storage array. The control circuit 120 reads read data from the storage cell corresponding to the read address based on the read command and feeds it back to the DDR protocol conversion circuit 112. The DDR protocol conversion circuit 112 converts the format of the read data so that the DDR interface 132 outputs read data conforming to the DDR interface 132 protocol. The DDR protocol conversion circuit 112 can be a standard protocol such as DDR4, PDDR2, LPDDR3, LPDDR4, LPDDR5, GDDR3, GDDR5, or GDDR6.

[0026] Among them, different types of standard interfaces 130 are independently connected to the corresponding protocol conversion circuits 110, and the protocol conversion circuits 110 and control circuits 120 are independently connected, thus realizing the multiplexing of bus interface 131 and DDR interface 132 with the controller.

[0027] In this embodiment, the standard interface 130 includes a bus interface 131 and / or a DDR interface 132. The protocol conversion circuit 110 is configured with a bus protocol conversion circuit 111 and / or a DDR protocol conversion circuit 112 corresponding to the standard interface 130. Different protocol conversion circuits 110 are used to convert the format of external data, enabling the control circuit 120 to read data stored in the storage array based on the external data, or to store data in the storage array. That is, external data accessed by different types of standard interfaces 130 can be read and written to the storage array by the control circuit 120 under the action of the protocol conversion circuit 110 corresponding to the standard interface 130, thus satisfying the data read and write requirements of different standard interfaces 130 in the storage array and improving the flexibility of user integration. Furthermore, the bus interface 131 is connected to the control circuit 120 through the bus protocol conversion circuit 111, and / or the DDR interface 132 is connected to the control circuit 120 through the DDR protocol conversion circuit 112, realizing the multiplexing of the bus interface 131 and the DDR interface 132 with the control circuit 120.

[0028] The interface circuit 100 is connected to the memory via printed circuit board (PCB) technology or multi-chip module (MCM) technology. Preferably, the interface circuit 100 and the memory are interconnected using hybrid bonding and through-silicon via (TSV) technologies within three-dimensional integrated technology (3DIC). 3DIC is a mature technology suitable for multi-chip stack interconnection. In 3DIC, fused bonding or direct wafer bonding provides a permanent connection through dielectric layers on each wafer surface. Hybrid bonding extends fused bonding with metal pads embedded in the bonding interface, allowing for face-to-face wafer connections. TSV technology achieves vertical electrical interconnection vias by filling conductive materials such as copper, tungsten, and polysilicon. Through-silicon via technology reduces interconnect length, signal delay, and capacitance / inductance through vertical interconnection, enabling low-power, high-speed communication between chips, increased bandwidth, and miniaturized device integration. In this embodiment, the data, address, and instruction terminals of all memory cells of the memory array chip and the different ports of the control circuit 120 in the interface circuit 100 can be interconnected in the same direction using Hybrid Bonding and TSV technologies. Then, the connected memory array chip and control circuit 120 can be interconnected on opposite sides using Hybrid Bonding technology. Figure 3 As shown, the interface circuit 100 and the memory are interconnected through the 3DIC process, and the connection lines between them are stacked on the middle layer of the 3DIC.

[0029] The interface circuit 100 is interconnected with the memory array through Hybrid Bonding and TSV technologies. The connection lines between the two are stacked on the middle layer of the 3DIC, so that the memory interface bit width is no longer limited by the package and system hardware. Therefore, the memory cell interface signal can be directly output, which allows the interface circuit 100 to directly control all memory cells to read and write at the same time, thereby improving the memory access efficiency.

[0030] Optionally, see Figures 4-5 , Figure 4 yes Figure 2 A schematic diagram of one embodiment of the control circuit is shown in the example. Figure 5 yes Figure 4This is a schematic diagram of one embodiment of the NOC circuit. As shown in the figure, the control circuit 120 includes a storage controller 121 and an NOC circuit 122. The NOC circuit 122 includes a source node (not labeled) and multiple path nodes (not labeled). The storage controller 121 is connected to the bus protocol conversion circuit 111, the DDR protocol conversion circuit 112, and the source node. The source node and the multiple path nodes are connected to the storage cells one-to-one. The data terminal, address terminal, and instruction terminal of each storage cell in the storage array are connected to different ports of the corresponding source node or path node. The storage controller 121 writes write data to the source node of the NOC circuit 122 based on write instructions and write addresses. The source node and path nodes route the write data to the storage cell corresponding to the write address. The storage controller 121 also aggregates read data from the storage cell corresponding to the read address through the path nodes and source nodes based on read instructions and read addresses. The source node is the path node selected from the path nodes; those not selected continue to be path nodes.

[0031] In this embodiment, the control circuit 120 includes a storage controller 121 and an NOC circuit 122. The NOC circuit 122 includes a source node and multiple path nodes. The storage controller 121 is connected to the bus protocol conversion circuit 111, the DDR protocol conversion circuit 112, and the source node. The source node and multiple path nodes are connected to a storage unit in a one-to-one correspondence. The data terminal, address terminal, and instruction terminal of each storage unit in the storage array are connected to different ports of the corresponding source node or path node. Through this method, the storage controller 121 writes the write data to the source node based on the format-converted write instructions and write addresses from the bus protocol conversion circuit 111 and the DDR protocol conversion circuit 112. Within the node, the write data is routed to the storage unit corresponding to the write address through the source node and path node; or the storage controller 121, based on the read instruction and read address, aggregates the read data of the storage unit corresponding to the read address through the path node and source node, so that the corresponding data can be read through different paths, thereby improving the access speed of data read and write in the storage array; furthermore, the bus interface 131 and the DDR interface 132 are connected through the bus protocol conversion circuit 111 and the DDR protocol conversion circuit 112, respectively, and both read and write data to the storage array through the storage controller 121, thereby realizing the multiplexing of the bus interface 131, the DDR interface 132 and the storage controller 121.

[0032] Optionally, see Figure 6 , Figure 6 yes Figure 2 A schematic diagram of another embodiment of the control circuit in the example. (See attached diagram.) Figure 6As shown, the control circuit 120 includes a bus storage controller 121b and an NOC circuit 122. The NOC circuit 122 includes a source node and multiple path nodes. The bus storage controller 121b is connected to both the bus protocol conversion circuit 111 and the source node of the NOC circuit 122. The source node and the multiple path nodes of the NOC circuit 122 are connected to storage cells one-to-one. Each storage cell in the storage array has its data terminal, address terminal, and instruction terminal connected to different ports of its corresponding source node or path node. The bus storage controller 121b writes write data to the source node based on the write instruction and write address. The source node and path nodes route the write data to the storage cell corresponding to the write address. The bus storage controller 121b aggregates read data from the storage cell corresponding to the read address through the path nodes and source node based on the read instruction and read address. And / or

[0033] The control circuit 120 includes a DDR memory controller 121a, which is connected to the DDR protocol conversion circuit 112 and the memory array. The data terminal, address terminal, and command terminal of each memory cell in the memory array are connected to different ports of the DDR memory controller 121a. The DDR memory controller 121a writes data to the memory cell corresponding to the write address based on the write command and write address. The DDR memory controller 121a feeds back the read data from the memory cell corresponding to the read address to the DDR protocol conversion circuit 112 based on the read command and read address.

[0034] Optionally, the source node and multiple path nodes of the NOC circuit 122 are each equipped with a DMA circuit (not shown in the figure). The DMA circuit of the source node is connected to the bus memory controller 121b and / or the DDR memory controller 121a, meaning the DMA circuit of the source node is connected to the memory controller 121. Furthermore, the data terminal, address terminal, and instruction terminal of the memory cell are respectively connected to different ports of the corresponding DMA circuit. The DMA circuit is used to implement data transfer between the corresponding memory cells.

[0035] This application also provides a memory chip, see reference. Figure 7 , Figure 7 This is a schematic diagram of the structure of an embodiment of the memory chip provided in this application. Figure 7 As shown, the memory chip 50 includes the interface circuit 100 and the memory array 500 in the above embodiments. The interface circuit 100 is used to access external data and perform read and write operations on the memory array 500 based on the external data.

[0036] The interface circuit 100 receives external data, which can be write data, write address and write instruction, or read address and read instruction. When the external data is write data, write address and write instruction, the interface circuit 100 performs a write operation on the memory array 500; when the external data is read address and read instruction, the interface circuit 100 performs a read operation on the memory array 500.

[0037] Alternatively, the interface circuit 100 and the storage array 500 can be integrated using printed circuit board (PCB) technology, multi-chip module (MCM) technology, or three-dimensional integrated technology (3DIC).

[0038] This application also provides a data access method for a memory, wherein the interface circuit 100 of the memory includes a protocol conversion circuit 110, a control circuit 120 and a standard interface 130, the control circuit 120 is connected to the conversion circuit and the memory array respectively, and the data terminal, address terminal and instruction terminal of each memory cell of the memory array are connected to different ports of the control circuit 120 respectively.

[0039] See Figure 8 , Figure 8 This is a schematic flowchart of an embodiment of the memory data access method provided in this application. Figure 8 As shown, this data access method includes the following steps:

[0040] Step S600: The standard interface 130 receives external data and outputs read data. The protocol conversion circuit 110 converts the format of the external data to obtain write data.

[0041] The standard interface 130 receives external data. After the external data is converted into a format by the protocol conversion circuit 110, it becomes write data that can be recognized by the control circuit 120.

[0042] Step S700: The control circuit 120 writes the data to the storage unit; and the control circuit 120 obtains the read data from the storage unit and feeds it back to the protocol conversion circuit 110. The protocol conversion circuit 110 is used to convert the format of the read data so that the standard interface 130 outputs read data that conforms to the standard interface 130 protocol.

[0043] When the control circuit 120 receives write data, it writes the write data to the storage unit. The control circuit 120 also retrieves read data from the storage unit and feeds it back to the protocol conversion circuit 110. The protocol conversion circuit 110 performs format conversion on the read data so that the standard interface 130 outputs read data that conforms to the standard interface 130 protocol.

[0044] Optionally, the standard interface 130 includes a bus interface 131, and the protocol conversion circuit 110 includes a bus protocol conversion circuit 111 connected to the control circuit 120 and the bus interface 131 respectively. Step S600 may further include the following steps:

[0045] S610: The bus interface 131 receives external data, and the bus protocol conversion circuit 111 performs format conversion on the external data to obtain write data, write address and write command that conform to the interface protocol of the storage array; and the bus protocol conversion circuit 111 performs format conversion on the external data to obtain read address and read command that conform to the interface protocol of the storage array chip.

[0046] Bus interface 131 receives external data, and bus protocol conversion circuit 111 converts the format of the external data to obtain write data, write address, and write command conforming to the interface protocol of the memory array. Alternatively, bus protocol conversion circuit 111 converts the format of external data to obtain read address and read command conforming to the interface protocol of the memory array chip.

[0047] Based on step S610, step S700 may further include the following steps:

[0048] S710: Control circuit 120 writes write data to the memory cell corresponding to the write address based on the write instruction; and control circuit 120 reads read data from the memory cell corresponding to the read address based on the read instruction and feeds it back to bus protocol conversion circuit 111. Bus protocol conversion circuit 111 performs format conversion on the read data so that bus interface 131 outputs read data that conforms to the bus interface 131 protocol.

[0049] The control circuit 120 writes the received write data into the memory cell corresponding to the write address based on the write instruction. Alternatively, the control circuit 120 reads the data from the memory cell corresponding to the read address based on the read instruction and feeds it back to the bus protocol conversion circuit 111. The bus protocol conversion circuit 111 performs format conversion on the read data so that the bus interface 131 outputs read data that conforms to the bus interface 131 protocol.

[0050] and / or

[0051] The standard interface 130 includes a DDR interface 132, and the protocol conversion circuit 110 includes a DDR protocol conversion circuit 112 connected to the control circuit 120 and the DDR interface 132 respectively. The standard interface 130 receives external data. Step S600 may further include the following steps:

[0052] S620: DDR interface 132 receives external data, and DDR protocol conversion circuit 112 is used to convert the format of external data to obtain write data, write address and write command that conform to the interface protocol of the storage array.

[0053] The DDR interface 132 receives external data and converts the external data into a format that conforms to the interface protocol of the storage array, thereby obtaining write data, write address and write command.

[0054] Based on step S620, step S700 may further include the following steps:

[0055] S720: The control circuit 120 writes write data to the memory cell corresponding to the write address based on the write instruction; and the control circuit 120 reads read data from the memory cell corresponding to the read address based on the read instruction, and feeds it back to the DDR protocol conversion circuit 112. The DDR protocol conversion circuit 112 performs format conversion on the read data so that the DDR interface 132 outputs read data that conforms to the DDR interface 132 protocol.

[0056] The control circuit 120 writes the received write data to the memory cell corresponding to the write address based on the write instruction. Alternatively, the control circuit 120 reads the read data from the memory cell corresponding to the read address based on the read instruction and feeds it back to the DDR protocol conversion circuit 112. The DDR protocol conversion circuit 112 performs format conversion on the read data so that the DDR interface 132 outputs read data that conforms to the DDR interface 132 protocol.

[0057] See Figure 9 , Figure 9 A flowchart illustrating another embodiment of the memory data access method provided in this application is shown below. Figure 9 As shown, the interface circuit 100 receives external data to the protocol conversion circuit 110. The conversion circuit performs format conversion on the external data. When write data, write address and write instruction are obtained, the control circuit 120 writes the write data to the memory unit corresponding to the write address based on the write instruction. When read address and read instruction are obtained after conversion, the control circuit 120 reads read data from the memory unit corresponding to the read address based on the read instruction and feeds it back to the protocol conversion circuit 110.

[0058] In the description of this application, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0059] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0060] Any process or method description in the flowchart or otherwise herein can be understood as representing an apparatus, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process, and the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order according to the functions involved, as should be understood by those skilled in the art to which embodiments of this application pertain.

[0061] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (which may be a personal computer, server, network device, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer storage medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer storage media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0062] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. An interface circuit, characterized in that, include: A control circuit is connected to the memory array, wherein the data terminal, address terminal, and instruction terminal of each memory cell of the memory array are respectively connected to different ports of the control circuit; Standard interface for receiving external data and outputting read data; The protocol conversion circuit is connected to the control circuit and the standard interface respectively. The protocol conversion circuit converts the format of the external data to obtain write data that conforms to the interface protocol of the storage array. The control circuit writes the protocol-converted write data into the storage unit. The control circuit obtains read data from the storage unit, and the protocol conversion circuit is used to convert the format of the read data so that the standard interface outputs read data that conforms to the standard interface protocol. The standard interface includes a bus interface and a DDR interface, and the protocol conversion circuit includes a bus protocol conversion circuit and a DDR protocol conversion circuit. The control circuit includes a storage controller and an NOC circuit. The NOC circuit includes a source node and multiple path nodes. The storage controller is connected to the bus protocol conversion circuit, the DDR protocol conversion circuit, and the source node. The source node and multiple path nodes are connected to the storage units one by one. The data terminal, address terminal, and instruction terminal of each storage unit of the storage array are connected to different ports of the corresponding source node or path node. The storage controller writes the write data to the source node based on the write instruction and the write address, and the source node and the path node route the write data to the storage unit corresponding to the write address. The storage controller aggregates the read data of the storage unit corresponding to the read address through the path node and the source node based on the read instruction and read address; The source node and the multiple path nodes are each equipped with a DMA circuit. The DMA circuit of the source node is connected to the storage controller, and the data terminal, address terminal and instruction terminal of the storage unit are respectively connected to different ports of the corresponding DMA circuit. The DMA circuit is used to realize the data transfer of the corresponding storage unit.

2. The interface circuit according to claim 1, characterized in that, The bus protocol conversion circuit is connected to the control circuit and the bus interface respectively, and is used to convert the format of the external data to obtain write data, write address and write instruction that conform to the interface protocol of the storage array. The control circuit writes the write data into the storage cell corresponding to the write address based on the write instruction. The external data is converted to obtain a read address and read instruction that conform to the interface protocol of the storage array. The control circuit reads read data from the storage cell corresponding to the read address based on the read instruction and feeds it back to the bus protocol conversion circuit. The bus protocol conversion circuit performs format conversion on the read data so that the bus interface outputs read data that conforms to the bus interface protocol. and The DDR protocol conversion circuit is connected to the control circuit and the DDR interface respectively, and is used to convert the format of the external data to obtain write data, write address and write instruction that conform to the interface protocol of the storage array. The control circuit writes the write data into the storage cell corresponding to the write address based on the write instruction. The external data is converted to obtain a read address and read command that conform to the interface protocol of the storage array. The control circuit reads read data from the storage cell corresponding to the read address based on the read command and feeds it back to the DDR protocol conversion circuit. The DDR protocol conversion circuit performs format conversion on the read data so that the DDR interface outputs read data that conforms to the DDR interface protocol.

3. The interface circuit according to claim 2, characterized in that, The control circuit includes: A bus storage controller and an NOC circuit are provided. The NOC circuit includes a source node and multiple path nodes. The bus storage controller is connected to both the bus protocol conversion circuit and the source node. The source node and multiple path nodes are connected to the storage cells one-to-one. The data terminal, address terminal, and instruction terminal of each storage cell in the storage array are connected to different ports of the corresponding source node or path node. The bus storage controller writes the write data to the source node based on the write instruction and the write address, and the source node and the path node route the write data to the storage unit corresponding to the write address; The bus storage controller, based on the read instruction and the read address, aggregates the read data of the storage unit corresponding to the read address through the path node and the source node; and The control circuit includes: A DDR memory controller is connected to both the DDR protocol conversion circuit and the memory array. The data terminal, address terminal, and command terminal of each memory cell in the memory array are connected to different ports of the DDR memory controller. The DDR memory controller writes the write data into the memory cell corresponding to the write address based on the write instruction and the write address; The DDR memory controller feeds back the read data of the memory cell corresponding to the read address to the DDR protocol conversion circuit based on the read instruction and the read address.

4. A memory chip, characterized in that, The invention includes the interface circuit and storage array as described in any one of claims 1-3, wherein the interface circuit is used to access the external data and perform read and write operations on the storage array based on the external data.

5. The memory chip according to claim 4, characterized in that, The storage array and the interface circuit are interconnected via Hybrid Bonding technology and Through Silicon Via technology.

6. The memory chip according to claim 5, characterized in that, The interface circuit and the storage array are integrated via PCB, MCM or 3DIC.

7. A data access method for a memory, characterized in that, The interface circuit of the memory includes the interface circuit described in claim 1; the interface circuit includes a control circuit, a standard interface and a protocol conversion circuit, the control circuit is connected to the protocol conversion circuit and the memory array of the memory respectively, and the data terminal, address terminal and instruction terminal of each memory cell of the memory array are connected to different ports of the control circuit respectively; The data access method includes: The standard interface receives external data, and the protocol conversion circuit performs format conversion on the external data to obtain write data. The control circuit writes data to the storage unit based on the write data; and the control circuit obtains read data from the storage unit and feeds it back to the protocol conversion circuit, the protocol conversion circuit being used to perform format conversion on the read data so that the standard interface outputs read data that conforms to the standard interface protocol.

8. The data access method according to claim 7, characterized in that, The standard interface includes a bus interface, and the protocol conversion circuit includes a bus protocol conversion circuit connected to both the control circuit and the bus interface. The standard interface receives external data, and the protocol conversion circuit performs format conversion on the external data to obtain write data. The circuit also includes: The bus interface receives the external data, and the bus protocol conversion circuit performs format conversion on the external data to obtain write data, write address, and write command that conform to the interface protocol of the storage array; and the bus protocol conversion circuit performs format conversion on the external data to obtain read address and read command that conform to the interface protocol of the storage array. The control circuit writes data to the storage unit based on the write data; and the control circuit retrieves read data from the storage unit and feeds it back to the protocol conversion circuit, the protocol conversion circuit being used to perform format conversion on the read data so that the standard interface outputs read data conforming to the standard interface protocol, further comprising: The control circuit writes the write data to the memory cell corresponding to the write address based on the write instruction; and the control circuit reads the read data from the memory cell corresponding to the read address based on the read instruction, and feeds it back to the bus protocol conversion circuit, which performs format conversion on the read data so that the bus interface outputs read data that conforms to the bus interface protocol; and The standard interface includes a DDR interface, and the protocol conversion circuit includes a DDR protocol conversion circuit connected to the control circuit and the DDR interface respectively. The standard interface receives external data, and the protocol conversion circuit performs format conversion on the external data to obtain write data. The circuit also includes: The DDR interface receives the external data, and the DDR protocol conversion circuit is used to convert the format of the external data to obtain write data, write address and write command that conform to the interface protocol of the storage array. The control circuit writes data to the storage unit based on the write data; and the control circuit retrieves read data from the storage unit and feeds it back to the protocol conversion circuit, the protocol conversion circuit being used to perform format conversion on the read data so that the standard interface outputs read data conforming to the standard interface protocol, further comprising: The control circuit writes the write data to the memory cell corresponding to the write address based on the write instruction; and the control circuit reads the read data from the memory cell corresponding to the read address based on the read instruction and feeds it back to the DDR protocol conversion circuit. The DDR protocol conversion circuit performs format conversion on the read data so that the DDR interface outputs read data that conforms to the DDR interface protocol.

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