A probe contact-based memory chip ft test method

Abstract

The application relates to the technical field of semiconductor testing, and discloses a memory chip FT test method based on probe contact. The method comprises the following steps: acquiring wafer-level process parameters, layout and wiring topology and historical yield data of a chip; dividing a logic test block; calculating defect probability scores of each block and sorting to generate a test sequence; performing full-function testing in sequence, collecting response signal features in real time and comparing the response signal features with a health benchmark model, and dynamically triggering adjacent expansion testing or failure determination; and feeding back test results to update yield data. The application shortens the test time and reduces the test cost while guaranteeing the defect coverage rate through a risk-oriented adaptive test strategy.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor testing technology, specifically relating to a probe-contact-based FT testing method for memory chips. Background Technology

[0002] With the continuous miniaturization of semiconductor manufacturing processes and the constant improvement of storage density, high-capacity memory chips are increasingly widely used in data centers, artificial intelligence accelerators, and high-end consumer electronics devices. Against this backdrop, wafer-level final test (FT), as a crucial step in ensuring chip yield and reliability, directly impacts product cost and market competitiveness through its testing efficiency and coverage completeness. Traditional FT testing methods rely on the physical contact between probe cards and chip pads, applying stimuli address-by-address and function-by-function to capture responses and verify the read / write correctness, timing compliance, and boundary condition stability of memory cells. This method faces challenges when dealing with high-density memory arrays: full address space traversal leads to an exponential increase in the number of test vectors, and the testing time for a single chip can reach several minutes or even longer, limiting production line throughput and increasing the cost of test equipment.

[0003] FT testing of memory chips based on probe contacts focuses on functional verification and defect screening of the internal memory array through physical electrical connections. The goal is to identify faulty chips with manufacturing defects with the highest possible confidence within a limited testing window, while avoiding misclassifying qualified chips as defective. To alleviate testing time pressure, the industry often employs address sampling or functional pruning strategies, verifying only a portion of the address space or critical operating modes. While such simplified methods can shorten the testing cycle, they carry the risk of missed defects due to insufficient sampling coverage, and are particularly difficult to capture hidden defects with spatial locality or conditional triggering, such as weak cell faults that only manifest under specific temperature-voltage combinations, or coupling interference errors that are only activated during continuous writing of specific data patterns.

[0004] In existing technologies, both full-scale testing and sampling testing are based on the assumption of the Nyquist sampling theorem, which states that signals must be sampled densely to fully reconstruct their state. This paradigm leads to a strong coupling between testing time and storage capacity, making it impossible to overcome the problem of "the larger the capacity, the slower the test." Although some research has attempted to introduce built-in self-test (BIST) or compressed test vector techniques, the former is limited by on-chip logic area overhead, while the latter struggles to balance versatility and diagnostic accuracy. In probe-based contact FT scenarios, external test equipment must handle all stimulus generation and response analysis tasks, lacking effective utilization of the sparsity of the storage array's inherent structure or fault propagation patterns. Therefore, while ensuring a high defect detection rate, how to overcome the limitations of traditional sampling theory and construct an FT testing method that deeply collaborates with the physical architecture of the storage array and can achieve rapid functional verification with extremely low sampling rates has become an urgent technical problem to be solved. Summary of the Invention

[0005] This invention provides a probe-based Final Test (FT) method for memory chips, aiming to solve the technical problems faced by large-capacity memory chips in the Final Test (FT) stage, such as the extremely long testing time and high testing cost of full address / full function testing, while traditional sampling testing may miss defects. This memory chip FT testing method constructs a dynamic adaptive test path selection mechanism, combining chip physical structure characteristics and historical yield data, to achieve precise focused testing of high-risk areas, thereby shortening testing time and reducing testing costs while ensuring defect coverage.

[0006] This invention provides a probe-contact-based FT testing method for memory chips, comprising:

[0007] After the probe station completes physical contact with the memory chip, it acquires the wafer-level process parameters, layout and routing topology information, and historical yield distribution data of the same batch of the memory chip.

[0008] Based on the layout and routing topology information, the memory array of the memory chip is divided into several logical test blocks, and each logical test block corresponds to a set of physical address ranges.

[0009] Based on the wafer-level process parameter information and the historical yield distribution data of the same batch, calculate the defect probability score for each logic test block;

[0010] Based on the defect probability score, all logical test blocks are prioritized and an initial test sequence is generated;

[0011] According to the initial test sequence, a full-function test instruction set is executed sequentially on each logic test block. The full-function test instruction set includes read / write operations, refresh cycle verification, voltage stress test, and temperature cycle response test.

[0012] During the test, the response signal characteristics of each logic test block are collected in real time. The response signal characteristics include signal rise time, fall time, eye diagram opening degree and bit error rate.

[0013] The response signal characteristics are compared with a preset health benchmark model. If the deviation is greater than the first threshold, an extended test is triggered on the neighboring blocks of the logic test block. If the deviation is greater than the second threshold and the second threshold is greater than the first threshold, the current test process is terminated immediately and the chip is marked as a defective product.

[0014] After the test is completed, update the historical yield distribution data of the same batch and feed the test results back to the defect probability score calculation module for the next round of testing.

[0015] Preferably, the wafer-level process parameter information includes photolithography alignment error, thin film deposition thickness uniformity, surface roughness after chemical mechanical polishing, resistivity of the metal interconnect layer, and breakdown voltage of the dielectric layer.

[0016] Preferably, the layout and routing topology information is obtained by parsing the GDSII layout file of the memory chip, including the physical coordinates of each memory cell, the direction of word lines and bit lines, the distribution density of the power network, and the location of the redundancy repair unit.

[0017] Preferably, the division of the logical test blocks follows these rules: each block contains a continuous physical address space, and the block boundary is aligned with the physical boundary of the storage volume or subarray; the number of storage units in each block is not greater than a preset upper limit.

[0018] Preferably, the defect probability score is calculated using a weighted fusion model. The input variables include: the radial position offset of the logic test block on the wafer, the average failure density of the surrounding area in historical tests, the local current density of the metal interconnect layer, and the activation state of the adjacent redundant units. Each input variable is multiplied by its corresponding weight coefficient and then summed. The sum is then mapped to the 0 to 1 interval by the Sigmoid function to obtain the final defect probability score.

[0019] Preferably, the weight coefficients are obtained through offline training, and the training data comes from the dataset of all memory chips that have completed FT testing under the same process node in the past 12 months. The training objective is to minimize the cross-entropy loss between the predicted defect probability and the actual failure label.

[0020] Preferably, the execution of the full-function test instruction set is generated by the vector generator of the test machine. The test vectors cover all basic operation modes, including single read / write, burst read / write, page mode access, self-refresh entry and exit, and hold time verification under alternating high and low temperatures.

[0021] Preferably, the acquisition of the response signal characteristics is achieved by synchronously capturing the DQ signal and control signal output by the probe card through a high-bandwidth oscilloscope channel.

[0022] Preferably, the health benchmark model is a multidimensional Gaussian distribution model, and the mean vector and covariance matrix are obtained by statistical analysis of the response signal features of good chips under standard test conditions. The model dimension is equal to the number of response signal features collected.

[0023] Preferably, the extended test range of the neighboring blocks is defined by the Manhattan distance. When the central block is determined to be abnormal, a full-function test instruction set is executed on all logical test blocks around it with a Manhattan distance of less than or equal to 2.

[0024] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0025] 1. This invention introduces a defect probability scoring mechanism based on physical structure and historical yield, transforming the traditional full address traversal test into a dynamic adaptive test strategy that prioritizes high-risk areas, thus avoiding redundant testing of low-risk areas and significantly shortening the average test time of a single chip.

[0026] 2. By collecting response signal characteristics in real time and comparing them quantitatively with the health benchmark model, early identification of potential defects and intelligent extended testing of adjacent areas are achieved, improving the defect detection rate and overcoming the inherent defect of traditional sampling testing that is prone to missing local defects.

[0027] 3. The closed-loop feedback mechanism of test results enables the system to continuously learn and adapt to process fluctuations, further optimizing the accuracy and efficiency of subsequent tests.

[0028] 4. The overall solution reduces testing costs and increases testing throughput without sacrificing test coverage, making it suitable for large-scale mass production testing scenarios of high-density, high-capacity memory chips. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of the overall technical solution architecture of the present invention;

[0030] Figure 2 This is a schematic diagram of the core principle framework of the dynamic adaptive test path selection mechanism in this invention;

[0031] Figure 3 This is a logical flowchart of the logical test block division and defect probability score calculation in this invention;

[0032] Figure 4 This is a logical flowchart of the full-function test execution and response signal feature acquisition in this invention;

[0033] Figure 5 This is a logical flowchart of the health status comparison, extended test triggering and failure determination in this invention;

[0034] Figure 6 This is a schematic diagram of the multi-level interaction relationship and data flow between test result feedback and dynamic updating of historical yield data in this invention. Detailed Implementation

[0035] refer to Figures 1 to 6 This invention provides a probe-based Full-Function Testing (FT) method for memory chips, aiming to solve the technical problems faced by large-capacity memory chips in the final testing stage, such as the extremely long testing time and high testing cost of full-address and full-function testing, while traditional sampling testing may miss defects. This memory chip FT testing method constructs a dynamic adaptive test path selection mechanism, combining chip physical structure characteristics and historical yield data, to achieve precise focused testing of high-risk areas, thereby shortening testing time and reducing testing costs while ensuring defect coverage.

[0036] After the probe station makes physical contact with the memory chip, step S1 is executed: The wafer-level process parameters, placement and routing topology information, and historical yield distribution data for the same batch are acquired. Wafer-level process parameters include lithography alignment error, thin film deposition thickness uniformity, surface roughness after chemical mechanical polishing, resistivity of the metal interconnect layer, and breakdown voltage of the dielectric layer. These parameters are automatically recorded by the manufacturing execution system after wafer fabrication and transmitted to the test control system via a standardized interface. Placement and routing topology information is obtained by parsing the memory chip's GDSII layout file, including the physical coordinates of each memory cell, the routing of word lines and bit lines, the distribution density of the power network, and the location of redundant repair cells. The GDSII file is generated by design automation tools, and the test system converts it into a structured data format using a dedicated parsing engine for subsequent logic block partitioning. Historical yield distribution data for the same batch originates from a central yield analysis server. Its content includes the failure statistics of all chips tested in the current wafer batch in each logic region, stored in the form of a two-dimensional spatial heatmap with a resolution consistent with the granularity of the logic test blocks.

[0037] Step S2: Based on the layout and routing topology information, the memory array of the memory chip is divided into several logical test blocks, each corresponding to a set of physical address ranges. The division of logical test blocks follows these rules: each block contains a continuous physical address space, and the block boundary is aligned with the physical boundary of the memory bank or subarray; the number of memory cells in each block does not exceed a preset upper limit of 1 million bits. The division process first identifies all memory bank boundaries, and then performs secondary division within each memory bank according to the subarray structure. If the subarray size is greater than 1 million bits, it is further divided evenly along the word line direction to ensure that the storage capacity of each logical test block is strictly controlled within the upper limit. The division results are stored in the form of a block index table. Each entry includes a block number, starting physical address, ending physical address, memory bank number, center physical coordinates, and a list of neighboring blocks. The list of neighboring blocks is defined according to the Manhattan distance and includes all other block numbers whose Manhattan distance from the center coordinates of the current block is less than or equal to 2.

[0038] Step S3: Based on the wafer-level process parameter information and the historical yield distribution data of the same batch, calculate the defect probability score for each logic test block. The defect probability score is calculated using a weighted fusion model, whose input variables include: the radial position offset of the logic test block on the wafer, the average failure density of its surrounding area in historical tests, the local current density of its metal interconnect layer, and the activation state of its neighboring redundant cells. The radial position offset is obtained by normalizing the Euclidean distance between the wafer center coordinates and the block center coordinates, and its value ranges from 0 to 1. The average failure density is obtained by counting all failure points in a circular area with a radius of 5 blocks centered on the current block and dividing by the total area of ​​the area in the historical yield distribution data of the same batch.

[0039] Local current density is jointly estimated by the power network distribution density and the expected workload, in amperes per square micrometer. The activation state of neighboring redundant units is a Boolean value: 1 if there is an activated redundant unit nearby for replacement, otherwise 0. Each input variable is multiplied by its corresponding weight coefficient, summed, and then mapped to the 0-1 interval using a Sigmoid function to obtain the final defect probability score. The weight coefficients are obtained through offline training. The training data comes from a dataset of all memory chips that have completed FT testing at the same process node within the past 12 months. The training objective is to minimize the cross-entropy loss between the predicted defect probability and the actual failure label. The training process uses a gradient descent optimization algorithm with a learning rate of 0.001, a batch size of 512, and 100,000 iterations. After training, the weight coefficients are stored in the non-volatile memory of the test system for real-time scoring.

[0040] Step S4: Prioritize all logical test blocks according to the defect probability score and generate an initial test sequence. The sorting is in descending order, with the block at the front of the sequence having the highest defect probability score. If multiple blocks have the same score, they are sorted in ascending order by their physical address to ensure determinism. The initial test sequence is stored in a queue structure, supporting a first-in, first-out (FIFO) scheduling strategy. All logical test blocks are loaded during queue initialization, and new blocks are dynamically inserted when extended tests are triggered. To prevent memory overflow due to excessively long test sequences, the system sets a maximum queue length limit. When the queue length reaches the limit, the addition of new test tasks is paused until existing tasks are completed and space is released.

[0041] Step S5: Execute the full-function test instruction set sequentially on each logic test block according to the initial test sequence. The full-function test instruction set includes read / write operations, refresh cycle verification, voltage stress test, and temperature cycle response test. Read / write operations cover single read / write, burst read / write, and page mode access. The address sequence is generated using a pseudo-random generator to ensure uniform address space coverage. Refresh cycle verification tests data retention capability by forcibly entering self-refresh mode and maintaining it for a preset duration before exiting. The voltage stress test adds a ±10% step disturbance to the standard supply voltage for 10 clock cycles to observe signal stability. The temperature cycle response test performs three complete cycles within the range of 0°C to 80°C by adjusting the test equipment's temperature control module. Each cycle includes three stages: heating, holding, and cooling, with data integrity monitored throughout. The full-function test instruction set is generated by the test equipment's vector generator. The test vectors cover all basic operation modes, with a vector depth of 4096 cycles and a clock frequency of 800 MHz. During the test, the power management module synchronously adjusts the core voltage and I / O voltage to simulate power supply conditions under different working scenarios.

[0042] Step S6: During the test, the response signal characteristics of each logic test block are acquired in real time. These characteristics include signal rise time, fall time, eye diagram opening, and bit error rate. The signal rise time is defined as the time required for the DQ signal to rise from 10% amplitude to 90% amplitude, and the fall time is defined as the time required for the signal to fall from 90% amplitude to 10% amplitude. The eye diagram opening is measured by superimposing 1000 consecutive clock cycles of the DQ signal waveform, determining the maximum interference-free window size of the central region of the eye diagram on both the time and voltage axes. The bit error rate is calculated by comparing the expected output data with the actual captured data, determining the ratio of the number of erroneous bits to the total number of transmitted bits. The acquisition of response signal characteristics involves synchronously capturing the DQ signal and control signal output from the probe card using a high-bandwidth oscilloscope channel. The sampling frequency is no less than 2000 MHz, and each acquisition lasts for 10 clock cycles. The acquisition system includes a multi-channel high-speed analog-to-digital converter with a resolution of 8 bits, an effective bit depth of 6.5 bits, and a signal-to-noise ratio of 48 dB. After high-frequency noise is removed by a digital filter, the collected data is sent to the feature extraction module for quantization.

[0043] Step S7: Compare the response signal features with a preset health benchmark model. If the deviation is greater than a first threshold, trigger extended testing of neighboring blocks of the logic test block. If the deviation is greater than a second threshold and the second threshold is greater than the first threshold, immediately terminate the current test process and mark the chip as a defective product. The health benchmark model is a multidimensional Gaussian distribution model. Its mean vector and covariance matrix are statistically derived from the response signal features of good chips under standard test conditions. The model dimension is equal to the number of collected response signal features, i.e., four-dimensional. The mean vector contains the expected values ​​of rise time, fall time, eye diagram opening, and bit error rate. The covariance matrix reflects the correlation between the features. The deviation is measured using Mahalanobis distance. The calculation formula is as follows:

[0044] ;

[0045] This is the feature vector of the response signal of the current test block. This represents the mean vector of the health baseline model. Let covariance matrix be the variance matrix. This is a transpose. The first threshold is set at three standard deviations of the Mahalanobis distance from the healthy baseline model, corresponding to a confidence level of 99.7%. The second threshold is set at five standard deviations of the Mahalanobis distance, corresponding to extreme abnormal states. When When the system queries the list of neighboring blocks of the current test block, it inserts the untested blocks in the list into the tail of the test sequence queue in descending order of their original defect probability scores, and then performs extended testing. When this happens, the system immediately stops all test operations, shuts off the test voltage, releases the probe contacts, marks the chip as a failed product, and records the failure cause code as "signal characteristics are seriously abnormal". The standard deviation is denoted as .

[0046] Step S8: After testing, update the historical yield distribution data for the same batch and feed the test results back to the defect probability scoring module for the next round of testing. Test results include the final state of each logic test block, the response signal feature vector, and the Mahalanobis distance value. The data feedback mechanism uses a sliding window update strategy, retaining only the test data from the most recent 5000 chips for dynamic correction of the historical yield distribution. The update process first writes new data to a temporary buffer, then calculates the cumulative number of failures and the total number of tests for each block within the sliding window, regenerating the average failure density heatmap. This average failure density heatmap overwrites the original historical yield distribution data and serves as input for the next chip test. Data upload uses an encrypted transmission protocol, encrypting the test results using the AES 356-bit encryption algorithm and transmitting them to the central yield analysis server via the TLS 1.3 protocol to ensure data security and integrity.

[0047] Throughout the testing process, the system possesses a comprehensive anomaly handling mechanism. If an abnormal contact resistance is detected during the probe contact phase, the contact operation is repeated up to three times. If it still fails, the chip is skipped and the contact failure event is recorded. If power fluctuations or clock jitter exceeding tolerance occur during test execution, the current test block is paused, and it is retried after the system stabilizes, with a maximum of two retries. If the retry still fails, the current test block is marked as suspicious, and adjacent block extension testing is triggered. All operation logs are recorded on local storage devices, including timestamps, operation types, parameter values, and result status, for subsequent traceability and analysis.

[0048] The division of logical test blocks considers not only physical structure alignment but also test efficiency and fault isolation capabilities. The address range of each block is strictly contiguous to ensure efficient generation of test vectors. Block boundaries are aligned with the memory bank or subarray to avoid introducing additional latency through cross-structure testing. The preset upper limit of 1 million bits is based on a balance between the test equipment's vector cache capacity and the test time budget, ensuring that a single test task can be completed within a reasonable time while avoiding excessive scheduling overhead due to excessively small blocks.

[0049] The input variables of the defect probability scoring model are rigorously screened to ensure that each variable has a physical correlation with the actual defect mechanism. Radial position offset reflects wafer edge effects; edge regions are more prone to thin film inhomogeneities or alignment deviations due to process gradients. Average failure density reflects the persistent impact of local process fluctuations or contamination events. Excessively high local current density may lead to electromigration or hot carrier injection, accelerating device aging. The activation state of neighboring redundant cells is an indirect indicator of potential defects, indicating the presence of unrepairable hard errors in edge regions. Offline training of the weight coefficients ensures the model's generalization ability in a mass production environment, avoiding overfitting to specific batch data.

[0050] The full-featured test instruction set is designed to cover all critical operating modes of the memory chip, ensuring comprehensive functional integrity verification. Voltage stress and temperature cycling tests simulate extreme conditions in real-world use, exposing potential reliability defects. The pseudo-random address sequence of the test vectors prevents fixed patterns from masking address-related faults. High-frequency signal acquisition ensures the capture of nanosecond-level transient anomalies, providing a high-precision data foundation for early defect identification.

[0051] The multidimensional Gaussian assumption of the health benchmark model is based on the central limit theorem, and the response characteristics of a large number of good chips statistically tend to a normal distribution. The use of Mahalanobis distance considers the correlation between features and reflects the degree of anomaly in multidimensional space more accurately than Euclidean distance. A dual-threshold mechanism achieves graded response: minor anomalies trigger local extended testing to avoid missed detections; severe anomalies immediately terminate the test to prevent waste of testing resources.

[0052] A sliding window strategy for data feedback addresses process drift. As the manufacturing process continues, process parameters may change slowly, and older data gradually loses its representativeness. Retaining data from the most recent 5000 wafers ensures that the historical yield distribution always reflects the current process status, keeping the defect probability score timely and accurate.

[0053] In summary, this embodiment constructs a closed-loop, adaptive, and high-precision FT testing method for memory chips through the coordinated execution of steps S1 to S8. After probe contact, the FT testing method dynamically generates a test sequence, prioritizes testing high-risk areas, and intelligently triggers extended tests or failure determinations based on real-time signal characteristics. The results are then fed back to optimize subsequent tests. The entire process ensures defect coverage while reducing redundant testing in low-risk areas, achieving a dual optimization of testing time and cost.

[0054] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0055] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A method for FT testing of memory chips based on probe contact, characterized in that, include: After the probe station completes physical contact with the memory chip, it acquires the wafer-level process parameters, layout and routing topology information, and historical yield distribution data of the same batch of the memory chip. Based on the layout and routing topology information, the memory array of the memory chip is divided into several logical test blocks, and each logical test block corresponds to a set of physical address ranges. Based on the wafer-level process parameter information and the historical yield distribution data of the same batch, calculate the defect probability score for each logic test block; Based on the defect probability score, all logical test blocks are prioritized and an initial test sequence is generated; According to the initial test sequence, a full-function test instruction set is executed sequentially on each logic test block. The full-function test instruction set includes read / write operations, refresh cycle verification, voltage stress test, and temperature cycle response test. During the test, the response signal characteristics of each logic test block are collected in real time. The response signal characteristics include signal rise time, fall time, eye diagram opening degree and bit error rate. The response signal characteristics are compared with a preset health benchmark model. If the deviation is greater than the first threshold, an extended test is triggered on the neighboring blocks of the logic test block. If the deviation is greater than the second threshold and the second threshold is greater than the first threshold, the current test process is terminated immediately and the chip is marked as a defective product. After the test is completed, update the historical yield distribution data of the same batch and feed the test results back to the defect probability score calculation module for the next round of testing; The defect probability score is calculated using a weighted fusion model. The input variables include: the radial position offset of the logic test block on the wafer, the average failure density of the surrounding area in historical tests, the local current density of the metal interconnect layer, and the activation state of the adjacent redundant units. Each input variable is multiplied by its corresponding weight coefficient and then summed. The sum is then mapped to the 0 to 1 interval by the Sigmoid function to obtain the final defect probability score.

2. The FT testing method for memory chips based on probe contact according to claim 1, characterized in that, The wafer-level process parameters include photolithography alignment error, thin film deposition thickness uniformity, surface roughness after chemical mechanical polishing, resistivity of the metal interconnect layer, and breakdown voltage of the dielectric layer.

3. The FT testing method for memory chips based on probe contact according to claim 2, characterized in that, The layout and routing topology information is obtained by parsing the GDSII layout file of the memory chip, including the physical coordinates of each memory cell, the direction of word lines and bit lines, the distribution density of the power network, and the location of the redundancy repair unit.

4. The FT testing method for memory chips based on probe contact according to claim 3, characterized in that, The division of the logical test blocks follows these rules: each block contains a continuous physical address space, and the block boundary is aligned with the physical boundary of the storage volume or subarray; the number of storage units in each block does not exceed a preset upper limit.

5. The FT testing method for memory chips based on probe contact according to claim 4, characterized in that, The weight coefficients were obtained through offline training. The training data came from a dataset of all memory chips that had completed FT testing at the same process node within the past 12 months. The training objective was to minimize the cross-entropy loss between the predicted defect probability and the actual failure label.

6. The FT testing method for memory chips based on probe contact according to claim 5, characterized in that, The execution of the full-function test instruction set is generated by the vector generator of the test machine. The test vectors cover all basic operation modes, including single read / write, burst read / write, page mode access, self-refresh entry and exit, and hold time verification under alternating high and low temperatures.

7. The FT testing method for memory chips based on probe contact according to claim 6, characterized in that, The acquisition of the response signal characteristics is achieved by synchronously capturing the DQ signal and control signal output by the probe card through a high-bandwidth oscilloscope channel.

8. The FT testing method for memory chips based on probe contact according to claim 7, characterized in that, The health benchmark model is a multidimensional Gaussian distribution model. The mean vector and covariance matrix are obtained by statistical analysis of the response signal features of good chips under standard test conditions. The model dimension is equal to the number of response signal features collected.

9. The FT testing method for memory chips based on probe contact according to claim 8, characterized in that, The extended test range of the neighboring blocks is defined by the Manhattan distance. When the central block is determined to be abnormal, a full set of test instructions is executed on all logical test blocks around it with a Manhattan distance of less than or equal to 2.

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