Memory chip processing method and memory chip

Abstract

The application discloses a memory chip processing method and a memory chip, and relates to the technical field of integrated circuits. The memory chip processing method comprises the following steps: providing a memory material and a control crystal grain, wherein the memory material comprises a plurality of memory crystal grains; packaging the memory crystal grains with a first substrate, so that the plurality of memory crystal grains are connected with the first substrate, and a first packaging body is obtained; cutting the first substrate, so that the plurality of memory crystal grains are separated, and a plurality of semi-finished memory modules are obtained, wherein each memory module comprises a memory crystal grain and a sub-substrate arranged on one side of the memory crystal grain, and the sub-substrate is divided from the first substrate; and packaging at least one memory module and the control crystal grain on a second substrate, so that a finished memory chip is obtained, and the control crystal grain is connected with the at least one memory module through a circuit. The memory chip processing method can improve the accuracy of testing and reduce the loss of testing of the memory chip.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a method for fabricating memory chips and a memory chip itself. Background Technology

[0002] Reference Figure 1 A flash wafer contains multiple flash dies arranged at intervals. After testing, the flash dies are classified into qualified and unqualified flash dies based on their capacity or performance.

[0003] During the wafer removal process, memory dies are prone to damage when removed from the memory wafer. Testing the removed dies can also easily cause damage, and even dies that pass testing may be damaged during subsequent packaging, resulting in poor performance of the packaged memory chip. Because the price of finished memory chips fluctuates rapidly, current memory chip manufacturing methods lead to uncontrollable costs, easily resulting in significant profit losses or even losses. Summary of the Invention

[0004] The main objective of this invention is to propose a memory chip fabrication method and a memory chip, aiming to improve the accuracy of testing while reducing the wear and tear on memory chip testing.

[0005] To achieve the above objectives, the present invention proposes a memory chip fabrication method comprising the following steps: Provide memory feedstock and control dies, wherein the memory feedstock includes multiple memory dies; The memory chips are encapsulated with a first substrate to connect multiple memory chips to the first substrate, thereby obtaining a first package. The first substrate has multiple mounting portions, and the multiple memory chips are disposed one-to-one with the multiple mounting portions. The first substrate is cut to separate multiple storage dies, resulting in multiple semi-finished storage modules. Each storage module includes the storage die and a sub-substrate disposed on one side of the storage die, the sub-substrate being formed by dividing the first substrate; and At least one of the memory modules and the control die are packaged on a second substrate to obtain a finished memory chip, wherein the control die is connected to the at least one memory module via a circuit.

[0006] In one embodiment, the memory chip fabrication method further includes: The storage modules were tested and graded. The step of encapsulating at least one of the storage modules and the control die on a second substrate to obtain a finished storage chip, wherein the control die is connected to the at least one storage module via a circuit, specifically: encapsulating multiple storage modules and the control die of the same level on a second substrate to obtain a finished storage chip, wherein the control die is connected to multiple storage modules via a circuit. Alternatively, the process of encapsulating at least one of the memory modules and the control die on a second substrate to obtain a finished memory chip, wherein the control die and the at least one memory module are connected by a circuit, specifically: multiple memory modules of the same level are each encapsulated with a control die on a second substrate to obtain multiple finished memory chips.

[0007] In one embodiment, the second substrate has a control mounting portion, a plurality of leads, and at least one storage mounting portion. At least one storage module and the control die are packaged on the second substrate to obtain the finished storage chip. The control die is connected to the at least one storage module via wiring. The storage module is attached to the corresponding storage mounting part, and the control die is attached to the corresponding control mounting part; All the memory modules are connected to the control chip via conductive leads, and the ports corresponding to the memory modules and the control chip are connected to multiple leads. The entire second substrate is injection molded and packaged to obtain the finished memory chip.

[0008] In one embodiment, the first substrate is a lead frame or a circuit board, and / or the second substrate is a lead frame or a circuit board.

[0009] In one embodiment, the memory material further includes a base film, and a plurality of the memory chips are bonded to the base film; Before encapsulating the memory chips with a first substrate to connect multiple memory chips to the first substrate to obtain a first package, wherein the first substrate has multiple mounting portions and the multiple memory chips are respectively disposed on the multiple mounting portions, the process further includes: Multiple storage dies on the base film are vacuum-lifted and fed using a multi-nozzle module.

[0010] In one embodiment, before packaging the semi-finished storage module and control die, the storage chip processing method further includes: Compatibility testing was performed on the storage module and control chip of the semi-finished product; Based on the tested and qualified storage module and control die, the packaging step of encapsulating at least one of the storage module and control die onto the second substrate to obtain the finished storage chip is then performed.

[0011] This application also provides a method for fabricating a memory chip, including the following steps: The system provides memory feedstock and control dies, wherein the memory feedstock includes a base film and a plurality of memory dies bonded to the base film; The memory chip is packaged with the first substrate so that the side of the multiple memory chips facing away from the blue film is connected to the first substrate to obtain the first package. The first substrate is cut to separate multiple storage dies, resulting in multiple semi-finished storage modules. Each storage module includes the storage die and a sub-substrate disposed on one side of the storage die, the sub-substrate being formed by dividing the first substrate; and At least one of the memory modules and the control die are packaged on a second substrate to obtain a finished memory chip, wherein the control die is connected to the at least one memory module via a circuit.

[0012] In one embodiment, the memory chip fabrication method further includes: The storage modules were tested and graded. The step of encapsulating at least one of the storage modules and the control die on a second substrate to obtain a finished storage chip, wherein the control die is connected to the at least one storage module via a circuit, specifically: encapsulating multiple storage modules and the control die of the same level on a second substrate to obtain a finished storage chip, wherein the control die is connected to multiple storage modules via a circuit. Alternatively, the process of encapsulating at least one of the memory modules and the control die on a second substrate to obtain a finished memory chip, wherein the control die and the at least one memory module are connected by a circuit, specifically: multiple memory modules of the same level are each encapsulated with a control die on a second substrate to obtain multiple finished memory chips.

[0013] In one embodiment, the second substrate has a control mounting portion, a plurality of leads, and at least one storage mounting portion. At least one storage module and the control die are packaged on the second substrate to obtain the finished storage chip. The control die is connected to the at least one storage module via wiring. The storage module is attached to the corresponding storage mounting part, and the control die is attached to the corresponding control mounting part; All the memory modules are connected to the control chip via conductive leads, and the ports corresponding to the memory modules and the control chip are connected to multiple leads. The entire second substrate is injection molded and packaged to obtain the finished memory chip.

[0014] In one embodiment, the first substrate is a lead frame or a circuit board, and / or the second substrate is a lead frame or a circuit board.

[0015] In one embodiment, before packaging the semi-finished storage module and control die, the storage chip processing method further includes: Compatibility testing was performed on the storage module and control chip of the semi-finished product; Based on the tested and qualified storage module and control die, the packaging step of encapsulating at least one of the storage module and control die onto the second substrate to obtain the finished storage chip is then performed.

[0016] In one embodiment, the memory chip is manufactured using the above-described memory chip fabrication method.

[0017] The technical solution of the present invention encapsulates multiple memory chips and a first substrate to obtain a first package. The first package is used to protect the memory chips and prevent damage to the memory chips during subsequent testing and grading as well as during transportation before and after testing and grading.

[0018] By encapsulating multiple memory chips before dicing them, the damage to the memory chips during wafer removal can be avoided in traditional technologies. Furthermore, encapsulating multiple memory chips saves packaging time and costs, and dicing the first substrate to obtain multiple memory modules facilitates the production of memory modules with uniform dimensions and specifications.

[0019] Existing methods directly package storage chips and control chips into finished storage chips. If the storage chip and control chip are incompatible, both the finished storage chip and the storage chip are scrapped. Compared with the existing methods, this application encapsulates at least one storage module and control chip on a second substrate. This allows the storage module and control chip to be separated and replaced with different storage modules, improving the reusability of the storage chip and avoiding cost losses caused by the direct scrapping of the finished storage chip and storage chip. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of the layout of the storage wafer provided by the present invention; Figure 2 A flowchart of the memory chip fabrication method provided by the present invention; Figure 3 This is a schematic diagram of the lead frame provided by the present invention; Figure 4 A schematic diagram showing the position of the storage die mounted on the lead frame, provided by the present invention; Figure 5 A schematic diagram of the layout of the memory chip provided by the present invention; Figure 6 A schematic diagram of the layout of a memory wafer with a base film provided by the present invention; Figure 7 A cross-sectional view of the storage module provided by the present invention; Figure 8 A cross-sectional view of the memory chip provided by the present invention.

[0022] Explanation of icon numbers: 10. Memory wafer; 11. Memory die; 12. Lead frame; 13. Conductive lead; 14. Electrode pad; 15. Lead pad; 16. Chip insulating adhesive; 17. Epoxy resin; 18. Control die; 19. Mounting part; 20. Circuit board; 21. Base film.

[0023] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0024] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0025] It should be noted that if the embodiments of the present invention involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a specific posture. If the specific posture changes, the directional indicators will also change accordingly.

[0026] Furthermore, if the embodiments of this invention involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the use of "and / or" or "and / or" throughout the text includes three parallel solutions. For example, "A and / or B" includes solution A, solution B, or a solution where both A and B are satisfied. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0027] Reference Figure 1 Since the capacity and performance of the storage die 11 are unknown before it is removed from the storage wafer 10, the common practice is to first remove the storage die 11 from the storage wafer 10 through a wafer removal process, then test the storage die 11 according to capacity and performance requirements to obtain qualified storage dies 11, and then package the qualified storage dies 11. This method is prone to damage when removing the storage die 11 from the storage wafer 10, and during the testing process, the protective film on the surface of the storage die 11 may be damaged due to the inaccuracy of the test probes, resulting in damage to the storage die 11. This causes the storage die 11, which was qualified before being removed from the storage wafer 10, to be damaged during the removal and testing process, resulting in poor application performance of the packaged storage die 11, i.e., the finished storage module, and causing significant losses. Because the price of finished storage modules fluctuates rapidly in the industry, and the packaging and processing cycle is long, costs are uncontrollable, which can easily lead to significant loss of profits or even losses.

[0028] Reference Figures 2 to 4 In an embodiment of the present invention, a memory chip manufacturing method is provided, comprising the following steps: Provide memory chips and control dies 18, the memory chips including multiple memory dies 11; The storage chip 11 is encapsulated with the first substrate to connect multiple storage chips 11 to the first substrate to obtain a first package. The first substrate has multiple mounting portions 19, and the multiple storage chips 11 are disposed one-to-one with the multiple mounting portions 19. The first substrate is cut to separate multiple storage dies 11 to obtain multiple semi-finished storage modules. Each storage module includes a storage die 11 and a sub-substrate disposed on one side of the storage die 11. The sub-substrate is divided from the first substrate. At least one memory module and a control chip 18 are packaged on a second substrate to obtain a finished memory chip. The control chip 18 is connected to at least one memory module via a circuit.

[0029] The technical solution of the present invention encapsulates multiple memory chips 11 with a first substrate to obtain a first package. The first package is used to protect the memory chips 11 and prevent damage to the memory chips 11 during subsequent testing and grading as well as during transportation before and after testing and grading.

[0030] By encapsulating multiple memory chips 11 and then dicing them, the damage to the memory chips 11 during wafer removal can be avoided in traditional technologies. In addition, encapsulating multiple memory chips 11 can save encapsulation time and costs, and dicing the first substrate to obtain multiple memory modules makes it easier to obtain memory modules with uniform size and specifications.

[0031] In existing systems, the storage die 11 is directly packaged with the control die 18 to form a finished storage chip. If the storage die 11 and the control die 18 are incompatible, the finished storage chip and the storage die 11 are directly scrapped. Compared with the existing method, this application uses a method of packaging at least one storage module and the control die 18 on a second substrate. This allows the storage module and the control die 18 to be separated, and different storage modules can be replaced, improving the reusability of the storage die 11 and avoiding cost losses caused by the direct scrapping of the finished storage chip and the storage die 11.

[0032] After packaging, the memory chip 11 undergoes testing, including electrical performance testing. This replaces existing technology that directly tests the surface of the memory chip 11 using test probes, which is prone to damaging the protective film on the surface of the memory chip 11 during testing, leading to reduced quality or damage. Furthermore, test probes can only detect 1 / 32 or 1 / 64 of the capacity and performance of the memory chip 11. Electrical performance testing can detect bad blocks inside the memory chip 11 that cannot be detected by probes, enabling the detection of the full capacity and performance of the memory chip 11, improving testing accuracy, and minimizing losses during testing. After testing, qualified memory chips 11 are selected based on capacity and performance. The testing also includes reliability testing.

[0033] In embodiments of the present invention, multiple storage modules are tested and graded; and multiple storage modules of the same grade and a control die 18 are packaged on a second substrate to obtain a finished storage chip. The control die 18 is connected to the multiple storage modules via wiring. Alternatively, multiple storage modules of the same grade and the control die 18 can be packaged on the second substrate, or multiple storage modules of the same grade can be packaged with one control die 18 on the second substrate respectively.

[0034] Multiple storage modules of the semi-finished product are tested and graded to obtain multiple storage modules of the same grade. This ensures that the storage chips in the final storage chip product are within the same grade range, that is, the quality (memory size and performance) is basically the same. This avoids the situation in the existing technology where the storage chip 11 is directly packaged with the control chip 18 into a storage chip product without knowing the capacity and performance of the storage chip 11 of the storage module. If it is found after packaging that the quality of multiple storage chips 11 is different, the storage chip product will not work properly and will be scrapped.

[0035] Existing methods directly package the storage die 11 and control die 18 into a finished memory chip. This requires a process involving probe testing of the storage die 11 and unpacking the packaged memory chip to determine its capacity and class. The entire packaging cycle typically takes 10 to 14 days. The present application's method, which packages the storage die 11 with a first substrate, then tests and grades the resulting diced storage modules, and finally packages multiple storage modules of the same class and the control die 18 onto a second substrate, reduces the entire packaging cycle to 7 to 10 days, shortening it by one-third compared to the previous method. Existing packaging methods are time-consuming, and the rapidly fluctuating prices in the memory chip industry lead to uncontrollable costs. The packaging method provided in this application can reduce and control the production cost of finished memory chips and shorten the packaging cycle, allowing for a more advantageous position and higher profits in the rapidly fluctuating memory chip market.

[0036] In an embodiment of the present invention, the second substrate has a control mounting portion, multiple leads, and multiple storage mounting portions. Multiple storage modules and a control die 18 are packaged on the second substrate to obtain a finished storage chip. The control die 18 is connected to the multiple storage modules via circuitry. The storage module is attached to the corresponding storage mounting part and the control chip 18 is attached to the corresponding control mounting part; All memory modules are connected to the control chip 18 via conductive leads 13, and the ports corresponding to the memory modules and the control chip 18 are connected to multiple leads. The entire second substrate is injection molded and encapsulated to obtain the finished memory chip.

[0037] In embodiments of the present invention, the first substrate is a lead frame 12 or a circuit board 20, and / or the second substrate is a lead frame 12 or a circuit board 20.

[0038] The first substrate has multiple mounting portions 19, and multiple memory chips 11 are disposed one-to-one with each of the multiple mounting portions 19.

[0039] Reference Figure 3 When the first substrate is a lead frame 12, multiple memory chips 11 are connected to the lead frame 12 via conductive leads 13. When the first substrate is a circuit board 20, multiple memory chips 11 are connected to the circuit board 20 via solder paste.

[0040] When the second substrate is the lead frame 12, the storage module and the control chip 18 are connected to the lead frame 12 through the conductive lead 13.

[0041] Reference Figure 7 When the first substrate is a circuit board 20, multiple memory chips 11 are connected to the mounting portion 19 of the circuit board 20 by solder paste.

[0042] Reference Figure 8 When the second substrate is a circuit board 20, reflow soldering can be used to solder the storage module to the pads of the circuit board 20.

[0043] The circuit board 20 mentioned above can be a solid-state drive board such as SATA / PCIE, a BGA board, a UDP board, a TF board, an SD NAND board, a COB board, or an SD card board.

[0044] Reference Figure 4 The storage die 11 has electrode pads 14, and the lead frame 12 has pin pads 15 corresponding to the electrode pads 14. When the first substrate is the lead frame 12, the specific packaging steps for encapsulating the storage die 11 and the first substrate include: attaching the storage die 11 to the mounting portion 19 of the lead frame 12, connecting the storage die 11 and the lead frame 12 through conductive leads 13, and performing injection molding encapsulation on the storage die 11 and the lead frame 12 as a whole to obtain the first package.

[0045] The bonding of the storage die 11 to the mounting portion 19 of the lead frame 12 specifically includes: placing the storage die 11 on the mounting portion 19 of the lead frame 12; and baking and curing the storage die 11 and the lead frame 12 to firmly bond the storage die 11 and the lead frame 12. The baking and curing process includes placing the storage die 11 in a high-temperature oven at 120-150°C for 2-4 hours to remove residual moisture from the storage die 11.

[0046] Before baking and curing the storage die 11 and the lead frame 12, a hot-pressing process is used to bond the storage die 11 and the lead frame 12 together. This prevents changes in their relative positions during the transfer to the high-temperature oven, which could affect the baking and curing process and ensure a firm bond between the storage die 11 and the lead frame 12. The hot-pressing process can be performed using a die bonder, with a pressure of 5-10 MPa, a temperature of 180-220℃, and a holding time of 10-20 seconds.

[0047] Before baking and curing the memory die 11 and lead frame 12, a chip insulating adhesive 16 is applied to the pin pads 15 using a dispensing machine. This ensures that after the memory die 11 is placed on the mounting portion 19 of the lead frame 12, the chip insulating adhesive 16 fills the gap between the memory die 11 and the lead frame 12. The thermal conductivity of the chip insulating adhesive 16 is required to be no less than 50 W / (m·K). (Refer to...) Figure 4 Chip insulating adhesive 16 is filled in the gap between the storage die 11 and the lead frame 12.

[0048] The memory chip 11 and the lead frame 12 are connected via conductive leads 13. This involves using a wire bonder to connect the electrode pads 14 of the memory chip 11 to the pin pads 15 of the lead frame 12 via the conductive leads 13. The conductive leads 13 can be gold or silver wires. The pin pads 15 have multiple pins, and the pin surfaces are coated with an anti-oxidation coating. The connection point between the conductive leads 13 and the memory chip 11 is located on the pin pads 15 of the lead frame 12, thus achieving an electrical signal connection between the memory chip 11 and the lead frame 12.

[0049] The storage die 11 and the lead frame 12 are integrally injection molded to obtain a first package. This includes using an encapsulation machine to encapsulate the storage die 11 and the conductive lead 13 with encapsulation materials such as epoxy resin 17 to form an encapsulation layer, and then curing it at high temperature to form the first package. The first package can strengthen the connection between the storage die 11 and the lead frame 12, and protect the storage die 11 from external dust and condensation contact with the storage die 11, which could lead to the failure of the storage die 11 or affect the storage performance.

[0050] When the second substrate is the lead frame 12, multiple memory modules and control chips 18 are connected to the lead frame 12 through conductive leads 13.

[0051] When the first substrate is a circuit board 20, multiple memory chips 11 are connected to the mounting portion 19 of the circuit board 20 via solder paste. Specifically, a pick-and-place machine is used to mount the multiple memory chips 11 onto the mounting portion 19 of the circuit board 20 with a pressure of 0.1-1N, to prevent damage to the memory chips 11 and to avoid solder paste displacement caused by compression during mounting onto the mounting portion 19 of the circuit board 20.

[0052] When the second substrate is a circuit board 20, reflow soldering can be used to solder the memory module to the pads of the circuit board 20.

[0053] The circuit board 20 mentioned above can be an ASTA board, BGA board, UDP board, TF board, SD NAND board, COB board, or SD card board.

[0054] In an embodiment of the present invention, reference is made to Figure 6 The incoming memory materials also include a memory wafer 10 with a base film 21, and multiple memory chips 11 are bonded to the base film 21; Before encapsulating the memory chips 11 with the first substrate to connect multiple memory chips 11 to the first substrate to obtain a first package, wherein the first substrate has multiple mounting portions 19 and the multiple memory chips 11 are respectively disposed on the multiple mounting portions 19, the process further includes: Multiple memory chips 11 on the base film 21 are vacuum-lifted and unloaded using a multi-nozzle module. Vacuum lifting avoids damage to the chips during the wafer unloading process, a technique employed in existing technologies. The multi-nozzle module also includes ejector pins. The nozzles are located above the chips, and the ejector pins are located below the chips and closer to the base film 21. The ejector pins lift the base film 21, and the nozzles of the multi-nozzle module grip the memory chips 11, thus detaching the memory chips 11 from the base film 21. The base film 21 can be a blue film.

[0055] In embodiments of the present invention, testing and classifying multiple storage modules includes: The memory size of each storage module was tested to obtain storage modules with different memory sizes; Storage modules of different memory sizes are classified into different levels, resulting in multiple levels of storage modules.

[0056] In an embodiment of the present invention, before packaging the semi-finished storage module and control die 18, the storage chip processing method further includes: Compatibility testing was performed on the semi-finished storage module and control chip 18; Based on the tested and qualified memory modules and control chips 18, the packaging step of encapsulating multiple memory modules and control chips 18 of the same level onto a second substrate is then performed to obtain the finished memory chip.

[0057] In existing technologies, after packaging and testing the memory chip 11 and control chip 18, if the test reveals incompatibility between the memory chip and control chip 18, and the memory chip has already been molded and cured together with the control chip 18, the memory chip must be scrapped. The technical solution of this application performs compatibility testing on the semi-finished memory module and control chip 18. If each of multiple memory modules of the same level is found to be compatible with the control chip 18, then injection molding is performed to cure and form a finished memory chip product containing both the memory module and control chip 18. If one of the multiple memory modules of the same level is found to be incompatible with the control chip 18, the memory module can be removed from the circuit board 20 and replaced with another memory module of the same level until a memory module compatible with the control chip 18 is found. If each of the multiple memory modules of the same level is found to be incompatible with the control chip 18, the memory module can be removed from the circuit board 20 and replaced with multiple memory modules of other levels until a memory module of another level compatible with the control chip 18 is found. By adopting this solution, the reusability of storage modules and storage chips 11 can be improved, and the losses caused by scrapping due to storage module compatibility issues can be minimized.

[0058] In an embodiment of the present invention, the control die 18 is a control chip.

[0059] In an embodiment of the present invention, the present invention also provides a method for manufacturing a memory chip, comprising the following steps: The system provides memory chips and control dies 18. The memory chips include a base film 21 and multiple memory dies 11 bonded to the base film 21. The memory chip is packaged with the first substrate so that the side of the multiple memory chips 11 facing away from the blue film is connected to the first substrate to obtain the first package. The first substrate is cut to separate multiple storage dies 11 to obtain multiple semi-finished storage modules. Each storage module includes a storage die 11 and a sub-substrate disposed on one side of the storage die 11. The sub-substrate is divided from the first substrate. At least one memory module and a control chip 18 are packaged on a second substrate to obtain a finished memory chip. The control chip 18 is connected to at least one memory module via a circuit.

[0060] The technical solution of the present invention encapsulates a plurality of memory dies 11 bonded to a base film 21 with a first substrate to obtain a first package. The first package protects the memory dies 11 bonded to the base film 21, preventing damage to the memory dies 11 during subsequent testing and grading, as well as during transportation before and after testing and grading. In some embodiments, the memory material can be the entire memory wafer 10 or a part of the memory wafer 10, see reference. Figure 6 The storage die 11 of the storage wafer 10 is bonded to the base film 21.

[0061] By encapsulating and then cutting multiple memory chips 11 bonded to the base film 21, the damage to the memory chips 11 during wafer removal can be avoided in traditional technologies. In addition, encapsulating multiple memory chips 11 can save encapsulation time and costs, and cutting the first substrate to obtain multiple memory modules makes it easier to obtain memory modules with uniform size and specifications.

[0062] In existing systems, the storage die 11 is directly packaged with the control die 18 to form a finished storage chip. If the storage die 11 and the control die 18 are incompatible, the finished storage chip and the storage die 11 are directly scrapped. Compared with the existing method, this application uses a method of packaging at least one storage module and the control die 18 on a second substrate. This allows the storage module and the control die 18 to be separated, and different storage modules can be replaced, improving the reusability of the storage die 11 and avoiding cost losses caused by the direct scrapping of the finished storage chip and the storage die 11.

[0063] The method involves packaging the memory chip 11 before testing, including electrical performance testing. This replaces existing technology that directly tests the surface of the memory chip 11 using test probes, which is prone to damaging the protective film on the surface of the memory chip 11 during testing, leading to reduced quality or damage. Electrical performance testing can detect bad blocks inside the memory chip 11 that cannot be detected by probes, improving testing accuracy and minimizing losses during the testing process. After testing, qualified memory chips 11 are selected based on capacity and performance. The testing also includes reliability testing.

[0064] In embodiments of the present invention, multiple storage modules are tested and graded; and multiple storage modules of the same grade and a control die 18 are packaged on a second substrate to obtain a finished storage chip. The control die 18 is connected to the multiple storage modules via wiring. Alternatively, multiple storage modules of the same grade and the control die 18 can be packaged on the second substrate, or multiple storage modules of the same grade can be packaged with one control die 18 on the second substrate respectively.

[0065] Multiple storage modules of the semi-finished product are tested and graded to obtain multiple storage modules of the same grade. This ensures that all storage modules and storage chips in the final storage chip product are within the same grade range, that is, the quality (memory size and performance) is basically the same. This avoids the situation in the existing technology where multiple storage modules are directly packaged with the control chip 18 into a storage chip product without knowing the capacity and performance of the storage chip 11 of the storage module. If the quality of the storage chip 11 of the storage module is found to be different after packaging, including different grades, the storage chip product will not work properly and will be scrapped.

[0066] In an embodiment of the present invention, the second substrate has a control mounting portion (not shown), multiple leads, and multiple storage mounting portions (not shown). Multiple storage modules and a control die 18 are packaged on the second substrate to obtain a finished storage chip. The control die 18 is connected to the multiple storage modules via circuitry, including: The storage module is attached to the corresponding storage mounting part and the control chip 18 is attached to the corresponding control mounting part; All memory modules are connected to the control chip 18 via conductive leads 13, and the ports corresponding to the memory modules and the control chip 18 are connected to multiple leads. The entire second substrate is injection molded and encapsulated to obtain the finished memory chip.

[0067] In embodiments of the present invention, the first substrate is a lead frame 12 or a circuit board 20, and / or the second substrate is a lead frame 12 or a circuit board 20.

[0068] When the first substrate is a lead frame 12, multiple memory chips 11 are connected to the lead frame 12 via conductive leads 13. When the first substrate is a circuit board 20, multiple memory chips 11 are connected to the circuit board 20 via solder paste.

[0069] Reference Figure 4 The memory chip 11 has electrode pads 14, and the lead frame 12 has pin pads 15 corresponding to the electrode pads 14. When the first substrate is the lead frame 12, the specific steps for encapsulating the multiple memory chips 11 bonded to the base film 21 with the first substrate to obtain the first package are the same as the specific encapsulation steps for encapsulating the memory chips 11 with the first substrate described above, and will not be repeated here.

[0070] When the second substrate is the lead frame 12, the storage module and the control chip 18 are connected to the lead frame 12 through the conductive lead 13.

[0071] When the first substrate is a circuit board 20, multiple memory chips 11 are connected to the mounting portion 19 of the circuit board 20 by solder paste.

[0072] When the second substrate is a circuit board 20, reflow soldering can be used to solder the memory module to the pads of the circuit board 20.

[0073] The circuit board 20 mentioned above can be a solid-state drive board such as SATA / PCIE, a BGA board, a UDP board, a TF board, an SD NAND board, a COB board, or an SD card board.

[0074] In existing technologies, the storage chip 11 is typically packaged together with the control chip 18 on a customized circuit board. The wiring of the customized circuit board is designed for a specific storage protocol and cannot flexibly adapt to different interface standards. If support for different storage protocols is required, the circuit board needs to be redesigned, resulting in a long development cycle and high cost. The second substrate of this application can support different storage protocols by adjusting the pad connection method, thereby adapting to different storage application scenarios such as flash drives, mobile hard drives, and memory cards, and reducing the development cycle and cost.

[0075] Adjusting pad connection methods includes: adding or removing pads to match the pin requirements of different storage protocols; selectively connecting or disconnecting pads to achieve flexible switching of signal paths; and enabling pads to support different signal definitions through protocol switching or software configuration.

[0076] In embodiments of the present invention, testing and classifying multiple storage modules includes: The memory size of each storage module was tested to obtain storage modules with different memory sizes; Storage modules of different memory sizes are classified into different levels, resulting in multiple levels of storage modules.

[0077] In an embodiment of the present invention, before packaging the semi-finished storage module and control die 18, the storage chip processing method further includes: Compatibility testing was performed on the semi-finished storage module and control chip 18; Based on the tested and qualified memory modules and control chips 18, the packaging step of encapsulating multiple memory modules and control chips 18 of the same level onto a second substrate is then performed to obtain the finished memory chip.

[0078] In existing technologies, after packaging and testing the memory chip 11 and control chip 18, if the test reveals incompatibility between the memory chip and control chip 18, and the memory chip has already been molded and cured together with the control chip 18, the memory chip must be scrapped. The technical solution of this application performs compatibility testing on the semi-finished memory module and control chip 18. If each of multiple memory modules of the same level is found to be compatible with the control chip 18, then injection molding is performed to cure and form a finished memory chip product containing both the memory module and control chip 18. If one of the multiple memory modules of the same level is found to be incompatible with the control chip 18, the memory module can be removed from the circuit board 20 and replaced with another memory module of the same level until a memory module compatible with the control chip 18 is found. If each of the multiple memory modules of the same level is found to be incompatible with the control chip 18, the memory module can be removed from the circuit board 20 and replaced with multiple memory modules of other levels until a memory module of another level compatible with the control chip 18 is found. By adopting this solution, the reusability of storage modules and storage chips 11 can be improved, and the losses caused by scrapping due to storage module compatibility issues can be minimized.

[0079] In an embodiment of the present invention, a storage module having storage dies 11 of the same level is cut. The cutting includes edge trimming to remove excess material and ensure that the size and shape of the storage module of the same level meet the design requirements.

[0080] In an embodiment of the present invention, the surface of the first package having the same level of storage die 11 is etched with information such as product model, batch number, and manufacturer identification using a laser marking machine, so as to facilitate the identification and traceability of storage modules of the same level.

[0081] Reference Figure 5 and Figure 8 In an embodiment of the present invention, the present invention also provides a memory chip manufactured using the memory chip processing method described above.

[0082] The above description is merely an exemplary embodiment of the present invention and does not limit the scope of patent protection of the present invention. Any equivalent structural transformations made using the contents of the present invention's specification and drawings under the technical concept of the present invention, or direct / indirect applications in other related technical fields, are included within the scope of patent protection of the present invention.

Claims

1. A method for fabricating a memory chip, characterized in that, Includes the following steps: Provide memory feedstock and control dies, wherein the memory feedstock includes multiple memory dies; The memory chips are encapsulated with a first substrate to connect multiple memory chips to the first substrate, thereby obtaining a first package. The first substrate has multiple mounting portions, and the multiple memory chips are disposed one-to-one with the multiple mounting portions. The first substrate is cut to separate multiple storage dies, resulting in multiple semi-finished storage modules. Each storage module includes the storage die and a sub-substrate disposed on one side of the storage die, the sub-substrate being formed by dividing the first substrate; and At least one of the memory modules and the control die are packaged on a second substrate to obtain a finished memory chip, wherein the control die is connected to the at least one memory module via a circuit.

2. The memory chip fabrication method as described in claim 1, characterized in that, The memory chip fabrication method further includes: The storage modules were tested and graded. The step of encapsulating at least one of the storage modules and the control die on a second substrate to obtain a finished storage chip, wherein the control die is connected to the at least one storage module via a circuit, specifically: encapsulating multiple storage modules and the control die of the same level on a second substrate to obtain a finished storage chip, wherein the control die is connected to multiple storage modules via a circuit. Alternatively, the process of encapsulating at least one of the memory modules and the control die on a second substrate to obtain a finished memory chip, wherein the control die and the at least one memory module are connected by a circuit, specifically: multiple memory modules of the same level are each encapsulated with a control die on a second substrate to obtain multiple finished memory chips.

3. The memory chip fabrication method as described in claim 1, characterized in that, The second substrate has a control mounting portion, multiple leads, and at least one storage mounting portion. At least one storage module and the control die are packaged on the second substrate to obtain the finished storage chip. The control die is connected to the at least one storage module via a circuit, including: The storage module is attached to the corresponding storage mounting part, and the control die is attached to the corresponding control mounting part; All the memory modules are connected to the control chip via conductive leads, and the ports corresponding to the memory modules and the control chip are connected to multiple leads. The entire second substrate is injection molded and packaged to obtain the finished memory chip.

4. The memory chip fabrication method as described in claim 1, characterized in that, The first substrate is a lead frame or a circuit board, and / or the second substrate is a lead frame or a circuit board.

5. The memory chip fabrication method as described in claim 1, characterized in that, The memory material also includes a base film, and multiple memory chips are bonded to the base film; Before encapsulating the memory chips with a first substrate to connect multiple memory chips to the first substrate to obtain a first package, wherein the first substrate has multiple mounting portions and the multiple memory chips are respectively disposed on the multiple mounting portions, the process further includes: Multiple storage dies on the base film are vacuum-lifted and fed using a multi-nozzle module.

6. The memory chip fabrication method as described in claim 1, characterized in that, Before packaging the semi-finished storage module and control die, the storage chip processing method further includes: Compatibility testing was performed on the storage module and control chip of the semi-finished product; Based on the tested and qualified storage module and control die, the packaging step of encapsulating at least one of the storage module and control die onto the second substrate to obtain the finished storage chip is then performed.

7. A method for fabricating a memory chip, characterized in that, Includes the following steps: The system provides memory feedstock and control dies, wherein the memory feedstock includes a base film and a plurality of memory dies bonded to the base film; The memory chip is packaged with the first substrate so that the side of the multiple memory chips facing away from the blue film is connected to the first substrate to obtain the first package. The first substrate is cut to separate multiple storage dies, resulting in multiple semi-finished storage modules. Each storage module includes the storage die and a sub-substrate disposed on one side of the storage die, the sub-substrate being formed by dividing the first substrate; and At least one of the memory modules and the control die are packaged on a second substrate to obtain a finished memory chip, wherein the control die is connected to the at least one memory module via a circuit.

8. The memory chip fabrication method as described in claim 7, characterized in that, The memory chip fabrication method further includes: The storage modules were tested and graded. The step of encapsulating at least one of the storage modules and the control die on a second substrate to obtain a finished storage chip, wherein the control die is connected to the at least one storage module via a circuit, specifically: encapsulating multiple storage modules and the control die of the same level on a second substrate to obtain a finished storage chip, wherein the control die is connected to multiple storage modules via a circuit. Alternatively, the process of encapsulating at least one of the memory modules and the control die on a second substrate to obtain a finished memory chip, wherein the control die and the at least one memory module are connected by a circuit, specifically: multiple memory modules of the same level are each encapsulated with a control die on a second substrate to obtain multiple finished memory chips.

9. The memory chip fabrication method as described in claim 7, characterized in that, The second substrate has a control mounting portion, multiple leads, and at least one storage mounting portion. At least one storage module and the control die are packaged on the second substrate to obtain the finished storage chip. The control die is connected to the at least one storage module via a circuit, including: The storage module is attached to the corresponding storage mounting part, and the control die is attached to the corresponding control mounting part; All the memory modules are connected to the control chip via conductive leads, and the ports corresponding to the memory modules and the control chip are connected to multiple leads. The entire second substrate is injection molded and packaged to obtain the finished memory chip.

10. The memory chip fabrication method as described in claim 7, characterized in that, The first substrate is a lead frame or a circuit board, and / or the second substrate is a lead frame or a circuit board.

11. The memory chip fabrication method as described in claim 7, characterized in that, Before packaging the semi-finished storage module and control die, the storage chip processing method further includes: Compatibility testing was performed on the storage module and control chip of the semi-finished product; Based on the tested and qualified storage module and control die, the packaging step of encapsulating at least one of the storage module and control die onto the second substrate to obtain the finished storage chip is then performed.

12. A memory chip, characterized in that, It is manufactured using the memory chip fabrication method as described in any one of claims 1 to 6 or any one of claims 7 to 11.

Images