172 results about "Internal memory" patented technology

The embodiment of the invention discloses an internal memory, a chip and related electronic equipment. A target computing unit of the internal memory comprises a plurality of groups of primary multipliers, a plurality of adder trees and a plurality of secondary multipliers, one group of first-level multipliers is connected with one second-level multiplier through one adder tree; the group of first-level multipliers comprises a plurality of pairs of first multipliers, and each adder tree comprises a first adder, a second adder and a third adder; each pair of first multipliers respectively receive data to perform multiplication operation, and respectively input output results into the first adder to perform addition operation; each second adder receives the output results of the plurality of first adders or the second adder at the upper level to carry out addition operation, and respectively inputs the output results to the second adder at the lower level or the third adder; and each third adder receives the output results of the plurality of second adders to carry out addition operation, and inputs the output results to the secondary multiplier to carry out multiplication operation. By implementing the embodiment of the invention, the memory computing capability can be improved.

The invention provides a data processing method and device of a processor, equipment, a medium and a program product. The method comprises the steps of loading an mth data block in a first matrix to a first cache position of an internal memory through a first thread in a thread group of a processor, and loading an nth data block in a second matrix to a second cache position of the internal memory; loading the (n + 1) th data block in the second matrix from the external memory to a third cache position of the internal memory through the first thread, and performing multiplication operation on the data blocks in the first cache position and the data blocks in the second cache position through the second thread; and loading the (n + 1) th data block in the second matrix from the internal memory to a second cache position of the internal memory through the first thread, and performing multiplication operation on the data block in the first cache position and the data block in the third cache position through the second thread. According to the invention, the calculation speed of multiplication in the processor can be improved.

Methods for producing and validating RFID transponders (e.g., ISO 11784 / 11785 compliant transponders) with identification number authentication capabilities. A signature indicator and a partial-signature trailer are introduced to the ISO telegram. An encrypted signature or partial signature is introduced to the internal memory of ISO compliant transponders. The encrypted signature can prevent fraudulent duplications of ISO 11784 / 11785 transponders by allowing users to securely validate the transponders' authenticity.

The invention discloses a diagnostic reasoning RAG system for resisting retrieval noise based on a self-generated knowledge base, and the system comprises a knowledge retrieval module which carries out the retrieval from an external knowledge base according to a user question to obtain a plurality of target text blocks; the evaluation generation module is used for independently evaluating each target text block through an evaluation model so as to identify retrieval noise, generating a correlation judgment result and a noise degree judgment result of each target text block, and generating internal memory information as a self-generated knowledge base based on a user question; and the diagnosis reasoning module is used for integrating the user question, each target text block, the corresponding correlation judgment result, the noise degree judgment result and the internal memory information into enhanced prompt information and inputting the enhanced prompt information into a large language model to generate a diagnosis reasoning answer. According to the method, retrieval noise interference can be effectively resisted, model knowledge support is strengthened by means of the self-generated knowledge base, the precision and timeliness of medical diagnosis reasoning are improved, and the requirements of the medical field for high-precision and strong-timeliness clinical decision making are met.

A modem chip receives a codeword including a transport block composed of a plurality of code blocks, and includes a hybrid automatic repeat request (HARQ) processing circuit configured to perform a HARQ-based processing operation with respect to the codeword, and an internal memory configured to store data generated by the HARQ processing circuit. The HARQ processing circuit includes a code block processing circuit configured to decode the plurality of code blocks in units of code blocks and perform a first cyclic redundancy check on each of the decoded plurality of code blocks, and a codeword processing circuit configured to perform a second cyclic redundancy check on a decoded transport block.

A compute tile includes a WCB that receives a workload of writing an output tensor of a convolution into a local memory of the compute tile. The local memory may be a SRAM. The WCB receives write transactions. A write transaction includes a data block, which is a part of the output tensor, and metadata describing one or more attributes of the data block. The WCB may store write transactions in its internal buffers. The WCB may determine whether to combine two write transactions, e.g., based on an operation mode or metadata in the write transactions. In embodiments where the WCB determines to combine the two write transactions, the WCB may combine the two write transactions into a new write transaction and write the new write transaction into the local memory or an internal memory of the WCB. The total number of write transactions for the workload can be reduced.

Disclosed in the embodiments of the present application are an internal memory, a chip and a related electronic device. A target processing unit (202) of an internal memory (102) comprises a plurality of groups of primary multipliers, a plurality of adder trees and a plurality of secondary multipliers, wherein one group of primary multipliers is connected to one secondary multiplier by means of one adder tree; one group of primary multipliers comprises a plurality of pairs of first multipliers; each adder tree comprises a first adder, a second adder and a third adder; each pair of first multipliers separately receives data to perform multiplication operations, and separately inputs output results into one first adder for addition operations; each second adder receives output results of a plurality of first adders or the upper-level second adder, so as to perform addition operations, and separately inputs the output results into the lower-level second adder or one third adder; and each third adder receives output results of a plurality of second adders to perform addition operations, and inputs the output results into one secondary multiplier for multiplication operations. Implementing the embodiments of the present application can improve the processing capability of the internal memory.

The invention relates to the technical field of heat dissipation, in particular to the technical field of heat dissipation of personal computers, workstations and servers, and particularly relates to an open type air duct memory radiator. The radiator comprises radiating fins, a limiting component and a heat-conducting medium, wherein the radiating fins, the limiting component and the heat-conducting medium surround a memory bank to form an open air duct. The cooling fins are symmetrically arranged on the two sides of the memory bank; the limiting component is arranged between the two cooling fins and abuts against the top of the memory bank. And the heat-conducting medium is arranged on a memory chip of the memory bank and is in contact with the inner surfaces of the adjacent cooling fins. According to the internal memory radiator, internal accumulated heat is reduced through the open air duct, and the air flowing efficiency is improved; and heat generated during operation of the memory bank is directly conducted to the cooling fins through the heat-conducting medium, so that the heat conduction efficiency is improved. The flow guide type design of an open type air channel is combined with the direct heat conduction design, efficient heat dissipation is achieved, and stable operation of the memory bank is guaranteed.

The embodiment of the invention provides a security defense method and device based on Hypervisor, and relates to the technical field of virtualization. The method comprises the steps of determining a memory processing type in response to a preset trigger operation; and calling an hvc command by calling a virtual machine monitor corresponding to the memory processing type so as to indicate a Hypervisor to execute a Hypervisor processing function corresponding to the hvc command. According to the embodiment of the invention, the distribution or release of the internal memory of the process is realized through the Hypervisor with higher authority, even if the kernel of the operating system is broken by a malicious application program, the integrity of a security mechanism of the operating system can still be ensured, and the effective defense of security threats of the operating system is realized.

A processor, method, and non-transitory computer-readable storage medium for processing template data and search data according to a search window applied to the search data. The search window comprising a set of offset positions. The processing is performed by a block matching engine (BME) that produces a tensor with difference values, and a convolutional engine (CE) that performs a convolutional operation on the tensor. The processing is performed in an iterative interleaved fashion, by dividing the set of offset positions into a plurality of subsets of offset positions. In parallel with processing of the first X offset positions by the CE, the BME generates the next X channels of the tensor, and which are subsequently pipelined through to the CE via an internal storage, etc.

A method and apparatus of direct memory access DMA between accelerator cards, an accelerator card, an accelerating platform and a non-volatile readable storage medium. The first accelerator card according to the present application can initiatively perform the initiation of the DMA, and, according to the idle-internal-memory datum of the second accelerator card as the data destination terminal recorded in the first accelerator card itself, write the datum directly into the internal memory of the second accelerator card in the mode of DMA, which does not require inquiring the idle-internal-memory address of the second accelerator card before the DMA, and does not require waiting for the second accelerator card to initiate the DMA. The solution realizes the direct DMA writing operation between different accelerator cards at the hardware level, and solves the problem in DMA operation between accelerator cards.

The present disclosure relates to a skew resistance PID device and a processing method, and the device includes: Dual In-line Memory Modules (DIMMs) composed of multiple ranks respectively having multiple banks, and In-DIMM Processors (IDPs) that process internal memory operations; a memory controller; and a host CPU connected to the memory module through the memory controller and configured to enhance parallel processing performance of the IDPs by replicating a join key in units of bank sets and rank sets.

Even when the processing result at a certain layer in a convolutional neural network is input to the next layer and further subsequent layers, the processing can be executed more appropriately. A subnetwork included in a convolutional neural network includes a first layer, a second layer, a third layer, and a fourth layer, the output of the first layer is input to the second layer, the output of the second layer is input to the third layer, and the output of the first layer and the output of the third layer are input to the fourth layer, the acquisition unit divides and acquires the data to be processed so that the total size of the input data to each layer is equal to or less than the storage capacity of the internal memory.

Encryption system with an application-specific integrated circuit (ASIC) which has a permanent memory for the non-volatile storage of the operating system (OS) of a processor and software modules for encrypting the data memory of the processor and which has a hardware-implemented encryption algorithm, characterized in that a security module (SM) is integrated in the ASIC for autonomous booting of the operating system (OS), consisting of: - a symmetric cryptosystem (SK) for processing symmetric keys, - an asymmetric cryptosystem (AK) for the use of public and private keys, - a module for generating cryptographic hash functions (KH), - a module for the secure exchange of keys using hardware-implemented key exchange protocols (SP), - a key storage (SS) for the secure storage of root keys (WS), which are protected by appropriate measures in the physical structures of the ASIC and - a key management system (SMS) for the secure introduction of authenticated-encrypted key packets, and that the security module (SM) communicates with a central processing unit (CPU) via a communication interface (CS1), and that the central processing unit (CPU) communicates with at least one internal storage (IS) and one external storage (ES), as well as with at least one internal persistent storage (IP) and one external persistent storage (EP), such that the operating system (OS) is loaded by a second-stage bootloader (SSB) stored in the external persistent storage (EP), and then the operating system (OS) loads the applications, the second-stage bootloader (SSB) itself being decrypted and loaded by a first-stage bootloader (FSB) stored in the internal persistent storage (IP), and a public key (PUBOS) to verify the operating system (OS).and a symmetric key (KOS) to decrypt the operating system (OS), and that the contents of the internal memory (IS) and the external memory (ES) are decrypted by the security module (SM) during read accesses by the central management unit (CMU) or other modules integrated on the ASIC, and re-encrypted during write accesses by the same.

A system and an accelerator circuit includes an internal memory to store data received a memory associated with a processor and a filter circuit block comprising a plurality of circuit stripes, each circuit stripe including a filter processor, a plurality of filter circuits, and a slice of the internal memory assigned to the plurality of filter circuits, where the filter processor is to execute a filter instruction to read data values from the internal memory based on a first memory address, for each of the plurality of circuit stripes: load the data values in weight registers and input registers associated with the plurality of filter circuits of the circuit stripe to generate a plurality of filter results, and write a result generated using the plurality of filter circuits in the internal memory at a second memory address.

The invention discloses a tobacco leaf modified atmosphere insecticidal system and method in a roadway type dense shelf warehouse based on flexible parameter configuration. The system comprises a roadway sealing subsystem, a gas regulation and control subsystem, an environment monitoring subsystem and a central control subsystem. A memory is arranged in an industrial computer of the central control subsystem, and a flexible parameter database and a flexible parameter configuration module are stored in the memory. The method comprises the following steps: sealing a roadway to form an independent modified atmosphere insecticidal unit, calling a first parameter set and a second parameter set according to input insecticidal object information, performing gas replacement and maintenance control according to the second parameter set, and dynamically triggering trace nitrogen supplementation, carbon dioxide supplementation, linkage temperature adjustment and linkage humidity adjustment deviation correction control based on real-time monitoring data. According to the method, one-product-one-strategy precise insect killing for different tobacco leaf materials is achieved, the problems of fixed parameters and poor adaptability of a traditional process are solved, and the method has the advantages of being thorough in insect killing, good in quality guarantee and low in energy consumption.

The invention relates to a memory device and an operating method thereof. According to an embodiment of the present disclosure, an operating method of a memory device including a memory bank including a plurality of edge memory cell arrays and a plurality of internal memory cell arrays arranged between the plurality of edge memory cell arrays may be provided. The operating method may include: receiving a fine-grained refresh command; identifying a refresh target pointer value for a refresh target determination list, the refresh target determination list including a plurality of row addresses of the memory bank; identifying a pointing row address corresponding to a refresh target pointer value among the plurality of row addresses; determining a first memory cell array type corresponding to the pointing row address; and performing a first refresh operation for a refresh target number of fine-grained refresh target row addresses, wherein the refresh target number is determined based on the first memory cell array type.

The present application provides a kind of alternative video data compression method, video specification conversion integrated circuit and operating method.Video specification conversion integrated circuit includes input interface, specification conversion engine, internal memory, decompression circuit and output interface.Specification conversion engine receives input video signal from input interface.In specification conversion mode, specification conversion engine converts input video signal meeting first video specification into converted video signal meeting second video specification, and output interface selects converted video signal as output video signal and outputs to display.In standby mode, decompression circuit decompresses the alternative video data of internal memory to generate alternative video signal, and output interface selects alternative video signal as output video signal and outputs to display.

The invention discloses a low-coherence interference microstructure rapid measurement method based on an FPGA, and the method comprises the steps: enabling the FPGA to respectively receive image data and single-point light intensity data collected by a CMOS sensor and a photoelectric detector, and transmitting the two types of data to an FPGA chip internal memory; a parallel pipeline architecture of the FPGA is designed, so that interference pattern contrast can be calculated in real time and displacement point-by-point calculation can be completed while a series of image data and photoelectric detector interference analog signals are received, and the processing efficiency is remarkably improved; and calculating the position of an interference envelope peak value by adopting a gravity center method, completing three-dimensional shape detection of the microstructure, and realizing three-dimensional shape reconstruction. According to the method, the processing speed of low-coherence interference measurement can be effectively increased, the microstructure morphology can be restored at a high speed, and online detection application of low-coherence interference in the fields of semiconductor packaging, lithium battery manufacturing, ultra-precision machining and the like is facilitated.

The application provides a magnetic resonance spectrum reconstruction method based on a local signal block structured low-rank matrix, and relates to magnetic resonance spectrum, and comprises the following steps: 1) establishing a magnetic resonance spectrum reconstruction model based on a local signal block structured matrix; 2) establishing a reconstruction model of an improved reconstruction model without singular value decomposition; 3) establishing a solution algorithm of the improved reconstruction model without singular value decomposition; and 4) performing two-dimensional Fourier transform on the obtained reconstructed time domain signal to obtain a final magnetic resonance spectrum. According to the technical scheme, a small-scale structured matrix is constructed by using a local signal block to replace a large-scale structured matrix, so that the reconstruction calculation speed is accelerated, and the required internal memory for reconstruction is reduced.

The embodiment of the invention provides a virtual machine control method and device, electronic equipment and a storage medium, relates to the technical field of computers, and realizes quick start of a virtual machine and improves user experience by exchanging process data corresponding to a pulled-up virtual machine process in an internal memory and an external memory. The virtual machine control method comprises the steps that in response to starting of a virtual machine, a virtual machine process in a frozen state is adjusted to be in a runnable state; determining process data associated with the virtual machine process in the external memory; and loading the process data in the memory, so that the virtual machine process calls the process data in the memory to realize the virtual machine service.

The invention relates to a method for realizing a full adder based on Flash, and belongs to the technical field of Flash storage and calculation fusion. The invention designs a full adder implementation method based on the association of inherent characteristics (multi-word line sensing (MWS), RowCopy operation and NOT logic) of Flash and multi-input majority voting (MAJ3 / MAJ5) operation, is suitable for machine learning multiply-accumulate (MAC), edge AI reasoning and other data intensive internal memory calculation scenes, and does not need to perform structural modification on Flash hardware.

A neural processing unit includes an internal memory including a plurality of memory units; a controller configured to control read and write operations of data in at least one of an input feature map domain, a weight domain, and an output feature map domain with respect to each of the plurality of memory units based on an operation schedule in a machine code in which a plurality of operation steps of an artificial neural network model are set.

The present invention provides a NAND flash memory remapping device and a NAND flash memory remapping method that maximize the utilization of internal memory bandwidth, reduce power consumption, and shorten processing delay time. [Solution] An access frequency-based NAND flash memory remapping device 100 according to one embodiment of the present invention includes: a data access frequency analysis unit that analyzes the access frequency to a memory area in which at least one target piece of information is stored; a data remapping unit that constructs a page containing the target information based on the analyzed access frequency; and a page buffer that stores the constructed page and loads it when an access request is made.

The invention provides an automatic generation method and device for a coal mine geologic body, relates to the technical field of computers, and aims to solve the technical problems that in the prior art, a complex geologic structure is inaccurately depicted, and model updating lags behind. Unifying the data format and the space coordinate system of the geological exploration data; the standardized geological data are input into a preset geological body construction model, a three-dimensional geological body model composed of a plurality of triangular prism voxels is generated, and a data structure of the three-dimensional geological body model comprises a memory structure used for storing geometric and attribute data and a rendering structure used for three-dimensional visualization rendering. The memory structure is separated from the rendering structure; and in response to the received updated geological exploration data, dynamically updating the three-dimensional geological body model, and carrying out geological stress analysis based on the updated three-dimensional geological body model to generate stress distribution visual data.

The invention relates to the technical field of distributed streaming data processing and cross-domain processing logic dynamic reconstruction, in particular to a real-time data stream analysis method and system oriented to an automobile internationalization market, and the method comprises the steps: obtaining vehicle pure physical kinematics state data and preset system authorization original environment data; calculating and generating a transient symmetric key, encrypting original environment data into ciphertext data, and writing the ciphertext data into a memory buffer space; inputting kinematics data into a gradient descent optimization model, finely adjusting a feature conversion calculation graph weight matrix and an offset item, and outputting a new rule field matching operator path; reading a hardware clock period numerical value, injecting a ciphertext data tensor head to generate a routing mark, and guiding data to flow to a new operator path; and after path switching is confirmed, an overwriting instruction is sent to replace the transient symmetric key to be in an all-zero physical state, and a decryption restoration path of the residual ciphertext data is blocked. According to the method, the problem of feature data leakage or calculation interruption caused by feature conversion standard difference in cross-regional driving is solved.

The present invention relates to a method and control arrangement for updating a vehicle component of a vehicle, the vehicle comprising: a vehicle component comprising an internal storage for storing a software component for operating the vehicle component; a control arrangement comprising an internal storage for storing a control software controlling operation of the control arrangement, the control arrangement being configured to control operation of the vehicle component; wherein: the control software of the control arrangement is replaced with an update software, the update software being configured to update the software component of the vehicle component; the software component of the vehicle component is updated utilizing the update software; and, following the updating, the software of the control arrangement is restored to control software for controlling operation of the control arrangement.

The invention relates to the technical field of laser synthesis, and discloses a cross-environment self-adaptive laser coherent synthesis method, equipment and a medium. The method comprises the following steps: constructing environment distribution containing various parameter combinations, and randomly sampling an environment from the environment distribution at the beginning of each training period; training an adaptive strategy network based on a sampled environment; deploying the trained adaptive strategy network to a laser coherent combination system, and fixing network parameters of the adaptive strategy network; and updating the internal memory state through initial interaction between the self-adaptive strategy network and the current environment, and outputting a phase correction instruction to perform phase control of laser synthesis. According to the method, the environment overfitting problem existing in laser coherent synthesis in traditional reinforcement learning is solved, rapid self-adaption can be achieved only through a small amount of initial interaction, the debugging cost of system deployment and scene switching is greatly reduced, different noise, turbulence intensity and laser array scales can be adapted, and the stable and efficient phase locking control effect is always kept.

The present invention relates to a method for generating coding tables for sensor signals of a vehicle, comprising: detecting the occurrence frequencies of the sensor signals; dividing the sensor signals into different levels according to the occurrence frequencies, wherein the numbers of the levels correlate with the number of coding bits, whereby with increasing occurrence frequency the numbers of the levels become smaller and the corresponding number of coding bits decreases;Assigning binary codes to the sensor signals, wherein the binary codes have a single middle bit position, as well as front bit positions and back bit positions, wherein a first bit value is written into the middle bit position, the number of front bit positions representing the level, and a second bit value is written, wherein the number of back bit positions depends on the number of front bit positions, and the value of the sensor signal is represented by means of the bit value of the back bit positions; generating a coding table to establish a correspondence between the sensor signals and the binary codes. The present invention further relates to a corresponding coding method, a corresponding decoding method, a corresponding computer program product, and a corresponding processing device. This makes it possible to reduce the internal memory required for recording the sensor signals.

System, comprehensive: an embedded modem with an internal memory whose size is too small to store the received data, which communicates with controllers via a vehicle bus, each controller including a working memory and an auxiliary memory, wherein the modem is programmed to to query the controllers via the bus in order to identify controllers that have available memory in the auxiliary memory, If the available memory is located in the auxiliary memory of a priority controller, the received data is sent to the priority controller via the bus, and Otherwise, if the available memory in the auxiliary memory of a subordinate controller is available, the received data should be sent to the subordinate controller via the bus. to query the controllers via the bus to confirm that the controller storing the received data is available for data storage, and to confirm that the controllers are not operating in a driving mode, and in response to the confirmation, to request the stored data via the bus and to transmit the stored data to a telematics server via a wide area network; the embedded modem is further programmed, if no available memory is found, to reduce the data to a size corresponding to the internal memory of the embedded modem.