556 results about "Internal memory" patented technology

A method and system of the device may include obtaining hardware constraints of an FHE accelerator configured to execute the FHE program. In addition, the device may include selecting an optimal bootstrapping configuration that corresponds to the hardware constraints. The device may include identifying repetitive data patterns in the auxiliary data to be used in the bootstrapping process. Moreover, the device may include reducing the auxiliary data by applying at least one auxiliary data optimization technique based on the repetitive data patterns. Also, the device may include modifying the FHE program to include an instruction to load at least a portion of the reduced auxiliary data into an internal memory of the FHE accelerator, where the at least a portion of the reduced auxiliary data is loaded to the internal memory once prior to the execution of the plurality of bootstrapping processes.

A method and system for optimizing compute runtime and memory footprint of a linear transformation process are provided. The method includes determining a set of optimal rotation parameters, wherein the optimal rotation parameters provide an optimal tradeoff between runtime compute resources and a memory footprint for a runtime execution of the linear transformation process; initializing the linear transformation process to run a boosting technique with the determined set of optimal rotation parameters, wherein the boosting technique, when executed at runtime as part of the linear transformation process, performs at least one iteration that yields rotated ciphertexts, and wherein the at least one iteration is based on the determined set optimal rotation parameters and at least one key switching key (KSK); and loading the initialized linear transformation process to an internal memory of a hardware accelerator.

The invention discloses a few-sample visual defect detection method based on approximate proximity search, and belongs to the technical field of industrial intellectualization. The system mainly comprises an image acquisition module, a feature extraction module, a memory bank construction module, a feature compression module, an approximate nearest neighbor search module and an anomaly detection and result output module. The feature extraction module is used for performing feature extraction on the collected image; the feature compression module is used for reducing the feature data volume and reducing the internal memory and calculation burden; the memory bank construction module is mainly operated during system initialization or model training and is used for constructing a feature memory bank of normal samples; the approximate nearest neighbor search module is responsible for quickly finding normal sample features closest to the input features in the memory bank; and the anomaly detection and result output module is used for converting distance information obtained by neighbor search into anomaly. According to the few-sample visual defect detection method based on the approximate proximity search, the effect of few-sample anomaly detection is achieved.

The invention provides a distributed recommendation method and system based on near data processing, the recommendation system proposes a near memory processing (NMP) architecture by utilizing a memory decoupling technology and a memory expansion capability of Compute Express Link (CXL) so as to realize extensible and efficient recommendation model training; the design of the ReCXL comprises a uniform and hardware-efficient NMP framework, the training of the whole embedded layer can be executed in a CXL memory, the forward propagation and reverse propagation processes are completed, the data volume transmitted through the bandwidth-limited CXL is minimized, and the utilization of the bandwidth of the internal memory is improved. In addition, the design of the ReCXL utilizes flexible management of memory resources and optimization of bandwidth bottleneck in the training process of a recommendation system (DLRM). By implementing near-memory processing in the CXL memory pool, the ReCXL improves the training efficiency. The ReCXL also integrates software and hardware co-optimization techniques, including independent prefetching and fine-grained update scheduling, to maximize the utilization rate of hardware and further improve performance.

The embodiment of the invention discloses a control method, an internal memory and a related chip system, the control method is applied to the internal memory, the internal memory is coupled with a processor, the internal memory comprises a plurality of storage areas Bank, each Bank comprises M rows * N columns of storage units, and M and N are integers greater than 0; the method comprises the following steps: receiving a first instruction sent by a processor, wherein the first instruction is used for indicating an initial column address j and a column number k; k is an integer greater than 1 and less than or equal to N; determining a target Bank and a target row according to the first instruction; in response to the first instruction, target data is read, and the target data is data stored from the jth column to the (j + k-1) th column of the target row in the target Bank. By implementing the embodiment of the invention, the data reading efficiency can be improved, the calculation performance is improved, and the user experience is further improved.

The invention discloses a data transmission method and computer equipment, and relates to the technical field of data transmission. The method comprises the following steps: acquiring a sending work request containing a local sending queue pair number and a work queue element; querying target sending information by taking a local sending queue number as an index; storing the working queue elements and the target sending information as operation contexts into an internal memory of a network card of a request end, and recording corresponding indexes; assembling a target data packet based on the target sending information and the memory index; receiving a feedback data packet of the target data packet and extracting a memory index and a serial number carried by the feedback data packet; if the feedback data packet is a correct confirmation data packet, judging that the sending of the work request is completed and releasing the context; and if the feedback data packet is a confirmation failure data packet, calculating a retransmission data initial address and organizing retransmission. The technical problem that the effective connection number of network cards is limited by hardware resources in the prior art is solved, and the technical effect of supporting large-scale network parallel communication is achieved.

The invention is suitable for the technical field of memory resource calling, and provides a memory resource calling optimization method and system. The method comprises the following steps: comprehensively monitoring memory resources to obtain memory monitoring data, scheduling and analyzing the memory monitoring data, and generating a distribution call notification or a recovery call notification; obtaining program request information and memory state information according to the allocation call notification, and allocating the target memory block to perform memory resource configuration; determining a plurality of adjacent idle memories according to the recovery calling notification, and compressing and recovering the plurality of adjacent idle memories; and when a preset fragment arrangement condition is met, identifying a plurality of dispersed memory fragments, and integrating the plurality of memory fragments into an available memory block. According to the method, the problems of more memory fragments, low utilization rate and poor flexibility in the prior art can be solved, more efficient memory allocation and recovery can be realized, the memory fragments are reduced, the utilization rate of the memory is improved, and meanwhile, the adaptability of a system to different memory requirements is enhanced.

A device for processing a medium includes: a conveyor for conveying the medium; an internal storage for storing the medium, the internal storage being disposed inside a body of the device and connected to the conveyor; an external storage for storing the medium, the external storage being disposed outside the body and connected to the conveyor; a temporary storage for storing the medium temporarily, the temporary storage being connected to the conveyor; and a controller for controlling the conveyer to perform at least one of collection processing and replenishment processing, the collection processing being processing of conveying the medium from the internal storage to the external storage via the temporary storage, the replenishment processing being processing of conveying the medium from the external storage to the internal storage via the temporary storage.

An internal memory reclaiming method, performed by a computer device that comprises at least two groups of SWAP devices, comprising: determining page access frequency information of an internal memory page to be reclaimed based on receiving an internal memory reclaiming instruction; determining a target SWAP device from the at least two groups of SWAP devices based on the page access frequency information; and transferring content data stored in the internal memory page to the target SWAP device.

The embodiment of the invention discloses an internal memory, a chip and related electronic equipment. A target computing unit of the internal memory comprises a plurality of groups of primary multipliers, a plurality of adder trees and a plurality of secondary multipliers, one group of first-level multipliers is connected with one second-level multiplier through one adder tree; the group of first-level multipliers comprises a plurality of pairs of first multipliers, and each adder tree comprises a first adder, a second adder and a third adder; each pair of first multipliers respectively receive data to perform multiplication operation, and respectively input output results into the first adder to perform addition operation; each second adder receives the output results of the plurality of first adders or the second adder at the upper level to carry out addition operation, and respectively inputs the output results to the second adder at the lower level or the third adder; and each third adder receives the output results of the plurality of second adders to carry out addition operation, and inputs the output results to the secondary multiplier to carry out multiplication operation. By implementing the embodiment of the invention, the memory computing capability can be improved.

A system and method for generating training data for fine-tuning an Object Detector (OD) are provided. The method comprises: receiving a given sequence of labelled 3D point clouds of the source domain; selecting, in the sequence bounding boxes, a quasi-stationary bounding box that is a most overlapped bounding box by other bounding boxes from the sequence of bounding boxes; generating a re-labelled 3D point cloud of the source domain by relocating, in the given labelled 3D point cloud, the respective bounding box of the training object to a location thereof corresponding to a location of the quasi-stationary bounding box in an other labelled 3D point cloud; and storing the re-labelled 3D point cloud of the source domain in an internal memory of the server.

The present invention provides a system for measuring real-time meteorological and oceanographic data using a buoyage network for smart ports and harbours. It consists of a moored floating station or moored buoy, or network of buoy-based measurement stations (A) moored at the port or harbour waters with the marine navigation and land-based measuring station (B) mounted at jetty or wharf or quay wall of port and harbours. The buoy-based system (A) is equipped with a cylindrical steel buoy structure featuring a mast (7) and is secured using a two-point mooring system. The present system comprises of an integrated monitoring and data transmission system that collects the real-time meteorological and oceanographic data from the sensors and processes the acquired data based on calibration, enabling accurate and reliable measurements. The processed data is then stored in the system's internal memory for analysis and transmitted to a remote-control station.

The invention discloses a substitute address verification method and system based on a dynamic page table. The method comprises the steps of determining a target constraint condition of a basic variable in a current instance based on a preset configuration specification through a page table generation component, and randomizing the basic variable based on the target constraint condition to generate a target page table and a target storage address corresponding to a target virtual address; storing the target page table to a target storage address of an internal memory based on a preset storage rule, and determining an expected physical address corresponding to the target virtual address based on the target page table; determining a target page table in an internal memory based on the target virtual address through an address management module, and determining a basic physical address corresponding to the target virtual address based on a preset reduced instruction set substitution rule and the target page table; and comparing and processing the expected physical address and the basic physical address through a verification module to generate a verification result. Through the technical scheme of the invention, the substitution address can be verified, and the verification efficiency and accuracy of the substitution address are improved.

A data processing method is applied to the field of artificial intelligence and comprises the steps of generating second data through a first network according to first data; generating third data through a second network according to the first data; wherein the first network comprises a first network layer, the second network comprises a second network layer, and the first network layer is a partial network of the second network layer; and verifying the second data according to the third data. According to the method and the device, the network (the second network) for performing the data verification process is multiplexed for generating the data network (a part of the first network), so that the additional reasoning deployment overhead can be reduced, the internal memory of the second network can reuse the reasoning result of the first network when the second network is verified, additional time delay is not needed, and the calculation overhead is reduced.

The invention relates to a satellite navigation baseband processing device optimized by a coprocessor. A core processing part of the device adopts a realization framework of a main processor and a coprocessor; the coprocessor is used for scheduling hardware acceleration computing resources in real time under exchange control of the main processor, and completing high-real-time processing tasks such as signal capture and tracking loop processing of satellite navigation; an instruction set and an external interface of the coprocessor are subjected to targeted optimization, the bus bit width and the internal storage width of the coprocessor are expanded, and the in-situ width of an ALU and a register of the coprocessor is reserved; performing bus data access and storage by adopting an external port access instruction and an internal memory access instruction which are matched with the expanded bus according to the expansion state; and performing access and storage of single register data by adopting a bus write enable, an access instruction and a storage instruction which are matched with the expanded internal storage width. According to the invention, the function load of the main processor is effectively reduced, and the implementation cost of the baseband processing device is reduced.

The invention provides a mode switching method and electronic equipment, the mode switching method is applied to the electronic equipment, the electronic equipment comprises a main processor, a coprocessor and an internal memory, operation modes of the electronic equipment comprise a power-saving mode and a working mode, the coprocessor works in the power-saving mode, the main processor does not work, and the internal memory does not work in the working mode. In the working mode, the main processor and the coprocessor work, and the method comprises the steps that first operation is received, and the first operation is used for switching the operation mode of the electronic equipment from the power-saving mode to the working mode; controlling the main processor to be powered on; and obtaining first data from the internal memory, wherein the first data is business data of the main processor stored when the operation mode of the electronic equipment is switched from the working mode to the power saving mode. By adopting the method and the device, the running mode of the electronic equipment can provide due function effects, and the function availability is improved, so that the user experience is improved.

The invention relates to the technical field of terminals, in particular to a control method, a related device and a readable storage medium, and the method can comprise the following steps: obtaining to-be-processed data; when the quantization precision of the to-be-processed data is greater than the calculation precision of the calculation unit, performing data splitting on the to-be-processed data to obtain a plurality of sub-data; the quantization precision of each piece of sub-data in the multiple pieces of sub-data is smaller than or equal to the calculation precision of the calculation unit; respectively sending a first memory access instruction for the plurality of sub-data according to a storage rule; the first memory access instruction is used for indicating the internal memory to write the sub-data into a specified row or column. The embodiment of the invention can be compatible with mixed quantization precision calculation, and meanwhile, the circuit area overhead is saved.

Provided is a secure execution of a first instruction by processing means of an electronic system, comprising fetching (S1) said first instruction in an execution pipeline of the processing means, determining (S2) that said first instruction to be executed is an instruction sensitive to a determined attack, selecting (S3), based on said determined attack, from an internal memory of said processing means, at least one second instruction, which, when executed by the processing means, causes the processing means to perform a combination of said first function and a dedicated security countermeasure against said determined attack, and executing (S4) said selected second instructions instead of said first instruction.

Methods and system are provided for virtualizing root of trust (ROT) to serve devices that do not have built-in ROT functionality. A component of a computer system may provide root of trust functionality for the computer system generally. That component may also provide virtualized ROT functionality for a non-ROT component by generating a symmetric encryption key and an asymmetric encryption key pair using a unique identifier of the non-ROT component. The virtual ROT functionality may handle storage of the encryption keys as well as an ID certificate for the non-ROT component. Furthermore, the virtual ROT functionality may be configured to write encrypted data to an internal memory of the non-ROT component, read and decrypt that data, and write back further encrypted data.

The present application belongs to the technical field of cloud computing and provides a computing system, a multi-round session inference method, an apparatus and a computing device cluster. In the system, an external storage device stores a historical key value cache of a completed session. As the capacity of the external storage device is far greater than the capacity of an HBM in an accelerator, the hit rate of the historical key value cache can be increased, thereby avoiding recomputing the key value cache. In addition, when the accelerator processes a session, a host can preload a historical key value cache of a session to be processed in a task queue from the external storage device to an internal memory of the host; when performing i-th layer computing on the session, the accelerator can preload from the internal memory of the host the historical key value cache required for the (i+1)-th layer computing. As the computing process and the data loading process are synchronously performed, the computing process does not need to wait for the completion of data loading, such that the time overheads of the accelerator accessing the external storage device can be hidden, improving the efficiency of multi-round session inference.

An information processing apparatus includes: an internal storage configured to store one or more programs; a controller configured to execute the one or more programs; and an interface configured to receive information from an external storage containing a whitelist. The whitelist includes determination information indicating whether to allow the controller to execute each of the one or more programs. The controller is configured to acquire the whitelist from the external storage through the interface, verify an integrity of the acquired whitelist, and in response to a determination that the acquired whitelist is complete, store the acquired whitelist in the internal storage as an active whitelist to be used for determining whether to allow the controller to execute each of the one or more programs stored in the internal storage.

The invention provides a heterogeneous computing method, a heterogeneous computing device, heterogeneous computing equipment and a computer readable storage medium, and is applied to the technical field of data processing. The method comprises the following steps: when a heterogeneous computing power card accesses data, a central processing unit firstly determines whether a target object accessed this time exists in a video memory or not; and under the condition that the target object does not exist in the video memory, the central processing unit reads the target object from the memory and stores the target object in the video memory. Further, the central processing unit can provide the target object loaded into the video memory for the heterogeneous computing power card. In the scheme provided by the embodiment of the invention, the heterogeneous computing data meeting the preset condition is transferred from the video memory to the memory, and the data written into the memory is subjected to a realistic copying strategy, so that the storage space of the heterogeneous computing data can be expanded, and the utilization rate of the video memory space can be improved, thereby realizing video memory oversell, and improving the user experience. And thus, high-performance calculation of the heterogeneous computing power card can be guaranteed.

A request to provide an application with direct memory access to data stored at an external memory address of an external memory is received. Responsive to determining that the external memory address is not registered in a cache, the data is copied from the external memory address to a first internal memory address within the internal memory. A first cache line, within the cache, associated with the external memory address is updated to include a reference to the first internal memory address. The data is provided from the internal memory to the application.

The invention belongs to the technical field of data acquisition, and particularly relates to a device for acquiring microwave equipment data, which comprises a data acquisition box and a central processor, the central processor is arranged in front of the left side in the data acquisition box, a memory is arranged in front of the central processor, and a power supply is arranged in front of the memory. A hard disk is arranged on the right side in the data acquisition box, a power jack is formed in the left side of the rear portion of the data acquisition box, a power switch is arranged on the right side of the power jack, a network interface is formed in the left side of the front portion of the data acquisition box, and a USB interface is formed in the right side of the network interface. The invention provides a device for acquiring data of microwave equipment, and the device completes the acquisition of the data of the microwave equipment by inserting a power line into a power jack, turning on a power switch, observing a power indicator light, connecting with the broadcast and television microwave equipment through a network cable, and through the mutual cooperation of an internal central processing unit, an internal memory and a hard disk.

Virtual memory pooling, including identifying GPUs of respective IHSs, wherein each of the GPUs is associated with a respective internal memory allocation; partitioning, for each GPU, the internal memory allocation associated with the GPU into a first memory allocation and a second memory allocation; allocating, for each GPU, the first memory allocation of the internal memory allocation associated with the GPU as accessible only by the associated GPU; pooling, for each GPU, the second memory allocation of the internal memory allocation associated with the GPU to define a virtual memory pool, the virtual memory pool accessible by each GPU; processing, at a first GPU, a computational task, including: accessing the first memory allocation associated with the first GPU; determining that processing of the computational task exceeds a capacity of the first memory allocation of the first GPU and in response, requesting access to the virtual memory pool.

An outdoor lighting and projection system that includes a light fixture device and a projector device is disclosed. The light fixture device comprises a display device integrated with a yard stake and a solar panel for absorbing solar power (i.e., solar energy) to illuminate the display. The projector device features a projector system pivotally coupled to a first arm and a second arm via hinge (i.e., pivotal) brackets, enabling for tilting, panning, and ground installation. An internal memory includes premade slides and messages for display by the display device and projection by the projector system. The system includes a wireless module for remote control via a mobile application and an AC to DC adaptor for external power supply. The system is configured for remote operation and provides different projection and illumination.

The invention discloses a portable intelligent signal processing system suitable for rapid detection and identification of communication signals. The portable intelligent signal processing system comprises a portable computer hardware device and an upper computer software system. Hardware equipment of the portable computer adopts a CPU + NPU computing architecture; the portable computer hardware device further comprises an internal memory, an SSD hard disk, a battery, an LED displayer and an IO interface. The upper computer software system comprises a data import and export module, a preprocessing module, a neural network deployment module, an intelligent reasoning module, a storage and data management module and a man-machine interaction module. According to the method, an intelligent signal processing technology is introduced, and a data set is constructed through fine signal analysis, identification and labeling of offline signals; a deep network is trained on the basis, and the ability of an existing analyst is transferred to a deep neural network; rapid analysis and identification of communication reconnaissance signals can be completed, knowledge transfer iteration improvement of manual offline analysis is realized, and intelligence generation efficiency is effectively improved.

The invention provides a data processing method and device of a processor, equipment, a medium and a program product. The method comprises the steps of loading an mth data block in a first matrix to a first cache position of an internal memory through a first thread in a thread group of a processor, and loading an nth data block in a second matrix to a second cache position of the internal memory; loading the (n + 1) th data block in the second matrix from the external memory to a third cache position of the internal memory through the first thread, and performing multiplication operation on the data blocks in the first cache position and the data blocks in the second cache position through the second thread; and loading the (n + 1) th data block in the second matrix from the internal memory to a second cache position of the internal memory through the first thread, and performing multiplication operation on the data block in the first cache position and the data block in the third cache position through the second thread. According to the invention, the calculation speed of multiplication in the processor can be improved.

A method performs a plurality of operations on an artificial neural network (ANN). The plurality of operations includes storing in at least one memory a set of weights, at least a portion of a first batch channel of a plurality of batch channels, and at least a portion of a second batch channel of the plurality of batch channels; and calculating the at least a portion of the first batch channel and the at least a portion of the second batch channel by the set of weights. A batch mode, configured to process a plurality of input channels, can determine the operation sequence in which the on-chip memory and / or internal memory stores and computes the parameters of the ANN. Even if the number of input channels increases, processing may be performed with one neural processing unit including a memory configured in consideration of a plurality of input channels.