317 results about "Internal memory" patented technology

A method and system of the device may include obtaining hardware constraints of an FHE accelerator configured to execute the FHE program. In addition, the device may include selecting an optimal bootstrapping configuration that corresponds to the hardware constraints. The device may include identifying repetitive data patterns in the auxiliary data to be used in the bootstrapping process. Moreover, the device may include reducing the auxiliary data by applying at least one auxiliary data optimization technique based on the repetitive data patterns. Also, the device may include modifying the FHE program to include an instruction to load at least a portion of the reduced auxiliary data into an internal memory of the FHE accelerator, where the at least a portion of the reduced auxiliary data is loaded to the internal memory once prior to the execution of the plurality of bootstrapping processes.

A method and system for optimizing compute runtime and memory footprint of a linear transformation process are provided. The method includes determining a set of optimal rotation parameters, wherein the optimal rotation parameters provide an optimal tradeoff between runtime compute resources and a memory footprint for a runtime execution of the linear transformation process; initializing the linear transformation process to run a boosting technique with the determined set of optimal rotation parameters, wherein the boosting technique, when executed at runtime as part of the linear transformation process, performs at least one iteration that yields rotated ciphertexts, and wherein the at least one iteration is based on the determined set optimal rotation parameters and at least one key switching key (KSK); and loading the initialized linear transformation process to an internal memory of a hardware accelerator.

The invention discloses a few-sample visual defect detection method based on approximate proximity search, and belongs to the technical field of industrial intellectualization. The system mainly comprises an image acquisition module, a feature extraction module, a memory bank construction module, a feature compression module, an approximate nearest neighbor search module and an anomaly detection and result output module. The feature extraction module is used for performing feature extraction on the collected image; the feature compression module is used for reducing the feature data volume and reducing the internal memory and calculation burden; the memory bank construction module is mainly operated during system initialization or model training and is used for constructing a feature memory bank of normal samples; the approximate nearest neighbor search module is responsible for quickly finding normal sample features closest to the input features in the memory bank; and the anomaly detection and result output module is used for converting distance information obtained by neighbor search into anomaly. According to the few-sample visual defect detection method based on the approximate proximity search, the effect of few-sample anomaly detection is achieved.

The invention discloses a data transmission method and computer equipment, and relates to the technical field of data transmission. The method comprises the following steps: acquiring a sending work request containing a local sending queue pair number and a work queue element; querying target sending information by taking a local sending queue number as an index; storing the working queue elements and the target sending information as operation contexts into an internal memory of a network card of a request end, and recording corresponding indexes; assembling a target data packet based on the target sending information and the memory index; receiving a feedback data packet of the target data packet and extracting a memory index and a serial number carried by the feedback data packet; if the feedback data packet is a correct confirmation data packet, judging that the sending of the work request is completed and releasing the context; and if the feedback data packet is a confirmation failure data packet, calculating a retransmission data initial address and organizing retransmission. The technical problem that the effective connection number of network cards is limited by hardware resources in the prior art is solved, and the technical effect of supporting large-scale network parallel communication is achieved.

The embodiment of the invention discloses an internal memory, a chip and related electronic equipment. A target computing unit of the internal memory comprises a plurality of groups of primary multipliers, a plurality of adder trees and a plurality of secondary multipliers, one group of first-level multipliers is connected with one second-level multiplier through one adder tree; the group of first-level multipliers comprises a plurality of pairs of first multipliers, and each adder tree comprises a first adder, a second adder and a third adder; each pair of first multipliers respectively receive data to perform multiplication operation, and respectively input output results into the first adder to perform addition operation; each second adder receives the output results of the plurality of first adders or the second adder at the upper level to carry out addition operation, and respectively inputs the output results to the second adder at the lower level or the third adder; and each third adder receives the output results of the plurality of second adders to carry out addition operation, and inputs the output results to the secondary multiplier to carry out multiplication operation. By implementing the embodiment of the invention, the memory computing capability can be improved.

An information processing apparatus includes: an internal storage configured to store one or more programs; a controller configured to execute the one or more programs; and an interface configured to receive information from an external storage containing a whitelist. The whitelist includes determination information indicating whether to allow the controller to execute each of the one or more programs. The controller is configured to acquire the whitelist from the external storage through the interface, verify an integrity of the acquired whitelist, and in response to a determination that the acquired whitelist is complete, store the acquired whitelist in the internal storage as an active whitelist to be used for determining whether to allow the controller to execute each of the one or more programs stored in the internal storage.

The invention provides a heterogeneous computing method, a heterogeneous computing device, heterogeneous computing equipment and a computer readable storage medium, and is applied to the technical field of data processing. The method comprises the following steps: when a heterogeneous computing power card accesses data, a central processing unit firstly determines whether a target object accessed this time exists in a video memory or not; and under the condition that the target object does not exist in the video memory, the central processing unit reads the target object from the memory and stores the target object in the video memory. Further, the central processing unit can provide the target object loaded into the video memory for the heterogeneous computing power card. In the scheme provided by the embodiment of the invention, the heterogeneous computing data meeting the preset condition is transferred from the video memory to the memory, and the data written into the memory is subjected to a realistic copying strategy, so that the storage space of the heterogeneous computing data can be expanded, and the utilization rate of the video memory space can be improved, thereby realizing video memory oversell, and improving the user experience. And thus, high-performance calculation of the heterogeneous computing power card can be guaranteed.

An outdoor lighting and projection system that includes a light fixture device and a projector device is disclosed. The light fixture device comprises a display device integrated with a yard stake and a solar panel for absorbing solar power (i.e., solar energy) to illuminate the display. The projector device features a projector system pivotally coupled to a first arm and a second arm via hinge (i.e., pivotal) brackets, enabling for tilting, panning, and ground installation. An internal memory includes premade slides and messages for display by the display device and projection by the projector system. The system includes a wireless module for remote control via a mobile application and an AC to DC adaptor for external power supply. The system is configured for remote operation and provides different projection and illumination.

The invention provides a data processing method and device of a processor, equipment, a medium and a program product. The method comprises the steps of loading an mth data block in a first matrix to a first cache position of an internal memory through a first thread in a thread group of a processor, and loading an nth data block in a second matrix to a second cache position of the internal memory; loading the (n + 1) th data block in the second matrix from the external memory to a third cache position of the internal memory through the first thread, and performing multiplication operation on the data blocks in the first cache position and the data blocks in the second cache position through the second thread; and loading the (n + 1) th data block in the second matrix from the internal memory to a second cache position of the internal memory through the first thread, and performing multiplication operation on the data block in the first cache position and the data block in the third cache position through the second thread. According to the invention, the calculation speed of multiplication in the processor can be improved.

Methods for producing and validating RFID transponders (e.g., ISO 11784 / 11785 compliant transponders) with identification number authentication capabilities. A signature indicator and a partial-signature trailer are introduced to the ISO telegram. An encrypted signature or partial signature is introduced to the internal memory of ISO compliant transponders. The encrypted signature can prevent fraudulent duplications of ISO 11784 / 11785 transponders by allowing users to securely validate the transponders' authenticity.

The invention discloses a diagnostic reasoning RAG system for resisting retrieval noise based on a self-generated knowledge base, and the system comprises a knowledge retrieval module which carries out the retrieval from an external knowledge base according to a user question to obtain a plurality of target text blocks; the evaluation generation module is used for independently evaluating each target text block through an evaluation model so as to identify retrieval noise, generating a correlation judgment result and a noise degree judgment result of each target text block, and generating internal memory information as a self-generated knowledge base based on a user question; and the diagnosis reasoning module is used for integrating the user question, each target text block, the corresponding correlation judgment result, the noise degree judgment result and the internal memory information into enhanced prompt information and inputting the enhanced prompt information into a large language model to generate a diagnosis reasoning answer. According to the method, retrieval noise interference can be effectively resisted, model knowledge support is strengthened by means of the self-generated knowledge base, the precision and timeliness of medical diagnosis reasoning are improved, and the requirements of the medical field for high-precision and strong-timeliness clinical decision making are met.

A data storage device and method for delaying execution of a host write command to perform an internal memory operation. In one embodiment, a data storage device is provided comprising a memory with single-level cell (SLC) blocks and multi-level cell (MLC) blocks, as well as a controller. The controller is configured to store, in a queue, a plurality of write commands received from a host, wherein each write command is associated with a timeout window; determine how long each of the plurality of write commands has been pending in the queue; and for each write command, delay execution of the write command within the write command's timeout window until the write command has been pending in the queue for a specified amount of time, wherein delaying execution of each write command provides the controller with time to perform a memory operation to increase an amount of available SLC blocks in the memory. Other embodiments are provided.

A microcontroller includes: a processor, a communication interface configured to enable communication between the processor and an external memory, and an internal memory. The internal memory stores: at least one driver for controlling the communication interface when it the driver is executed by the processor, and a management software module for controlling the external memory by using the at least one driver and at least one communication parameter associated with the external memory when the driver is executed by the processor.

A self-coiling light structure is designed to expand and retract in a controlled manner to prevent tangling and facilitate compact storage. The structure comprises a flexible coil made of wire, rope, plastic, or a combination thereof, incorporating a power-conducting element and LED lights positioned at intervals. The coil is configured to retain a predetermined shape through an internal memory material, allowing it to automatically retract into a compact form when not in use. The structure further includes securement features such as loops or clips for attachment to external structures, as well as male and female power connectors for interconnection with additional sections. Various embodiments provide for different configurations of the coil in excited and unexcited states, ensuring ease of deployment and retraction.

A modem chip receives a codeword including a transport block composed of a plurality of code blocks, and includes a hybrid automatic repeat request (HARQ) processing circuit configured to perform a HARQ-based processing operation with respect to the codeword, and an internal memory configured to store data generated by the HARQ processing circuit. The HARQ processing circuit includes a code block processing circuit configured to decode the plurality of code blocks in units of code blocks and perform a first cyclic redundancy check on each of the decoded plurality of code blocks, and a codeword processing circuit configured to perform a second cyclic redundancy check on a decoded transport block.

A compute tile includes a WCB that receives a workload of writing an output tensor of a convolution into a local memory of the compute tile. The local memory may be a SRAM. The WCB receives write transactions. A write transaction includes a data block, which is a part of the output tensor, and metadata describing one or more attributes of the data block. The WCB may store write transactions in its internal buffers. The WCB may determine whether to combine two write transactions, e.g., based on an operation mode or metadata in the write transactions. In embodiments where the WCB determines to combine the two write transactions, the WCB may combine the two write transactions into a new write transaction and write the new write transaction into the local memory or an internal memory of the WCB. The total number of write transactions for the workload can be reduced.

Disclosed in the embodiments of the present application are an internal memory, a chip and a related electronic device. A target processing unit (202) of an internal memory (102) comprises a plurality of groups of primary multipliers, a plurality of adder trees and a plurality of secondary multipliers, wherein one group of primary multipliers is connected to one secondary multiplier by means of one adder tree; one group of primary multipliers comprises a plurality of pairs of first multipliers; each adder tree comprises a first adder, a second adder and a third adder; each pair of first multipliers separately receives data to perform multiplication operations, and separately inputs output results into one first adder for addition operations; each second adder receives output results of a plurality of first adders or the upper-level second adder, so as to perform addition operations, and separately inputs the output results into the lower-level second adder or one third adder; and each third adder receives output results of a plurality of second adders to perform addition operations, and inputs the output results into one secondary multiplier for multiplication operations. Implementing the embodiments of the present application can improve the processing capability of the internal memory.

Aspects of the present disclosure include a serializer, a method, and / or a non-transitory computer readable medium for receiving an indication indicating the sensor circuit is connected to a controller circuit, identifying a sensor identifier associated with the sensor circuit from an internal memory of the serializer, transmitting the sensor identifier from the serializer to the controller circuit to a deserializer to identify and load a sensor circuit driver associated with the sensor identifier, transmitting sensor calibration data from the memory circuit on the sensor circuit to the controller circuit, and transmitting sensor data to the deserializer.

The invention discloses a construction method of an equipment temperature custom sorting table under new energy configuration and a related device. The construction method comprises the following steps: editing a configuration file; reading the configuration file, extracting the width, the height and the segmentation number of the table, and storing the mapping relation between the component name and the measuring point into a memory cache; reading the temperature value of each measuring point; the temperature values of all the measuring points are sorted, a sorting table is constructed according to the sorting result, the width and height of the table, segmentation data and the mapping relation between the component names and the measuring points, and the method and the related device can meet the quick response requirement of new energy equipment for temperature anomaly.

The invention relates to a method for exchanging interface information between different communication partners for communication between communication partners (3, 4) by PCI-Express, comprising the following steps: a) ascertaining an interface definition (7), which describes a memory region (8) and a memory internal layout of a first communication partner (4), the second communication partner (3) should access the memory region in order to read and / or write data; b) creating a serialized form of the interface definition (7) ascertained in step a); c) providing the serialized form of the interface definition (7) created in step b) to the second communication partner (3); and d) automatically configuring the second communication partner (3) with the provided interface definition (7) for communication of the communication partners (3, 4). The invention also relates to a system (1) for data processing.

The invention relates to the technical field of heat dissipation, in particular to the technical field of heat dissipation of personal computers, workstations and servers, and particularly relates to an open type air duct memory radiator. The radiator comprises radiating fins, a limiting component and a heat-conducting medium, wherein the radiating fins, the limiting component and the heat-conducting medium surround a memory bank to form an open air duct. The cooling fins are symmetrically arranged on the two sides of the memory bank; the limiting component is arranged between the two cooling fins and abuts against the top of the memory bank. And the heat-conducting medium is arranged on a memory chip of the memory bank and is in contact with the inner surfaces of the adjacent cooling fins. According to the internal memory radiator, internal accumulated heat is reduced through the open air duct, and the air flowing efficiency is improved; and heat generated during operation of the memory bank is directly conducted to the cooling fins through the heat-conducting medium, so that the heat conduction efficiency is improved. The flow guide type design of an open type air channel is combined with the direct heat conduction design, efficient heat dissipation is achieved, and stable operation of the memory bank is guaranteed.

The embodiment of the invention provides a security defense method and device based on Hypervisor, and relates to the technical field of virtualization. The method comprises the steps of determining a memory processing type in response to a preset trigger operation; and calling an hvc command by calling a virtual machine monitor corresponding to the memory processing type so as to indicate a Hypervisor to execute a Hypervisor processing function corresponding to the hvc command. According to the embodiment of the invention, the distribution or release of the internal memory of the process is realized through the Hypervisor with higher authority, even if the kernel of the operating system is broken by a malicious application program, the integrity of a security mechanism of the operating system can still be ensured, and the effective defense of security threats of the operating system is realized.

The present invention provides a real-time internal and external memory replacement mechanism and mapping management method for a limited resource system, comprising the following steps: defining a storage management structure for internal memory space; defining a storage management structure for external memory space; starting a task and performing a storage resource allocation process; and implementing a real-time internal and external memory replacement mechanism during task reading and writing. The real-time internal and external memory replacement mechanism and mapping management method for a limited resource system provided by the present invention have the following advantages: The present invention provides a real-time internal and external memory replacement mechanism and mapping management method for a limited resource system, implementing a data mapping algorithm for computer system function runtime. By defining a mechanism for orderly and accurate mapping of runtime data between internal memory space and external memory space, and real-time replacement on demand, the available memory space for runtime is expanded, effectively meeting the technical requirement of completing a large number of intensive tasks under conditions of limited memory resources.

The invention relates to a method for displaying data, the method being implemented in a display module comprising a screen and a control module adapted to control light elements of the screen as a function of data on a data interface. The display module includes a memory storing at least one image. The method comprises the following steps:-detecting (202; 203) when data onto the data interface is unavailable and a power signal is received through at least one power interface, accessing (204), by the control module, the at least one image in the memory; -controlling (205) the light emitting elements by the control module to display the at least one image.

A processor, method, and non-transitory computer-readable storage medium for processing template data and search data according to a search window applied to the search data. The search window comprising a set of offset positions. The processing is performed by a block matching engine (BME) that produces a tensor with difference values, and a convolutional engine (CE) that performs a convolutional operation on the tensor. The processing is performed in an iterative interleaved fashion, by dividing the set of offset positions into a plurality of subsets of offset positions. In parallel with processing of the first X offset positions by the CE, the BME generates the next X channels of the tensor, and which are subsequently pipelined through to the CE via an internal storage, etc.

A method and apparatus of direct memory access DMA between accelerator cards, an accelerator card, an accelerating platform and a non-volatile readable storage medium. The first accelerator card according to the present application can initiatively perform the initiation of the DMA, and, according to the idle-internal-memory datum of the second accelerator card as the data destination terminal recorded in the first accelerator card itself, write the datum directly into the internal memory of the second accelerator card in the mode of DMA, which does not require inquiring the idle-internal-memory address of the second accelerator card before the DMA, and does not require waiting for the second accelerator card to initiate the DMA. The solution realizes the direct DMA writing operation between different accelerator cards at the hardware level, and solves the problem in DMA operation between accelerator cards.

The present invention concerns a kit (1) comprising a timekeeping device (2) driven by a self-winding mechanical movement and a winder case (3) for said timekeeping device (2). The timekeeping device (2) includes means for displaying the counting of time elapsed since an event and means for activating, stopping and resetting the counting of time elapsed since said event. The winder case includes means configured for memorising the time of activation of the timekeeping device (2), microprocessor means (8) and means for comparing the counting of time indicated by said timekeeping device (2) with the stored data of the activation event. The invention has the particular advantage that, in the event of a discrepancy between the counting of time indicated by the timekeeping device (2) and the stored data, the synchronisation of the counting is carried out automatically inside the winder case (3) by means of counting of time correction. The timekeeping device (2) and the winder case (3) may include proximity communication devices so as to enable wireless communication between the timekeeping device (2) and the microprocessor means (8) in the winder case (3). In particular, at the time of the activation event of the timekeeping device (2), the details of the activation event, contained for example in a digital timestamp, may be recorded in an encrypted internal memory of the winder case (3). Furthermore, the details of the activation event may be sent to a remote server from where they are submitted online via a blockchain protocol.

Methods, systems, and media comprising; a host device configured to execute one or more applications; and a processing-in-memory (PIM) subsystem comprising one or more memory arrays and one or more integrated compute elements, wherein the integrated compute elements comprise internal storage that is accessible during execution of instructions by the PIM subsystem operating on data stored in the one or more memory arrays, wherein the host device is configured to send commands over a command interface to initiate storing data in the one or more memory arrays over a data interface, and wherein the host device is configured to send data for storage in the internal storage of the PIM subsystem over the command interface.

The present disclosure relates to a skew resistance PID device and a processing method, and the device includes: Dual In-line Memory Modules (DIMMs) composed of multiple ranks respectively having multiple banks, and In-DIMM Processors (IDPs) that process internal memory operations; a memory controller; and a host CPU connected to the memory module through the memory controller and configured to enhance parallel processing performance of the IDPs by replicating a join key in units of bank sets and rank sets.

Even when the processing result at a certain layer in a convolutional neural network is input to the next layer and further subsequent layers, the processing can be executed more appropriately. A subnetwork included in a convolutional neural network includes a first layer, a second layer, a third layer, and a fourth layer, the output of the first layer is input to the second layer, the output of the second layer is input to the third layer, and the output of the first layer and the output of the third layer are input to the fourth layer, the acquisition unit divides and acquires the data to be processed so that the total size of the input data to each layer is equal to or less than the storage capacity of the internal memory.