274 results about "Internal memory" patented technology

A method and system of the device may include obtaining hardware constraints of an FHE accelerator configured to execute the FHE program. In addition, the device may include selecting an optimal bootstrapping configuration that corresponds to the hardware constraints. The device may include identifying repetitive data patterns in the auxiliary data to be used in the bootstrapping process. Moreover, the device may include reducing the auxiliary data by applying at least one auxiliary data optimization technique based on the repetitive data patterns. Also, the device may include modifying the FHE program to include an instruction to load at least a portion of the reduced auxiliary data into an internal memory of the FHE accelerator, where the at least a portion of the reduced auxiliary data is loaded to the internal memory once prior to the execution of the plurality of bootstrapping processes.

A method and system for optimizing compute runtime and memory footprint of a linear transformation process are provided. The method includes determining a set of optimal rotation parameters, wherein the optimal rotation parameters provide an optimal tradeoff between runtime compute resources and a memory footprint for a runtime execution of the linear transformation process; initializing the linear transformation process to run a boosting technique with the determined set of optimal rotation parameters, wherein the boosting technique, when executed at runtime as part of the linear transformation process, performs at least one iteration that yields rotated ciphertexts, and wherein the at least one iteration is based on the determined set optimal rotation parameters and at least one key switching key (KSK); and loading the initialized linear transformation process to an internal memory of a hardware accelerator.

The invention discloses a few-sample visual defect detection method based on approximate proximity search, and belongs to the technical field of industrial intellectualization. The system mainly comprises an image acquisition module, a feature extraction module, a memory bank construction module, a feature compression module, an approximate nearest neighbor search module and an anomaly detection and result output module. The feature extraction module is used for performing feature extraction on the collected image; the feature compression module is used for reducing the feature data volume and reducing the internal memory and calculation burden; the memory bank construction module is mainly operated during system initialization or model training and is used for constructing a feature memory bank of normal samples; the approximate nearest neighbor search module is responsible for quickly finding normal sample features closest to the input features in the memory bank; and the anomaly detection and result output module is used for converting distance information obtained by neighbor search into anomaly. According to the few-sample visual defect detection method based on the approximate proximity search, the effect of few-sample anomaly detection is achieved.

The invention discloses a data transmission method and computer equipment, and relates to the technical field of data transmission. The method comprises the following steps: acquiring a sending work request containing a local sending queue pair number and a work queue element; querying target sending information by taking a local sending queue number as an index; storing the working queue elements and the target sending information as operation contexts into an internal memory of a network card of a request end, and recording corresponding indexes; assembling a target data packet based on the target sending information and the memory index; receiving a feedback data packet of the target data packet and extracting a memory index and a serial number carried by the feedback data packet; if the feedback data packet is a correct confirmation data packet, judging that the sending of the work request is completed and releasing the context; and if the feedback data packet is a confirmation failure data packet, calculating a retransmission data initial address and organizing retransmission. The technical problem that the effective connection number of network cards is limited by hardware resources in the prior art is solved, and the technical effect of supporting large-scale network parallel communication is achieved.

The embodiment of the invention discloses an internal memory, a chip and related electronic equipment. A target computing unit of the internal memory comprises a plurality of groups of primary multipliers, a plurality of adder trees and a plurality of secondary multipliers, one group of first-level multipliers is connected with one second-level multiplier through one adder tree; the group of first-level multipliers comprises a plurality of pairs of first multipliers, and each adder tree comprises a first adder, a second adder and a third adder; each pair of first multipliers respectively receive data to perform multiplication operation, and respectively input output results into the first adder to perform addition operation; each second adder receives the output results of the plurality of first adders or the second adder at the upper level to carry out addition operation, and respectively inputs the output results to the second adder at the lower level or the third adder; and each third adder receives the output results of the plurality of second adders to carry out addition operation, and inputs the output results to the secondary multiplier to carry out multiplication operation. By implementing the embodiment of the invention, the memory computing capability can be improved.

An information processing apparatus includes: an internal storage configured to store one or more programs; a controller configured to execute the one or more programs; and an interface configured to receive information from an external storage containing a whitelist. The whitelist includes determination information indicating whether to allow the controller to execute each of the one or more programs. The controller is configured to acquire the whitelist from the external storage through the interface, verify an integrity of the acquired whitelist, and in response to a determination that the acquired whitelist is complete, store the acquired whitelist in the internal storage as an active whitelist to be used for determining whether to allow the controller to execute each of the one or more programs stored in the internal storage.

An outdoor lighting and projection system that includes a light fixture device and a projector device is disclosed. The light fixture device comprises a display device integrated with a yard stake and a solar panel for absorbing solar power (i.e., solar energy) to illuminate the display. The projector device features a projector system pivotally coupled to a first arm and a second arm via hinge (i.e., pivotal) brackets, enabling for tilting, panning, and ground installation. An internal memory includes premade slides and messages for display by the display device and projection by the projector system. The system includes a wireless module for remote control via a mobile application and an AC to DC adaptor for external power supply. The system is configured for remote operation and provides different projection and illumination.

The invention provides a data processing method and device of a processor, equipment, a medium and a program product. The method comprises the steps of loading an mth data block in a first matrix to a first cache position of an internal memory through a first thread in a thread group of a processor, and loading an nth data block in a second matrix to a second cache position of the internal memory; loading the (n + 1) th data block in the second matrix from the external memory to a third cache position of the internal memory through the first thread, and performing multiplication operation on the data blocks in the first cache position and the data blocks in the second cache position through the second thread; and loading the (n + 1) th data block in the second matrix from the internal memory to a second cache position of the internal memory through the first thread, and performing multiplication operation on the data block in the first cache position and the data block in the third cache position through the second thread. According to the invention, the calculation speed of multiplication in the processor can be improved.

Methods for producing and validating RFID transponders (e.g., ISO 11784 / 11785 compliant transponders) with identification number authentication capabilities. A signature indicator and a partial-signature trailer are introduced to the ISO telegram. An encrypted signature or partial signature is introduced to the internal memory of ISO compliant transponders. The encrypted signature can prevent fraudulent duplications of ISO 11784 / 11785 transponders by allowing users to securely validate the transponders' authenticity.

The invention discloses a diagnostic reasoning RAG system for resisting retrieval noise based on a self-generated knowledge base, and the system comprises a knowledge retrieval module which carries out the retrieval from an external knowledge base according to a user question to obtain a plurality of target text blocks; the evaluation generation module is used for independently evaluating each target text block through an evaluation model so as to identify retrieval noise, generating a correlation judgment result and a noise degree judgment result of each target text block, and generating internal memory information as a self-generated knowledge base based on a user question; and the diagnosis reasoning module is used for integrating the user question, each target text block, the corresponding correlation judgment result, the noise degree judgment result and the internal memory information into enhanced prompt information and inputting the enhanced prompt information into a large language model to generate a diagnosis reasoning answer. According to the method, retrieval noise interference can be effectively resisted, model knowledge support is strengthened by means of the self-generated knowledge base, the precision and timeliness of medical diagnosis reasoning are improved, and the requirements of the medical field for high-precision and strong-timeliness clinical decision making are met.

A modem chip receives a codeword including a transport block composed of a plurality of code blocks, and includes a hybrid automatic repeat request (HARQ) processing circuit configured to perform a HARQ-based processing operation with respect to the codeword, and an internal memory configured to store data generated by the HARQ processing circuit. The HARQ processing circuit includes a code block processing circuit configured to decode the plurality of code blocks in units of code blocks and perform a first cyclic redundancy check on each of the decoded plurality of code blocks, and a codeword processing circuit configured to perform a second cyclic redundancy check on a decoded transport block.

A compute tile includes a WCB that receives a workload of writing an output tensor of a convolution into a local memory of the compute tile. The local memory may be a SRAM. The WCB receives write transactions. A write transaction includes a data block, which is a part of the output tensor, and metadata describing one or more attributes of the data block. The WCB may store write transactions in its internal buffers. The WCB may determine whether to combine two write transactions, e.g., based on an operation mode or metadata in the write transactions. In embodiments where the WCB determines to combine the two write transactions, the WCB may combine the two write transactions into a new write transaction and write the new write transaction into the local memory or an internal memory of the WCB. The total number of write transactions for the workload can be reduced.

Disclosed in the embodiments of the present application are an internal memory, a chip and a related electronic device. A target processing unit (202) of an internal memory (102) comprises a plurality of groups of primary multipliers, a plurality of adder trees and a plurality of secondary multipliers, wherein one group of primary multipliers is connected to one secondary multiplier by means of one adder tree; one group of primary multipliers comprises a plurality of pairs of first multipliers; each adder tree comprises a first adder, a second adder and a third adder; each pair of first multipliers separately receives data to perform multiplication operations, and separately inputs output results into one first adder for addition operations; each second adder receives output results of a plurality of first adders or the upper-level second adder, so as to perform addition operations, and separately inputs the output results into the lower-level second adder or one third adder; and each third adder receives output results of a plurality of second adders to perform addition operations, and inputs the output results into one secondary multiplier for multiplication operations. Implementing the embodiments of the present application can improve the processing capability of the internal memory.

The invention discloses a construction method of an equipment temperature custom sorting table under new energy configuration and a related device. The construction method comprises the following steps: editing a configuration file; reading the configuration file, extracting the width, the height and the segmentation number of the table, and storing the mapping relation between the component name and the measuring point into a memory cache; reading the temperature value of each measuring point; the temperature values of all the measuring points are sorted, a sorting table is constructed according to the sorting result, the width and height of the table, segmentation data and the mapping relation between the component names and the measuring points, and the method and the related device can meet the quick response requirement of new energy equipment for temperature anomaly.

The invention relates to the technical field of heat dissipation, in particular to the technical field of heat dissipation of personal computers, workstations and servers, and particularly relates to an open type air duct memory radiator. The radiator comprises radiating fins, a limiting component and a heat-conducting medium, wherein the radiating fins, the limiting component and the heat-conducting medium surround a memory bank to form an open air duct. The cooling fins are symmetrically arranged on the two sides of the memory bank; the limiting component is arranged between the two cooling fins and abuts against the top of the memory bank. And the heat-conducting medium is arranged on a memory chip of the memory bank and is in contact with the inner surfaces of the adjacent cooling fins. According to the internal memory radiator, internal accumulated heat is reduced through the open air duct, and the air flowing efficiency is improved; and heat generated during operation of the memory bank is directly conducted to the cooling fins through the heat-conducting medium, so that the heat conduction efficiency is improved. The flow guide type design of an open type air channel is combined with the direct heat conduction design, efficient heat dissipation is achieved, and stable operation of the memory bank is guaranteed.

The embodiment of the invention provides a security defense method and device based on Hypervisor, and relates to the technical field of virtualization. The method comprises the steps of determining a memory processing type in response to a preset trigger operation; and calling an hvc command by calling a virtual machine monitor corresponding to the memory processing type so as to indicate a Hypervisor to execute a Hypervisor processing function corresponding to the hvc command. According to the embodiment of the invention, the distribution or release of the internal memory of the process is realized through the Hypervisor with higher authority, even if the kernel of the operating system is broken by a malicious application program, the integrity of a security mechanism of the operating system can still be ensured, and the effective defense of security threats of the operating system is realized.

The invention relates to a method for displaying data, the method being implemented in a display module comprising a screen and a control module adapted to control light elements of the screen as a function of data on a data interface. The display module includes a memory storing at least one image. The method comprises the following steps:-detecting (202; 203) when data onto the data interface is unavailable and a power signal is received through at least one power interface, accessing (204), by the control module, the at least one image in the memory; -controlling (205) the light emitting elements by the control module to display the at least one image.

A processor, method, and non-transitory computer-readable storage medium for processing template data and search data according to a search window applied to the search data. The search window comprising a set of offset positions. The processing is performed by a block matching engine (BME) that produces a tensor with difference values, and a convolutional engine (CE) that performs a convolutional operation on the tensor. The processing is performed in an iterative interleaved fashion, by dividing the set of offset positions into a plurality of subsets of offset positions. In parallel with processing of the first X offset positions by the CE, the BME generates the next X channels of the tensor, and which are subsequently pipelined through to the CE via an internal storage, etc.

A method and apparatus of direct memory access DMA between accelerator cards, an accelerator card, an accelerating platform and a non-volatile readable storage medium. The first accelerator card according to the present application can initiatively perform the initiation of the DMA, and, according to the idle-internal-memory datum of the second accelerator card as the data destination terminal recorded in the first accelerator card itself, write the datum directly into the internal memory of the second accelerator card in the mode of DMA, which does not require inquiring the idle-internal-memory address of the second accelerator card before the DMA, and does not require waiting for the second accelerator card to initiate the DMA. The solution realizes the direct DMA writing operation between different accelerator cards at the hardware level, and solves the problem in DMA operation between accelerator cards.

Methods, systems, and media comprising; a host device configured to execute one or more applications; and a processing-in-memory (PIM) subsystem comprising one or more memory arrays and one or more integrated compute elements, wherein the integrated compute elements comprise internal storage that is accessible during execution of instructions by the PIM subsystem operating on data stored in the one or more memory arrays, wherein the host device is configured to send commands over a command interface to initiate storing data in the one or more memory arrays over a data interface, and wherein the host device is configured to send data for storage in the internal storage of the PIM subsystem over the command interface.

The present disclosure relates to a skew resistance PID device and a processing method, and the device includes: Dual In-line Memory Modules (DIMMs) composed of multiple ranks respectively having multiple banks, and In-DIMM Processors (IDPs) that process internal memory operations; a memory controller; and a host CPU connected to the memory module through the memory controller and configured to enhance parallel processing performance of the IDPs by replicating a join key in units of bank sets and rank sets.

Even when the processing result at a certain layer in a convolutional neural network is input to the next layer and further subsequent layers, the processing can be executed more appropriately. A subnetwork included in a convolutional neural network includes a first layer, a second layer, a third layer, and a fourth layer, the output of the first layer is input to the second layer, the output of the second layer is input to the third layer, and the output of the first layer and the output of the third layer are input to the fourth layer, the acquisition unit divides and acquires the data to be processed so that the total size of the input data to each layer is equal to or less than the storage capacity of the internal memory.

Encryption system with an application-specific integrated circuit (ASIC) which has a permanent memory for the non-volatile storage of the operating system (OS) of a processor and software modules for encrypting the data memory of the processor and which has a hardware-implemented encryption algorithm, characterized in that a security module (SM) is integrated in the ASIC for autonomous booting of the operating system (OS), consisting of: - a symmetric cryptosystem (SK) for processing symmetric keys, - an asymmetric cryptosystem (AK) for the use of public and private keys, - a module for generating cryptographic hash functions (KH), - a module for the secure exchange of keys using hardware-implemented key exchange protocols (SP), - a key storage (SS) for the secure storage of root keys (WS), which are protected by appropriate measures in the physical structures of the ASIC and - a key management system (SMS) for the secure introduction of authenticated-encrypted key packets, and that the security module (SM) communicates with a central processing unit (CPU) via a communication interface (CS1), and that the central processing unit (CPU) communicates with at least one internal storage (IS) and one external storage (ES), as well as with at least one internal persistent storage (IP) and one external persistent storage (EP), such that the operating system (OS) is loaded by a second-stage bootloader (SSB) stored in the external persistent storage (EP), and then the operating system (OS) loads the applications, the second-stage bootloader (SSB) itself being decrypted and loaded by a first-stage bootloader (FSB) stored in the internal persistent storage (IP), and a public key (PUBOS) to verify the operating system (OS).and a symmetric key (KOS) to decrypt the operating system (OS), and that the contents of the internal memory (IS) and the external memory (ES) are decrypted by the security module (SM) during read accesses by the central management unit (CMU) or other modules integrated on the ASIC, and re-encrypted during write accesses by the same.

The utility model relates to a memory and an electronic device, the memory comprises a memory chip and a logic chip, the memory chip and the logic chip are packaged by adopting a three-dimensional stack packaging technology, the memory chip comprises a plurality of memory groups and interfaces corresponding to at least part of the memory groups, and the interfaces are connected with the memory groups. And the at least part of the memory groups are in data interaction with the logic chip through the independent interfaces. Through an advanced packaging mode and a distributed architecture design, the number of external communication interfaces of the memory chip is increased, the access mode of the memory to an internal memory group and a memory block is fundamentally changed, and an original centralized working mode is changed into a distributed working mode; therefore, the memory bank and the memory block are supported to execute related operations at the same time, the resource utilization rate of the memory is improved, a larger data bandwidth is provided for efficient calculation, and the bottleneck of a'storage wall 'faced by the memory is effectively relieved.

Systems are provided for a device. In one example, the device is configured for performing a transcutaneous vagus nerve stimulation (tVNS) treatment, the device including at least one electrode for generating a stimulation pulse, at least one acoustic stimulation device, an input device for inputting feedback data, an internal memory configured to store feedback, and a controller with instructions stored in memory thereof that when executed cause the controller to adjust one or more parameters of an acoustic stimulation provided by the at least one acoustic stimulation device.

The application provides a multi-machine alarm log association method and device, electronic equipment and a storage medium, and belongs to the technical field of communication. In the method, an internal memory graph is used for association. The internal memory graph can realize multi-machine (between nodes of different entity elements) association. The association points of the internal memory graph are at least one of the sub-nodes, that is, multiple association points are allowed to be set, the dimension of the association is greatly increased, the use of the internal memory graph compresses the internal memory occupation, the merging and multi-machine association are all carried out in the internal memory, the storage and network dependence is removed, and real-time and efficient association can be realized. When the multi-machine association is carried out, the association is combined according to the association point granularity, and the association calculation amount is greatly reduced. In addition, the first internal memory graph and the second internal memory graph can be automatically combined and expanded, the third internal memory graph manually triggered and expanded by the front end can be associated with the current attack event graph, and the expandability is good.

A system and an accelerator circuit includes an internal memory to store data received a memory associated with a processor and a filter circuit block comprising a plurality of circuit stripes, each circuit stripe including a filter processor, a plurality of filter circuits, and a slice of the internal memory assigned to the plurality of filter circuits, where the filter processor is to execute a filter instruction to read data values from the internal memory based on a first memory address, for each of the plurality of circuit stripes: load the data values in weight registers and input registers associated with the plurality of filter circuits of the circuit stripe to generate a plurality of filter results, and write a result generated using the plurality of filter circuits in the internal memory at a second memory address.

Embodiments of this application provide a resource management method and apparatus, an electronic device, and a non-volatile readable storage medium, and relate to the field of computer storage technology. The method includes: determining, in response to a target command sent by a host, a command type corresponding to the target command by a bridging device, the command type including an internal memory application command and an internal memory release command; determining, in a case that the target command is the internal memory application command, a first target resource allocated to the host based on an internal memory mapping table, and enabling a first channel between the first target resource and the host, the internal memory mapping table being configured for representing an internal memory allocation and usage status of internal memory devices; and determining, in a case that the target command is the internal memory release command, a second target resource indicated by the internal memory release command, and disabling a second channel between the second target resource and the host. Accordingly, the bridging device is used as a core for resource management and allocation in a resource management system, thereby shortening the processing time required for resource allocation or release, and improving the performance of the resource management system.

The invention discloses a tobacco leaf modified atmosphere insecticidal system and method in a roadway type dense shelf warehouse based on flexible parameter configuration. The system comprises a roadway sealing subsystem, a gas regulation and control subsystem, an environment monitoring subsystem and a central control subsystem. A memory is arranged in an industrial computer of the central control subsystem, and a flexible parameter database and a flexible parameter configuration module are stored in the memory. The method comprises the following steps: sealing a roadway to form an independent modified atmosphere insecticidal unit, calling a first parameter set and a second parameter set according to input insecticidal object information, performing gas replacement and maintenance control according to the second parameter set, and dynamically triggering trace nitrogen supplementation, carbon dioxide supplementation, linkage temperature adjustment and linkage humidity adjustment deviation correction control based on real-time monitoring data. According to the method, one-product-one-strategy precise insect killing for different tobacco leaf materials is achieved, the problems of fixed parameters and poor adaptability of a traditional process are solved, and the method has the advantages of being thorough in insect killing, good in quality guarantee and low in energy consumption.

The invention relates to a memory device and an operating method thereof. According to an embodiment of the present disclosure, an operating method of a memory device including a memory bank including a plurality of edge memory cell arrays and a plurality of internal memory cell arrays arranged between the plurality of edge memory cell arrays may be provided. The operating method may include: receiving a fine-grained refresh command; identifying a refresh target pointer value for a refresh target determination list, the refresh target determination list including a plurality of row addresses of the memory bank; identifying a pointing row address corresponding to a refresh target pointer value among the plurality of row addresses; determining a first memory cell array type corresponding to the pointing row address; and performing a first refresh operation for a refresh target number of fine-grained refresh target row addresses, wherein the refresh target number is determined based on the first memory cell array type.