Tcp/ip processor and engine using rdma

Abstract

A TCP / IP processor and data processing engines for use in the TCP / IP processor is disclosed. The TCP / IP processor can transport data payloads of Internet Protocol (IP) data packets using an architecture that provides capabilities to transport and process Internet Protocol (IP) packets from Layer 2 through transport protocol layer and may also provide packet inspection through Layer 7. The engines may perform pass-through packet classification, policy processing and / or security processing enabling packet streaming through the architecture at nearly the full line rate. A scheduler schedules packets to packet processors for processing. An internal memory or local session database cache stores a TCP / IP session information database and may also store a storage information session database for a certain number of active sessions. The session information that is not in the internal memory is stored and retrieved to / from an additional memory. An application running on an initiator or target can in certain instantiations register a region of memory, which is made available to its peer(s) for access directly without substantial host intervention through RDMA data transfer.

Description

CROSS REFERENCE TO RELATED APPLICATIONS[0001]This application is a divisional of U.S. patent application Ser. No. 10 / 459,349 filed on Jun. 10, 2003 titled TCP / IP Processor and Engine Using RDMA and allowed, which claims the benefit of U.S. Provisional Patent Application Ser. No. 60 / 388,407, filed on Jun. 11, 2002 titled A High Performance IP Storage Processor and now expired, both of which are hereby incorporated by reference in their entirety.[0002]This application is related to the following non-provisional applications, each filed on Jun. 10, 2003 claiming the benefit of U.S. Provisional Patent Application Ser. No. 60 / 388,407, and each of which is hereby incorporated by reference for all purposes: 10 / 458,844 titled Data Processing System Using Internet Protocols, which is Pending, 10 / 458,855 titled Data Processing System Using Internet Protocols and RDMA, which is Pending, 10 / 459,019 titled Memory System for a High Performance IP Processor, which is Pending, 10 / 459,297 titled Hig...

AI Technical Summary

Benefits of technology

"The described hardware processor eliminates or minimizes the processing overhead and latency caused by the TCP / IP protocol stack, allowing for high-line rate storage or data traffic over IP. It achieves this by implementing a high-speed memory subsystem that reduces the processing cycles required for each packet. The processor also includes integrated security features for secure storage of data traffic. Additionally, the processor reduces the classification overhead required for network traffic management, leading to improved storage area management costs. Overall, the described processor architecture provides a more efficient and high-speed solution for transporting storage traffic over IP."

Problems solved by technology

The overhead comes from various aspects of the software TCP / IP stack including checksum calculation, memory buffer copy, processor interrupts on packet arrival, session establishment, session tear down and other reliable transport services.

The software stack overhead becomes prohibitive at higher lines rates.

Similar issues occur in networks with lower line rates, like wireless networks, that use lower performance host processors.

This is an expensive compute intensive operation performed on each packet involving each received byte in the packet.

When the line rates increase to above 1 Gbps, the memory size overhead and memory speed bottleneck resulting from these add significant cost to the network cards and also cause huge performance overhead.

Another function that consumes a lot of processor resources is the copying of the data to / from the network card buffers, kernel buffers and the application buffers.

Interrupting these processors on arrival of small packets will cause severe performance degradation due to context switching overhead, pipeline flushes and refilling of the pipelines.

When the block storage traffic is transported over TCP / IP networks, these performance issues become critical, severely impacting the throughput and the latency of the storage traffic.

However, there usually isn't alignment relationship between the TCP segments and the protocol data units that are encapsulated by TCP packets.

This becomes an issue when the packets arrive out of order, which is a very frequent event in today's networks.

This can be expensive from the size of the memory storage required and also the performance that the memory subsystem is expected to support, particularly at line rates above 1 Gbps.

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