474 results about "Packet scheduling" patented technology

A runtime adaptable search processor is disclosed. The search processor provides high speed content search capability to meet the performance need of network line rates growing to 1 Gbps, 10 Gbps and higher. he search processor provides a unique combination of NFA and DFA based search engines that can process incoming data in parallel to perform the search against the specific rules programmed in the search engines. The processor architecture also provides capabilities to transport and process Internet Protocol (IP) packets from Layer 2 through transport protocol layer and may also provide packet inspection through Layer 7. Further, a runtime adaptable processor is coupled to the protocol processing hardware and may be dynamically adapted to perform hardware tasks as per the needs of the network traffic being sent or received and/or the policies programmed or services or applications being supported. A set of engines may perform pass-through packet classification, policy processing and/or security processing enabling packet streaming through the architecture at nearly the full line rate. A high performance content search and rules processing security processor is disclosed which may be used for application layer and network layer security. scheduler schedules packets to packet processors for processing. An internal memory or local session database cache stores a session information database for a certain number of active sessions. The session information that is not in the internal memory is stored and retrieved to/from an additional memory. An application running on an initiator or target can in certain instantiations register a region of memory, which is made available to its peer(s) for access directly without substantial host intervention through RDMA data transfer. A security system is also disclosed that enables a new way of implementing security capabilities inside enterprise networks in a distributed manner using a protocol processing hardware with appropriate security features.

A runtime adaptable security processor is disclosed. The processor architecture provides capabilities to transport and process Internet Protocol (IP) packets from Layer 2 through transport protocol layer and may also provide packet inspection through Layer 7. Further, a runtime adaptable processor is coupled to the protocol processing hardware and may be dynamically adapted to perform hardware tasks as per the needs of the network traffic being sent or received and/or the policies programmed or services or applications being supported. A set of engines may perform pass-through packet classification, policy processing and/or security processing enabling packet streaming through the architecture at nearly the full line rate. A high performance content search and rules processing security processor is disclosed which may be used for application layer and network layer security. A scheduler schedules packets to packet processors for processing. An internal memory or local session database cache stores a session information database for a certain number of active sessions. The session information that is not in the internal memory is stored and retrieved to/from an additional memory. An application running on an initiator or target can in certain instantiations register a region of memory, which is made available to its peer(s) for access directly without substantial host intervention through RDMA data transfer. A security system is also disclosed that enables a new way of implementing security capabilities inside enterprise networks in a distributed manner using a protocol processing hardware with appropriate security features.

A transmission systems suitable for video.

A method for scheduling the delivery of multimedia data packets over a communications medium with a limited bandwidth. The packets may contain data representing images, sounds, or other media which are to be delivered from a source or server to a recipient or client. The 6 method described here minimizes the delay between the point in time when a client requests the multimedia data and the point in time when the client may start presenting the data without risk of interruption, for a given communications bandwidth. This method also determines the minimum buffer sizes needed by the client in order to present this multimedia data subject to the specified bandwidth limit.

The invention relates to transmitting data elements of a data stream based on a priority and target buffer fill levels at a receiving device. A transmitter controller transmits data elements of a data element class with a highest priority first, for reaching an associated buffer fill level and then turns to data elements of successively lower priorities, until the available bandwidth is exhausted.

Methods and apparatus for providing an Anti-Flooding Flow-Control (AFFC) mechanism suitable for use in defending against flooding network Denial-of-Service (N-DoS) attacks is described. Features of the AFFC mechanism include (1) traffic baseline generation, (2) dynamic buffer management, (3) packet scheduling, and (4) optional early traffic regulation. Baseline statistics on the flow rates for flows of data corresponding to different classes of packets are generated. When a router senses congestion, it activates the AFFC mechanism of the present invention. Traffic flows are classified. Elastic traffic is examined to determine if it is responsive to flow control signals. Flows of non-responsive elastic traffic is dropped. The remaining flows are compared to corresponding class baseline flow rates. Flows exceeding the baseline flow rates are subject to forced flow rate reductions, e.g., dropping of packets.

The complexity of user designs, the limited capacity of FPGA chips, and the limited number of chip pinouts have resulted in the development of inter-chip communication technology that necessitates the transfer of a large amount of data across a limited number of pins in the shortest amount of time. The inter-chip communication system transfers signals across FPGA chip boundaries only when these signals change values. Thus, no cycles are wasted and every event signal has a fair chance of achieving communication across chip boundaries. The inter-chip communication system includes a series of event detectors that detect changes in signal values and packet schedulers which can then schedule the transfer of these changed signal values to another designated chip. Working with a plurality of signal groups that represents signals at the separated connections, the event detector detects events (or changes in signal values). When an event has been detected, the event detector alerts the packet scheduler. The packet scheduler employs a token ring scheme as follows. When the packet scheduler receives a token and detects an event, the packet scheduler “grabs” the token and schedules the transmission of this packet in the next packet cycle. If, however, the packet scheduler receives the token but does not detect an event, it will pass the token to the next packet scheduler. At the end of each packet cycle, the packet scheduler that grabbed the token will pass the token to the next logic associated with another packet.

A new scheduling discipline is disclosed for the forward link of a wireless network such as a CDMA network. The new discipline, which we denominate Modified LWDF (M-LWDF), resembles the known LWDF discipline in that only one queue is served at a time, and the queue to be served is that having the largest weighted delay. According to M-LWDF, the weighted delay of the i'th queue is defined aswherein Wi(t) is a packet delay, a queue length, or an increasing function of packet delay or queue length for the i'th queue, ci(t) is a weight coefficient descriptive of channel conditions for the i'th user, and gammai is a fixed constant that can be chosen arbitrarily. We have found that if any scheduling discipline can yield stable queues for a given traffic pattern of arriving packets, then M-LWDF can, even under changing channel conditions. Moreover, we have found that M-LWDF can provide favorable QoS in terms of delay bounds.

A method of controlling link adaptation and packet scheduling in an HSDPA (High Speed Downlink Packet Access) radio system and an HSDPA base station communicating over a control channel with one or more user equipment units is provided. According to one embodiment the base station includes a device for receiving feedback information from the user equipment. The base station further includes a device for calculating a quality estimate related to the feedback information and executing link adaptation and packet scheduling based on the calculated quality estimate.

The present invention defines a method and apparatus to extend class-based queuing (CBQ) with multiple “behavioral” queues per class, to include a dynamic weighting mechanism between these queues. The packets are forwarded from the behavioral queues according to the weighting assigned to each queue. The weighting for packet scheduling of the queues is adjusted to account for additional flow going through the queues. The weight of a queue is controlled relative to the weight available to other queues. When a flow is reclassified, the queue weights is readjusted accordingly. Well behaved flows experience low delay and can thus achieve a fair bandwidth allocation without having to have multiple packets queued to compete with non-adaptive aggressive flows.

In a network router, a tree structure or a sorting network is used to compare scheduling values and select a packet to be forwarded from an appropriate queue. In the tree structure, each leaf represents the scheduling value of a queue and internal nodes of the structure represent winners in comparisons of scheduling values of sibling nodes of the tree structure. CBR scheduling values may first be compared to select a queue and, if transmission from a CBR queue is not timely, a packet may be selected using WFQ scheduling values. The scheduling values are updated to reflect variable packet lengths and byte stuffing in the prior packet. Scheduling may be performed in multiple stages.

A method, apparatus and system for scheduling data packets in a wireless communications system. The invention includes determining a priority for at least one data packet, wherein determining the priority of the data packet is based at least on a plurality of quality of service factors, wherein each of the plurality of QoS factors has a corresponding weighting factor and the determined priority includes minimum-performance guarantees. The invention further includes scheduling transmission of the at least one data packet based at least on the determined priority.

A method of performing packet level transmission scheduling in a communications systems including a plurality of cells,each cell including a base station and plurarity of mobile stations. The method performs scheduling while considering radio resource allocation at the wireless access node. In a schedule plan phase of the method, average power and average effective data rate are determined for all mobile stations in the system. In addition, the planned fractions of frames rho that each mobile in the system will transmit is determined so that resources are allocated fairly. In the actual schedule phase of the method, current power and effective data rate values are compared to the average power values. This information along with the rho values is used to determine the actual schedule of packet transmissions for all mobiles in a particular cell.

Methods and apparatus for providing an Anti-Flooding Flow-Control (AFFC) mechanism suitable for use in defending against flooding network Denial-of-Service (N-DoS) attacks is described. Features of the AFFC mechanism include (1) traffic baseline generation, (2) dynamic buffer management, (3) packet scheduling, and (4) optional early traffic regulation. Baseline statistics on the flow rates for flows of data corresponding to different classes of packets are generated. When a router senses congestion, it activates the AFFC mechanism of the present invention. Traffic flows are classified. Elastic traffic is examined to determine if it is responsive to flow control signals. Flows of non-responsive elastic traffic is dropped. The remaining flows are compared to corresponding class baseline flow rates. Flows exceeding the baseline flow rates are subject to forced flow rate reductions, e.g., dropping of packets.

Opportunistic packet scheduling apparatus and method in a multihop relay wireless access communication system are provided. The method includes aggregating channel condition information which are estimated and reported by Mobile Stations (MSs) and a Relay Station (RS) for each MS path in a cell, determining a Modulation and Coding Scheme (MCS) level which corresponds to the aggregated channel condition information for a corresponding hop of each MS path, determining a transmittable coded packet size and a number of subchannels required for the packet transmission depending on the determined MCS level, and calculating a current radio resource efficiency of the corresponding MS path using the determined coded packet size and the determined number of the subchannels.

A Wide Register Set (WRS) is used in a packet processor to increase performance for certain packet processing operations. The registers in the WRS have wider bit lengths than the main registers used for primary packet processing operations. A wide logic unit is configured to conduct logic operations on the wide register set and in one implementation includes hardware primitives specifically configured for packet scheduling operations. A special interlocking mechanism is additionally used to coordinate accesses among multiple processors or threads to the same wide register address locations. The WRS produces a scheduling engine that is much cheaper than previous hardware solutions with higher performance than previous software solutions. The WRS provides a small, compact, flexible, and scalable scheduling sub-system and can tolerate long memory latencies by using cheaper memory while sharing memory with other uses. The result is a new packet processing architecture that has a wide range of cost/performance points, based on desired scheduling requirements.

The invention relates to a spatial-orthogonality-based large-scale MIMO system pilot frequency distribution method. The method comprises the following steps: 1) obtaining the statistical covariance matrix information of every user terminal channel through a base station; 2) under the condition that the statistical covariance matrix information is known, obtaining the condition for achieving no-speed-loss transmission when two users located in different cells on the same time-frequency block perform pilot frequency multiplexing; 3) according to the information obtained in step 1), contrasting and calculating the spatial orthogonality degree among the channels of different users through the base station, and utilizing the condition of achieving the no-speed-loss transmission in step 2) to perform greedy packet scheduling on the users under the principle of maximizing the system sum speed; and 4) performing pilot frequency distribution on every user group. Under the condition that the user side does not know instantaneous channel state information, the spatial-orthogonality-based large-scale MIMO system pilot frequency distribution method can achieve the pilot frequency multiplexing and meanwhile effectively reduce the influence caused by the problem of pilot frequency pollution and improve the system throughput performance.