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2578results about "Baseband system details" patented technology

System and method for transmission-line termination by signal cancellation, and applications thereof

An active terminating device (30) for an electrical transmission line with optional line-receiving and line-driving capabilities. The basic device is a two-terminal unit, denoted as a Signal Canceling Unit (SCU), which sensesthe signal available at its terminals (34a, 34b), and applies negative feedback in order to cancel and absorb the signal. When applied to the end of a transmission line (15a, 15b) as part of wired communication network, the SCU functions as a terminator. When connected in the middle of such wired transmission line, the SCU splits the transmission line into two separate and isolated segments. In such a configuration, the SCU can be used to isolate a portion of a network from signal degradation due to noise or bridge-tap. Furthermore, the two isolated segments may each employ independent communications, such that no interference exists between the segments. In another embodiment, line receiver functionality is integrated into the SCU, designated as a Signal Canceling and Receiving Unit (SCRU) (90). The SCRU can perform all the SCU functions, and also serves as a line receiver in the communication network. In yet another embodiment, line driver functionality is integrated into the SCRU, designated as a Signal Canceling, Receiving and Transmitting Unit (SCRTU) (120). The SCRTU can perform all the SCRU functions, and also serves as a line driver in the communication network. Upon connecting multiple SCRTU's to a continuous transmission line, terminated independent point-to-point communication segments are formed.

Synchronous processing method based on CMMB signals

The invention provides a synchronous processing method based on new CMMB (China Mobile Multimedia Broadcasting) synchronous signals. The CMMB synchronous signals comprise first training sequences and second training sequences; the first training sequences comprise CAZAC (Constant Amplitude Zero Auto Correlation) sequences, and the second training sequences comprise PN (Pseudo-Noise) sequences; in the synchronous processing method, the CAZAC sequences are utilized to achieve coarse symbol timing offset estimation and decimal frequency offset coarse estimation; the PN sequences are utilized to achieve the estimation of strongest path time delay in multipath, and the multipath is taken as coarse symbol timing positioning; the CAZAC sequences and the PN sequences are utilized to achieve the integer frequency offset estimation; the fast Fourier transform (FFT) is performed on the PN sequences to achieve the channel response estimation so as to estimate a first path time delay and achieve the fine symbol timing position estimation; and a maximum likelihood (ML) criterion is utilized to process the PN sequences in the second training sequences to obtain the decimal frequency offset fine estimation. The synchronous processing method can effectively improve the synchronous accuracy and can achieve better synchronization performance in the mobile communication environment with low signal-to-noise ratio.

Massively parallel supercomputer

InactiveUS7555566B2Massive level of scalabilityUnprecedented level of scalabilityError preventionProgram synchronisationPacket communicationSupercomputer
A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node may be used individually or simultaneously to work on any combination of computation or communication as required by the particular algorithm being solved or executed at any point in time. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency. In the preferred embodiment, the multiple networks include three high-speed networks for parallel algorithm message passing including a Torus, Global Tree, and a Global Asynchronous network that provides global barrier and notification functions. These multiple independent networks may be collaboratively or independently utilized according to the needs or phases of an algorithm for optimizing algorithm processing performance. For particular classes of parallel algorithms, or parts of parallel calculations, this architecture exhibits exceptional computational performance, and may be enabled to perform calculations for new classes of parallel algorithms. Additional networks are provided for external connectivity and used for Input/Output, System Management and Configuration, and Debug and Monitoring functions. Special node packaging techniques implementing midplane and other hardware devices facilitates partitioning of the supercomputer in multiple networks for optimizing supercomputing resources.
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