59results about "Input/output impedence modification" patented technology

A component having a bus termination. A component (3, 4, 7-9, 13, 27) for a combustion appliance, such as an appliance having a boiler, the component (3, 4, 7-9, 13, 27) comprising an outer surface and a tangible electrical interface (30, 32, 35, 36) configured to be electrically connected by a user such that the tangible electrical interface (30, 32, 35, 36) is in a short circuit condition, the tangible electrical interface (30, 32, 35, 36) is electrically disconnected by the user such that the tangible electrical interface (30, 32, 35, 36) is in an open condition; wherein the tangible electrical interface (30, 32, 35, 36) is arranged on an outer surface of the component (3, 4, 7-9, 13, 27) such that the tangible electrical interface (30, 32, 35, 36) is accessible to the user; the components (3, 4, 7-9, 13, 27) comprise a first and a second bus wire.

An example method includes for a first calibration impedance, determining a first pulldown calibration code to set a replica pulldown driver circuit to a first impedance. A first pullup calibration code is determined for a replica pullup driver circuit based on the first impedance. The first pulldown and pullup calibration codes are stored. For a second calibration impedance, a second pulldown calibration code is determined to set the replica pulldown driver circuit to a second impedance. A second pullup calibration code is determined for the replica pullup driver circuit based on the second impedance. The second pulldown and pullup calibration codes are stored. The first and second calibration impedances may be on-die calibration impedances. The first and second calibration impedances may be external calibration impedances. The first and second calibration impedances may be provided by a calibration impedance having an adjustable impedance.

Component with bus termination. A component (3, 4, 7-9, 13, 27) for a combustion appliance such as an appliance having a boiler, the component (3, 4, 7-9, 13, 27) comprising an outer surface and a tangible, electric interface (30, 32, 35, 36) configured to be electrically connected by a user such that the tangible, electric interface (30, 32, 35, 36) is in a short circuit condition and configured to be electrically disconnected by the user such that the tangible, electric interface (30, 32, 35, 36) is open circuit condition; wherein the tangible, electric interface (30, 32, 35, 36) is arranged on the outer surface of the component (3, 4, 7-9, 13, 27) such that the tangible, electric interface (30, 32, 35, 36) is accessible to the user; the component (3, 4, 7-9, 13, 27) comprising first and second bus wires.

This invention provides an integrated circuit trimming method based on trimming code separation, belonging to the field of integrated circuit trimming technology. The method includes: calculating a trimming code based on the initial and target values ​​of the parameter to be trimmed, and establishing a mapping relationship between the trimming code and the trimming parameter; based on the mapping relationship between the trimming code and the trimming parameter, reversing the highest position of the trimming code to obtain the applied trimming code, obtaining the mapping relationship between the applied trimming code and the trimming parameter; and trimming the integrated circuit chip based on the mapping relationship between the applied trimming code and the trimming parameter. This solves the problems of complex code search logic and low trimming efficiency in existing methods based on digital trimming codes.

A device for transmitting first data to an external device and receiving second data from the external device is provided. The device includes: a voltage mode driver connected to a first node, the voltage mode driver including a pull-up resistor circuit and a pull-down resistor circuit, the pull-up resistor circuit including a plurality of pull-up resistors, and the pull-down resistor circuit including a plurality of pull-down resistors; a current source circuit connected to a second node and including a first current source and a second current source; a pre-driver configured to control the voltage mode driver and the current source circuit, based on the first data; a receiver connected to the second node and configured to obtain the second data based on a voltage level of the second node; and a hybrid resistor connected between the first node and the second node.

A signal generator circuit is provided. The gate of a first transistor and the drain of a second transistor are coupled to a first output terminal. The sources of the first and second transistors are coupled to a first power terminal. The drains of the first and third transistors, and the gate of the second transistor are coupled to a second output terminal. The gate of the third transistor is coupled to a second power terminal. The source of the third transistor is coupled to a third power terminal. A fourth transistor is coupled to the second power terminal and the first output terminal. When the third transistor is turned off, a first bias circuit turns on the fourth transistor. A second bias circuit provides a first predetermined voltage to the second transistor. A third bias circuit provides a second predetermined voltage to the first transistor.

Apparatuses and methods for calibrating adjustable impedances of a semiconductor device are disclosed in the present application. An example apparatus includes a register configured to store impedance calibration information and further includes programmable termination resistances having a programmable impedance. The example apparatus further includes an impedance calibration circuit configured to perform a calibration operation to determine calibration parameters for setting the programmable impedance of the programmable termination resistances. The impedance calibration circuit is further configured to program the impedance calibration information in the register related to the calibration operation.

High-swing push-pull assisted Voltage Mode Logic (VML) driver circuits can enhance output voltage amplitude to improve efficiency and performance in electronic applications. For example, this is accomplished by utilizing a primary current generator circuit that is powered by a supply voltage to generate a primary current. The primary current is provided, through a switching circuit, to an output node that, in response to an input signal, generates a first output voltage. Further, a supplementary current generator circuit is coupled to the switching circuit to generate a secondary current. The combination of the primary and secondary currents increases the amplitude of the first output voltage, thereby enabling the VML driver circuit to deliver enhanced performance, particularly in applications requiring precise voltage control and high efficiency.

A circuit with calibration function includes a fully differential amplifier circuit, two voltage generation circuits, two multiplexers, a comparator and a digital logic circuit. The fully differential amplifier circuit amplifies a pair of differential input voltages to generate a pair of differential output voltages. One voltage generation circuit utilizes a first current to flow through a capacitor to generate a first voltage. The other voltage generation circuit utilizes a second current to flow through a resistor to generate a second voltage. The multiplexers provide the pair of differential output voltages or the first and second voltages to the comparator according to a digital control signal. The digital logic circuit generates a first digital code to adjust a capacitance of the capacitor or a second digital code to adjust DC voltage levels of the pair of differential output voltages according to the comparison signal provided by the comparator.

Control logic in a memory device initiates an impedance (ZQ) calibration to be performed by a calibration circuit coupled to an output buffer of an input / output circuit the I / O circuit of the memory device. A first set of calibration units of the calibration circuit includes a first calibration unit and a second calibration unit, where a first calibration code including a first sequence of bit values is generated having at least one bit value of the first sequence generated by a first transistor set of the first calibration unit and a second transistor set of the second calibration unit. The first calibration code is provided to one or more pull-up units of the output buffer, where the first calibration code is used to calibrate a first impedance of the one or more pull-up units. A second calibration code including a second sequence of bit values is generated by a second set of calibration units and a third set of calibration units. The second calibration code is provided to one or more pull-down units of the output buffer to calibrate a second impedance of the one or more pull-down units.

An example method includes for a first calibration impedance, determining a first pulldown calibration code to set a replica pulldown driver circuit to a first impedance. A first pullup calibration code is determined for a replica pullup driver circuit based on the first impedance. The first pulldown and pullup calibration codes are stored. For a second calibration impedance, a second pulldown calibration code is determined to set the replica pulldown driver circuit to a second impedance. A second pullup calibration code is determined for the replica pullup driver circuit based on the second impedance. The second pulldown and pullup calibration codes are stored. The first and second calibration impedances may be on-die calibration impedances. The first and second calibration impedances may be external calibration impedances. The first and second calibration impedances may be provided by a calibration impedance having an adjustable impedance.

A device for transmitting first data to an external device and receiving second data from the external device is provided. The apparatus includes: a voltage mode driver connected to a first node, the voltage mode driver including a pull-up resistor circuit and a pull-down resistor circuit, the pull-up resistor circuit including a plurality of pull-up resistors, and the pull-down resistor circuit including a plurality of pull-down resistors; the current source circuit is connected to the second node and comprises a first current source and a second current source; a pre-driver configured to control the voltage mode driver and the current source circuit based on first data; a receiver connected to the second node and configured to obtain second data based on a voltage level of the second node; and a hybrid resistor connected between the first node and the second node.

The invention discloses a feedback expansion conversion device and method for an encoder, the output end of the encoder is connected with the feedback expansion conversion device, the encoder outputs a differential signal, and the feedback expansion conversion device comprises a signal buffer circuit, a signal processing circuit and a feedback expansion conversion circuit, the input end of the driver is connected with the output end of the encoder so as to perform driving enhancement on the differential signal to generate an enhanced signal; and the interface expansion circuit comprises a plurality of groups of connectors, and the input ends of the connectors are respectively connected with the signal buffer circuit so as to realize expansion output of the enhanced signal. Through the design of signal buffering, multi-path expansion, impedance matching, overcurrent protection and electrical isolation, the transmission stability, the driving capability, the system expansibility and the anti-interference capability of feedback signals of the encoder are remarkably improved, multiple pain points in the prior art are solved, and the precision, the reliability and the maintenance convenience of the shaft control system are improved.

The invention relates to an impedance adjusting circuit and a semiconductor device including the same. An impedance adjustment circuit includes a calibration circuit and a code update circuit. The calibration circuit performs an impedance adjustment operation to generate a source impedance code in response to activation of the impedance adjustment enable signal. The code update circuit performs a first channel code update operation according to the source impedance code to update the first channel impedance code when a first channel code update request signal is input. When a second channel code update request signal is input, performing a second channel code update operation according to the first channel impedance code to update the second channel impedance code; and blocking the second channel code update operation when the second channel code update request signal is input while the first channel code update operation is performed.

A termination circuit of a receiver is provided. The termination circuit includes an input resistor, a capacitor, a first resistor, a second resistor, a third resistor and a bias signal generator. The input resistor is coupled between an input terminal of the termination circuit and a first reference voltage. The capacitor is coupled between a first node of the termination circuit and an output terminal of the termination circuit. The first resistor is coupled between the first node and a second node of the termination circuit. The second resistor is coupled between the second node and the output terminal. The third resistor is coupled between the second node and a control terminal of the termination circuit. In addition, the bias signal generator is coupled to the control terminal, and generates a control signal positively correlated with a second reference voltage to the control terminal.

Embodiments of the present application relate to the field of memories, and provide a data input / output circuit and a memory. The data input / output circuit comprises: a parallel-to-serial circuit, configured to receive N pieces of data and output the N pieces of data in series within a first time period; a read enable signal generation circuit configured to generate a read enable signal, the read enable signal being at an active level within the first time period; a resistance control circuit electrically connected to the read enable signal generation circuit and configured to receive a termination resistance control code, an output driving resistance control code and the read enable signal, and select, on the basis of the read enable signal, to output the termination resistance control code or output the output driving resistance control code; and an output driving circuit electrically connected to the parallel-to-serial circuit and the resistance control circuit and configured to receive the N pieces of data and a signal outputted by the resistance control circuit, and configure, on the basis of the signal outputted by the resistance control circuit, an output driving resistance value and output the N pieces of data, or configure a termination resistance value, wherein N is a positive integer greater than 1.

Provided is a non-volatile memory device including an input / output (I / O) pin configured to transfer data to or receive data from a memory controller, and a plurality of memory dies connected to the I / O pin, the plurality of memory dies including a target die, a first non-target die, and a second non-target die, wherein the first non-target die includes a first on-die-termination (ODT) circuit connected to the I / O pin and provides a first ODT resistance value based on a first distance between the target die and the first non-target die, and wherein the second non-target die includes a second ODT circuit connected to the I / O pin and provides a second ODT resistance value based on a second distance between the target die and the second non-target die, the second ODT resistance value being different from the first ODT resistance value.

Disclosed is a memory device, which comprises a memory cell array that includes a plurality of memory cells; an input / output circuit configured to transmit data received from an outside (e.g., an external source) through a data pad to the memory cell array or transmit data read from the memory cell array to the external source; and an impedance calibration circuit configured to generate an impedance calibration code that is applied to the input / output circuit. The impedance calibration circuit is further configured to divide a total impedance calibration section into a plurality of sub-impedance calibration sections, and perform at least one sub-impedance calibration in each of the plurality of sub-impedance calibration sections, the at least one sub-impedance calibration corresponding to at least one of a plurality of impedance modes.

The present invention provides a circuitry including a driver, a band-pass filter, a routing trace and at least one receiver is disclosed. The driver is configured to generate a first signal. The band-pass filter is configured to filters the first signal to generate a second signal. The second signal passes through the routing trace to generate a third signal. The at least one receiver is configured to receive the third signal to generate an output signal.

The present invention provides a circuit capable of automatically adjusting impedance thereof having a wide adjustment range and high accuracy by selecting a pull-up code and a pull-down code for obtaining resistances closest to those of a first reference resistor and a second reference resistor, respectively, using a first reference P-code and a second reference P-code, and a first reference N-code and a second reference N-code.

Provided are a ZQ calibration circuit and a ZQ calibration method. The ZQ calibration circuit includes: a first calibration circuit; and a second calibration circuit sharing a first ZQ voltage with the first calibration circuit, wherein the first ZQ voltage is generated from a ZQ pad connected to an external resistor. The first calibration circuit includes: a first comparator; a second comparator; a first pull-up counter; a first pull-up driver; and a first switch electrically interconnecting the first pull-up counter. The second calibration circuit includes: a third comparator; a fourth comparator; a second pull-up counter; a second pull-up driver; and a second switch connected to the second pull-up counter and turned on based on a second logic level of the clock signal to electrically interconnect the second pull-up counter and the second pull-up driver.

This application relates to data driver circuits, in particular to laser drivers. A driver is configured to receive an input signal and generate a corresponding driver output signal for driving an output device, such as a laser. A bias generator has a first output branch connected to an output node of the bias generator and a first control loop is configured to control a current in the first output branch to have a defined relationship to a bandgap referred current to provide a first bias current for biasing the output device. A driver output node is coupled to the driver and also to the output node of the bias generator, for outputting the driver output signal and the first bias current to the output device.

The present invention provides a circuitry (100, 200, 300) including a driver (114, 214), a band-pass filter (120, 220), a routing trace (130, 230) and at least one receiver (140, 144, 240_1 - 240_N, 244_1 - 244_N) is disclosed. The driver (114, 214) is configured to generate a first signal. The band-pass filter (120, 220) is configured to filters the first signal to generate a second signal. The second signal passes through the routing trace (130, 230) to generate a third signal. The at least one receiver (140, 144, 240_1 - 240_N, 244_1 - 244_N) is configured to receive the third signal to generate an output signal.

The present disclosure provides a single-loop memory device, a double-loop memory device, and a ZQ calibration method. The single-loop memory device includes: a master chip and a plurality of slave chips each provided with a first transmission terminal and a second transmission terminal, where the second transmission terminal of the master chip is connected to the first transmission terminal of the slave chip of a first stage, and the second transmission terminal of the slave chip of each stage is connected to the first transmission terminal of the slave chip of a next stage; and the master chip is provided with a first signal receiver, and the slave chip is provided with a second signal receiver.

The present disclosure describes embodiments of driver circuit. The driver circuit includes a first impedance element electrically coupled to a first inverter circuit and a second impedance element electrically coupled to the first impedance element and a second inverter circuit. For a first encoding using the driver circuit, the first inverter circuit and the second inverter circuit are controlled such that a first current flows through the first and second impedance elements, the first current having a first value and a first direction. For a second encoding using the driver circuit, the first inverter circuit and the second inverter circuit are controlled such that a second current flows through the first and second impedance elements, the second current having a second value and a second direction. The first value is substantially the same as the second value and the first direction is opposite to the second direction.

Provided is a non-volatile memory device including an input / output (I / O) pin (P11) configured to transfer data to or receive data from a memory controller (20_1), and a plurality of memory dies (100a to 100n) connected to the I / O pin (P11), the plurality of memory dies (100a to 100n) including a target die (100a), a first non-target die (100b), and a second non-target die (100c), wherein the first non-target die (100b) includes a first on-die-termination (ODT) circuit (110b) connected to the I / O pin (P11) and provides a first ODT resistance value (RTT2) based on a first distance between the target die (100a) and the first non-target die (100b), and wherein the second non-target die (100c) includes a second ODT circuit (110c) connected to the I / O pin (P11) and provides a second ODT resistance value (RTT3) based on a second distance between the target die (100a) and the second non-target die (100c), the second ODT resistance value (RTT3) being different from the first ODT resistance value (RTT3).

There is provided a non-volatile memory device including an on-die interconnect circuit, including: an input / output (I / O) pin configured to transmit data to or receive data from a memory controller; and a plurality of memory dies connected to the I / O pin, the plurality of memory dies including a target die, a first non-target die, and a second non-target die, where the first non-target die includes a first die-up-die (ODT) circuit connected to the I / O pin, and the second non-target die includes a second die-up-die (ODT) circuit connected to the I / O pin. A first on-die termination (ODT) circuit provides a first ODT resistance value based on a first distance between a target die and a first non-target die; and wherein the second non-target die includes a second ODT circuit connected to the I / O pin, the second ODT circuit providing a second ODT resistance value based on a second distance between the target die and the second non-target die, the second ODT resistance value being different from the first ODT resistance value.

Provided is a data transmission circuit that includes first and second drive circuits and an operation state control circuit. The first drive circuit drives first data that transitions or does not transition in synchronization with a clock signal. The second drive circuit drives second data that transitions at a timing when the first data does not transition in synchronization with the clock signal. The operation state control circuit individually controls operation states of the first and second drive circuits.

Systems, devices, and methods for managing ZQ calibration in semiconductor devices are provided. In one aspect, a circuit includes a memory configured to provide an offset code and a logic circuit. The logic circuit is configured to receive a ZQ calibration code as a first input and the offset code as a second input, and provide a resistor code as an output based on the ZQ calibration code and the offset code.

An impedance calibration circuit includes a code generation circuit and a code update control circuit. The code generation circuit generates a first impedance code set by performing an impedance adjustment operation within an activated period of a data output enable signal generated in response to a read command. The code update control circuit prevents updating a second impedance code set to the first impedance code set until deactivation of the data output enable signal, wherein the second impedance code set is used in impedance adjustment of a transmitting circuit.