145results about "Input/output impedence modification" patented technology

Systems and methods are provided for trimming RTTs in a memory device. The effective termination resistance (RTT) of the ODT may be adjusted by adjusting one or more driver units having predefined values (e.g., 240 Ω. Because PVT characteristics may impact the driver unit values, resistances of the driver units may be fluctuated away from the predefined values (e.g., 240 Ω. ZQ calibration signals may be used to calibrate the resistances of the driver units to the predefined values (e.g., 240 Ω to trim the RTTs. Separate ZQ calibration signals may be generated for different circuits (e.g., a circuit associated with DQ pad, a circuit associated with CA pad). In addition, two ZQ calibration signals may be generated simultaneously by a ZQ circuit during the same time period.

Systems and methods are provided for performing “smooth RTT transitions” to avoid unintended fluctuations in termination resistance (RTT) values (e.g., unexpected values during skewing). RTT control signals (e.g., RTT_PARK, RTT_WR, RTT_NOM_WR, RTT_NOM_RD) are converted from binary codes to unary codes, and resistance drivers are enabled / disabled based on the unary codes to provide corresponding termination resistance of the RTT control signals. There is no unintended value that occurs during the transitioning of the termination resistance from one value to another value. Accordingly, noises on the transmission line (e.g., connecting the memory device to a host device) caused by unintended fluctuations are reduced / avoided.

An impedance calibration circuit includes a code generation circuit and a code update control circuit. The code generation circuit generates a first impedance code set by performing an impedance adjustment operation within an activated period of a data output enable signal generated in response to a read command. The code update control circuit prevents updating a second impedance code set to the first impedance code set until deactivation of the data output enable signal, wherein the second impedance code set is used in impedance adjustment of a transmitting circuit.

Apparatuses and methods for calibrating adjustable impedances of a semiconductor device are disclosed in the present application. An example apparatus includes a register configured to store impedance calibration information and further includes programmable termination resistances having a programmable impedance. The example apparatus further includes an impedance calibration circuit configured to perform a calibration operation to determine calibration parameters for setting the programmable impedance of the programmable termination resistances. The impedance calibration circuit is further configured to program the impedance calibration information in the register related to the calibration operation.

A transmission circuit includes a plurality of driving units coupled with an input / output pad. The transmission circuit performs a data transmission operation by selecting at least one main driving unit corresponding to a predetermined driving strength from among the plurality of driving units and performs an equalization operation by selecting at least one auxiliary driving unit from among remaining driving units excluding the main driving unit.

Apparatuses and methods for identifying memory devices of a semiconductor device sharing an external resistance are disclosed. A memory device of a semiconductor device may be set in an identification mode and provide an identification request to other memory devices that are coupled to a common communication channel. The memory devices that are coupled to the common communication channel may share an external resistance, for example, for calibration of respective programmable termination components of the memory devices. The memory devices that receive the identification request set a respective identification flag which can be read to determine which memory devices share an external resistance with the memory device having the set identification mode.

A component having a bus termination. A component (3, 4, 7-9, 13, 27) for a combustion appliance, such as an appliance having a boiler, the component (3, 4, 7-9, 13, 27) comprising an outer surface and a tangible electrical interface (30, 32, 35, 36) configured to be electrically connected by a user such that the tangible electrical interface (30, 32, 35, 36) is in a short circuit condition, the tangible electrical interface (30, 32, 35, 36) is electrically disconnected by the user such that the tangible electrical interface (30, 32, 35, 36) is in an open condition; wherein the tangible electrical interface (30, 32, 35, 36) is arranged on an outer surface of the component (3, 4, 7-9, 13, 27) such that the tangible electrical interface (30, 32, 35, 36) is accessible to the user; the components (3, 4, 7-9, 13, 27) comprise a first and a second bus wire.

An example method includes for a first calibration impedance, determining a first pulldown calibration code to set a replica pulldown driver circuit to a first impedance. A first pullup calibration code is determined for a replica pullup driver circuit based on the first impedance. The first pulldown and pullup calibration codes are stored. For a second calibration impedance, a second pulldown calibration code is determined to set the replica pulldown driver circuit to a second impedance. A second pullup calibration code is determined for the replica pullup driver circuit based on the second impedance. The second pulldown and pullup calibration codes are stored. The first and second calibration impedances may be on-die calibration impedances. The first and second calibration impedances may be external calibration impedances. The first and second calibration impedances may be provided by a calibration impedance having an adjustable impedance.

The invention provides a self-adaptive adjustment method and system for the resistance value of a controllable digital resistor and a storage medium, and the method comprises the steps: determining first resistance information according to obtained first voltage information; whether the resistance value of the controllable digital resistor needs to be adjusted is judged according to the difference value between the first resistor information and the target resistor information; when the resistance value needs to be adjusted, decomposing the first resistance information through a preset decomposition rule to obtain second resistance information and third resistance information; the resistor series connection condition of the first resistor is adjusted according to the second resistor information, and the resistor series connection condition of the second resistor is adjusted according to the third resistor information, so that the effect of detecting and adjusting the resistance value of the controllable digital resistor in real time is achieved.

In an integrated circuit component having a command interface to receive commands, a data interface to receive write data during a write-data reception interval, and first and second registers, control circuitry within the integrated circuit component responds to one or more of the commands by storing within the first register and the second register, respectively, a first control value that specifies a first termination to be applied to the data interface during the write-data reception interval, and a second control value that specifies a second termination to be applied to the data interface after the write-data reception interval transpires.

Component with bus termination. A component (3, 4, 7-9, 13, 27) for a combustion appliance such as an appliance having a boiler, the component (3, 4, 7-9, 13, 27) comprising an outer surface and a tangible, electric interface (30, 32, 35, 36) configured to be electrically connected by a user such that the tangible, electric interface (30, 32, 35, 36) is in a short circuit condition and configured to be electrically disconnected by the user such that the tangible, electric interface (30, 32, 35, 36) is open circuit condition; wherein the tangible, electric interface (30, 32, 35, 36) is arranged on the outer surface of the component (3, 4, 7-9, 13, 27) such that the tangible, electric interface (30, 32, 35, 36) is accessible to the user; the component (3, 4, 7-9, 13, 27) comprising first and second bus wires.

An impedance calibration circuit includes a variable impedance circuit, a detection circuit and a control circuit. The variable impedance circuit includes conduction paths connected in parallel between an output terminal and a supply terminal coupled to a first supply voltage. The variable impedance circuit is configured to adjust an impedance at the output terminal by enabling one or more of the conduction paths according to a calibration code. The detection circuit is configured to detect a change in impedance of the conduction paths by applying a second supply voltage to a reference terminal through a detection path, and accordingly generate an input voltage at the reference terminal. An electric potential of the second supply voltage is equal to an electric potential of the first supply voltage. The control circuit is configured to compare the input voltage with reference voltages to generate the calibration code.

Local on-die termination controllers for effecting termination of a high-speed signaling links simultaneously engage on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and / or within the same integrated-circuit package, and coupled to the high-speed signaling link. A termination control bus is coupled to memory devices on a module, and provides for peer-to-peer communication of termination control signals.

A memory controller may include an interface, and an input / output driving circuit. The interface may be configured to transfer data between a host and a memory device. The input / output driving circuit may include a pull-down driver connected between a pad and a ground node, and a gate control logic connected between a pad voltage terminal and a first supply voltage terminal. The pull-down driver includes a plurality of NMOS transistors and the gate control logic includes a plurality of PMOS transistors.

This invention provides an integrated circuit trimming method based on trimming code separation, belonging to the field of integrated circuit trimming technology. The method includes: calculating a trimming code based on the initial and target values ​​of the parameter to be trimmed, and establishing a mapping relationship between the trimming code and the trimming parameter; based on the mapping relationship between the trimming code and the trimming parameter, reversing the highest position of the trimming code to obtain the applied trimming code, obtaining the mapping relationship between the applied trimming code and the trimming parameter; and trimming the integrated circuit chip based on the mapping relationship between the applied trimming code and the trimming parameter. This solves the problems of complex code search logic and low trimming efficiency in existing methods based on digital trimming codes.

A transmission circuit comprises a plurality of driver units coupled to an input / output pad. The transmission circuit performs a data transmission operation by selecting at least one main driver unit, corresponding to a predetermined driver strength, from the plurality of driver units, and performs an equalization operation by selecting at least one auxiliary driver unit from the remaining driver units, excluding the main driver unit.

A device for transmitting first data to an external device and receiving second data from the external device is provided. The device includes: a voltage mode driver connected to a first node, the voltage mode driver including a pull-up resistor circuit and a pull-down resistor circuit, the pull-up resistor circuit including a plurality of pull-up resistors, and the pull-down resistor circuit including a plurality of pull-down resistors; a current source circuit connected to a second node and including a first current source and a second current source; a pre-driver configured to control the voltage mode driver and the current source circuit, based on the first data; a receiver connected to the second node and configured to obtain the second data based on a voltage level of the second node; and a hybrid resistor connected between the first node and the second node.

A memory device includes a memory circuit, a redistribution layer, and a resistor circuit. The redistribution layer is coupled to the memory circuit. The resistor circuit is coupled to the memory circuit. The resistor circuit includes a first resistor group and a second resistor group. The first resistor group includes a first resistor and a second resistor. The second resistor group comprises a third resistor and a fourth resistor. After the first resistor and the second resistor are coupled in parallel according to the impedance value of the redistribution layer and the third resistor and the fourth resistor are coupled in parallel according to the impedance value of the redistribution layer, the first resistor group and the second resistor group are coupled in parallel according to the impedance value of the memory circuit. In this way, the signal integrity (SI) of the signal written to the memory device is not affected. In addition, the invention also discloses a method for operating the memory device.

A signal generator circuit is provided. The gate of a first transistor and the drain of a second transistor are coupled to a first output terminal. The sources of the first and second transistors are coupled to a first power terminal. The drains of the first and third transistors, and the gate of the second transistor are coupled to a second output terminal. The gate of the third transistor is coupled to a second power terminal. The source of the third transistor is coupled to a third power terminal. A fourth transistor is coupled to the second power terminal and the first output terminal. When the third transistor is turned off, a first bias circuit turns on the fourth transistor. A second bias circuit provides a first predetermined voltage to the second transistor. A third bias circuit provides a second predetermined voltage to the first transistor.

The present application relates to a calibration circuit and a transmitter including the same. A calibration circuit includes: an oscillator configured to generate an oscillation signal according to a control voltage; a counter configured to generate a count value according to the oscillation signal; and a control circuit configured to control a pull-up driver and a pull-down driver commonly coupled to an output node according to the count value, wherein the control circuit compares a reference count value of the counter by providing a reference voltage as the control voltage for a unit control period with a count value of the counter by providing an output voltage of the output node as the control voltage for the unit control period, and controls a pull-up control signal for adjusting an on-resistance of the pull-up driver and a pull-down control signal for adjusting an on-resistance of the pull-down driver.

A first impedance calibration part configured to perform a first impedance calibration operation of generating a first impedance calibration code set for adjusting an impedance of a first terminating resistor to a first target value, with reference to an external resistor having a first resistance value. A second impedance calibration part configured to perform a second impedance calibration operation of generating a second impedance calibration code set for adjusting an impedance of a second terminating resistor to a second target value, with reference to a reference resistance unit, a resistance value of which is set to a second resistance value according to a part of the first impedance calibration code set.

Apparatuses and methods for calibrating adjustable impedances of a semiconductor device are disclosed in the present application. An example apparatus includes a register configured to store impedance calibration information and further includes programmable termination resistances having a programmable impedance. The example apparatus further includes an impedance calibration circuit configured to perform a calibration operation to determine calibration parameters for setting the programmable impedance of the programmable termination resistances. The impedance calibration circuit is further configured to program the impedance calibration information in the register related to the calibration operation.

High-swing push-pull assisted Voltage Mode Logic (VML) driver circuits can enhance output voltage amplitude to improve efficiency and performance in electronic applications. For example, this is accomplished by utilizing a primary current generator circuit that is powered by a supply voltage to generate a primary current. The primary current is provided, through a switching circuit, to an output node that, in response to an input signal, generates a first output voltage. Further, a supplementary current generator circuit is coupled to the switching circuit to generate a secondary current. The combination of the primary and secondary currents increases the amplitude of the first output voltage, thereby enabling the VML driver circuit to deliver enhanced performance, particularly in applications requiring precise voltage control and high efficiency.

A biased impedance circuit, an impedance adjustment circuit, and an associated signal generator are provided. The biased impedance circuit is coupled to a summation node and applies a biased impedance to the summation node. A periodic input signal is received at the summation node. The biased impedance circuit includes a switching circuit for receiving an output window signal, wherein a period of the output window signal is shorter than a period of the periodic input signal. The switching circuit includes a low impedance path and a high impedance path. The low impedance sets the biased impedance to a first impedance when the output window signal is at a first voltage level. The high impedance path sets the biased impedance to a second impedance when the output window signal is at a second voltage level. The first impedance is less than the second impedance.

A memory module includes a plurality of memory devices. Each of the plurality of memory devices includes a plurality of data input / output pads, a plurality of on-die termination (ODT) circuits each including one or more resistors, a plurality of transceiver circuits each including one or more transmission drivers and one or more reception buffers, and a plurality of equalizer circuits each including one or more inductors. Each of the plurality of equalizer circuits is connected to one of the plurality of data input / output pads, one of the plurality of ODT circuits, and one of the plurality of transceiver circuits. Each of the one or more transmission drivers drives a node of one of the plurality of data input / output pads. Inductances of the one or more inductors have individual values which are based on a driver strength of each of the one or more transmission drivers.

A memory device includes an ODT control circuit which provides an ODT pulse signal responsive to a command. The ODT control circuit compresses an ODT off latency added with a CRC bit based on a value of an ODT on latency. The compressed value of the ODT off latency added with a CRC bit is combined with the ODT on latency to generate a compressed ODT offset value. The duration of the ODT pulse signal is based on the compressed ODT offset value, a burst length, and an ODT pulse width parity. The combination of the compressed ODT offset and burst length is done along circuits of an even path or circuits of an odd path based on when the command was received. However, the compression and the generation of the ODT offset is shared between the even and odd paths.

An interface circuit for reducing input impedance using mirrored current feedback is disclosed herein. The interface circuit includes a current mirror and an input circuit path. The parallel feedback via the return circuit path provides a mirrored current to the interface input, thereby reducing the input impedance of the interface circuit. With parallel feedback, an input impedance of the interface circuit is reduced relative to an impedance of the input circuit path. In this manner, the input impedance of the interface circuit may be reduced without changing the impedance of the input circuit path.

A circuit with calibration function includes a fully differential amplifier circuit, two voltage generation circuits, two multiplexers, a comparator and a digital logic circuit. The fully differential amplifier circuit amplifies a pair of differential input voltages to generate a pair of differential output voltages. One voltage generation circuit utilizes a first current to flow through a capacitor to generate a first voltage. The other voltage generation circuit utilizes a second current to flow through a resistor to generate a second voltage. The multiplexers provide the pair of differential output voltages or the first and second voltages to the comparator according to a digital control signal. The digital logic circuit generates a first digital code to adjust a capacitance of the capacitor or a second digital code to adjust DC voltage levels of the pair of differential output voltages according to the comparison signal provided by the comparator.

A method of configuring an on-die termination circuit in each non-volatile memory die of a plurality of non-volatile memory dice that have one or more pads coupled in common, includes determining, by each of the non-volatile memory dice whether that non-volatile memory die is a target or a non-target for a memory operation; setting, by each of the non-volatile memory die that determines it is a target, a first on-die termination configuration value; setting, by each of the non-volatile memory die that determines it is a non-target, a second on-die termination configuration value; configuring, by each of the target non-volatile memory die, its corresponding on-die termination circuit to provide a first impedance based, at least in part, on the first on-die termination configuration value; and concurrently with the configuring by each target non-volatile memory die, configuring, by each non-target non-volatile memory die, its corresponding on-die termination circuit to provide a second impedance based, at least in part, on the second on-die termination configuration value.

Control logic in a memory device initiates an impedance (ZQ) calibration to be performed by a calibration circuit coupled to an output buffer of an input / output circuit the I / O circuit of the memory device. A first set of calibration units of the calibration circuit includes a first calibration unit and a second calibration unit, where a first calibration code including a first sequence of bit values is generated having at least one bit value of the first sequence generated by a first transistor set of the first calibration unit and a second transistor set of the second calibration unit. The first calibration code is provided to one or more pull-up units of the output buffer, where the first calibration code is used to calibrate a first impedance of the one or more pull-up units. A second calibration code including a second sequence of bit values is generated by a second set of calibration units and a third set of calibration units. The second calibration code is provided to one or more pull-down units of the output buffer to calibrate a second impedance of the one or more pull-down units.