575results about "Impedence matching networks" patented technology

An apparatus for converting power includes at least one impedance matching network which receives an electrical signal. The apparatus includes at least one AC to DC converter in communication with the impedance matching network. Also disclosed is a method for powering a load and an apparatus for converting power and additional embodiments of an apparatus for converting power.

An embodiment of the present invention provides an apparatus, comprising an RF matching network connected to at least one RF input port and at least one RF output port and including one or more voltage or current controlled variable reactive elements and wherein the RF matching network is adapted to maximize RF power transferred from the at least one RF input port to the at least one RF output port by varying the voltage or current to the voltage or current controlled variable reactive elements to maximize the RF voltage at the at least one RF output port. The variable reactive elements may be variable capacitances, variable inductances, or both.

A balanced high-frequency device is constituted by a balanced device and a phase circuit. The input side of the balanced device is connected to an input terminal IN serving as an unbalanced input / output terminal and the output side of it is connected to output terminals OUT1 and OUT2 serving as balanced input / output terminals. Moreover, the phase circuit is connected between the output terminals.

Disclosed is a programmable impedance control circuit, comprising a voltage divider, the voltage divider comprising an MOS array supplied with a first voltage and an external resistance having an external impedance equal to N times said external resistance. The voltage divider outputs a second voltage. A reference voltage generator is provided for generating a third voltage corresponding to N / (N+M) times said first voltage as a reference voltage for said second voltage, and wherein M times internal impedance is used for N times external impedance (N=M or N<> M).

A method and apparatus for use in a digitally tuning a capacitor in an integrated circuit device is described. A Digitally Tuned Capacitor DTC is described which facilitates digitally controlling capacitance applied between a first and second terminal. In some embodiments, the first terminal comprises an RF+ terminal and the second terminal comprises an RF− terminal. In accordance with some embodiments, the DTCs comprise a plurality of sub-circuits ordered in significance from least significant bit (LSB) to most significant bit (MSB) sub-circuits, wherein the plurality of significant bit sub-circuits are coupled together in parallel, and wherein each sub-circuit has a first node coupled to the first RF terminal, and a second node coupled to the second RF terminal. The DTCs further include an input means for receiving a digital control word, wherein the digital control word comprises bits that are similarly ordered in significance from an LSB to an MSB.

A plurality of sets of circuits are provided, each of which generates an impedance code through the use of an impedance control circuit in association with a resistive element connected to an external terminal, and each of which varies the impedance in accordance with such an impedance code. The impedance control circuit includes an impedance comparator which is formed equivalently to the resistive element and the plurality of sets of circuits, and which performs an impedance comparison with each of a plurality of replica circuits to form an up signal that increases the impedance and a down signal that decreases the impedance. Counters are provided adjacent to the individuals of the plurality of sets of circuits to thereby generate the impedance codes in response to the up signal and the down signal.

This disclosure describes systems, methods, and apparatuses for impedance-matching radio frequency power transmitted from a radio frequency generator to a plasma load in a semiconductor processing chamber. Impedance-matching can be performed via a match network having a variable-reactance circuit. The variable-reactance circuit can comprise one or more reactive elements all connected to a first terminal and selectively shorted to a second terminal via a switch. The switch can comprise a bipolar junction transistor (BJT) or insulated gate bipolar transistor (IGBT) controlled via bias circuitry. In an on-state, the BJT base-emitter junction is forward biased, and AC is conducted between a collector terminal and a base terminal. Thus, AC passes through the BJT primarily from collector to base rather than from collector to emitter. Furthermore, the classic match network topology used with vacuum variable capacitors can be modified such that voltages do not overload the BJT's in the modified topology.

To decrease the circuit scale necessary for the calibration of the output circuit and to decrease the time required for the calibration operation. The invention includes a first output buffer and a second output buffer that are connected to a data pin, and a calibration circuit that is connected to a calibration pin. The first output buffer and the second output buffer include plural unit buffers. The unit buffers have mutually the same circuit structures. With this arrangement, the impedances of the first output buffer and the second output buffer can be set in common, based on the calibration operation using the calibration circuit. Consequently, both the circuit scale necessary for the calibration operation and the time required for the calibration operation can be decreased.

To decrease the circuit scale necessary for the calibration of the output circuit and to decrease the time required for the calibration operation. The invention includes a first output buffer and a second output buffer that are connected to a data pin, and a calibration circuit that is connected to a calibration pin. The first output buffer and the second output buffer include plural unit buffers. The unit buffers have mutually the same circuit structures. With this arrangement, the impedances of the first output buffer and the second output buffer can be set in common, based on the calibration operation using the calibration circuit. Consequently, both the circuit scale necessary for the calibration operation and the time required for the calibration operation can be decreased.

A system that incorporates teachings of the present disclosure may include, for example, a matching network including a tunable reactance circuit configured to be coupled to at least one of a transmitter portion and a receiver portion of a communication device, where the tunable reactance circuit is adjustable to a plurality of tuning states, and where the determination of a tuning state is based on whether detected signal measurements are determined to be invalid and is based on information from at least one of an open-loop or closed-loop feedback configuration of the tunable reactance circuit. Additional embodiments are disclosed.

An apparatus for detecting an operating characteristic mismatch at an output of an amplifier by using a replica circuit is presented. In one exemplary case, a detected voltage difference at the output of the two circuits is used to drive a tuning control loop to minimize an impedance mismatch at the output of the amplifier. In another exemplary case, the replica circuit is used to detect a fault in operation in a corresponding main circuit. A method for detecting a load mismatch in a main RF circuit using the replica circuit is also presented.

In one embodiment, the present disclosure is directed to a method for matching an impedance. The method can include determining or receiving a reflection parameter value at an RF input or output; stopping the altering of a first capacitance and a second capacitance when the reflection parameter value is at or below a first reflection value; causing a limited altering of the first capacitance and the second capacitance to pursue an impedance match when the reflection parameter value is at or above a second reflection value and at or below the third reflection value; and causing an unlimited altering of the first capacitance and the second capacitance to pursue an impedance match when the reflection parameter value is at or above a third reflection value.

A matching circuit includes a demultiplexer for demultiplexing a signal outputted from an amplification device into signals of respective frequency bands, and at least two matching blocks which are connected to the demultiplexer, are respectively fed with the signals of the respective frequency bands, and perform impedance matching in the respective frequency bands of the inputted signals. Impedance matching is performed on each of the demultiplexed signals of the respective frequency bands, thereby achieving a matching circuit capable of efficiently performing impedance matching in the respective frequency bands. With this matching circuit, it is possible to achieve a multi-band amplifier capable of simultaneously amplifying signals of multiple frequency bands with high efficiency and low noise.