456 results about "High capacitance" patented technology

The utility model discloses a silicon capacitor electrode structure and a silicon capacitor, which can further improve the capacitance of a capacitor in a limited space by nesting, combining and arranging a plurality of groups of element arrays distributed in a triangular grid mode more reasonably and precisely, so that the capacitor can store more charges.

The invention relates to the technical field of injection molding processes, in particular to an injection molding process for an ultrathin capacitor shell, which comprises the following steps: premixing ABS (Acrylonitrile Butadiene Styrene), polycarbonate and a reinforcing aid, and carrying out melt blending granulation on the obtained premix to obtain reinforced particles; the multi-cavity mold is preheated in advance; and the reinforced particles are fed into a screw extruder to be molten, then the molten reinforced particles are injected into a preheated multi-cavity mold, pressure maintaining treatment is carried out, then cooling and demolding are carried out, and the capacitor shell is obtained. The MBS and the modified glass fiber are added into the ABS / polycarbonate composite material to prepare the reinforced particles, so that the mechanical property of a product prepared from the reinforced particles is greatly improved, the product has good rigidity and toughness, and the tensile strength, bending strength and impact strength of the capacitor shell can be improved when the product is applied to the capacitor shell, and the service life of the capacitor shell is prolonged. Therefore, the shell of the capacitor can be made thinner on the premise of ensuring the quality, and the miniaturization of the capacitor is facilitated.

The invention discloses a semiconductor structure forming method and a semiconductor structure. The method comprises the steps of providing a substrate; forming a shallow trench isolation structure connected with the buried oxide layer in the top layer silicon, wherein the shallow trench isolation structure is provided with a capacitor region; forming a first interlayer dielectric layer on the substrate; at least two adjacent and mutually independent capacitor openings and a plurality of first conductive openings are formed, the projection of each capacitor opening on the surface of the shallow trench isolation structure is located in the capacitor area, and the projection of each first conductive opening on the surface of the shallow trench isolation structure is located outside the capacitor area; the capacitor opening and the first conductive opening penetrate through the first interlayer dielectric layer, the shallow trench isolation structure and the buried oxide layer; a capacitor conductive structure is formed in each capacitor opening, a first conductive structure is formed in the first conductive opening, and the capacitor conductive structures form MOM capacitors with adjacent positive and negative plates. According to the invention, high integration level is considered while large capacitance is provided.

A touch panel, display screen, and electronic device are disclosed. The touch panel includes a touch area and a wiring area. The touch area has a plurality of touch channels arranged at intervals and extending along a first direction, including adjacent first touch channels and second touch channels. Each first touch channel includes a first electrode, and each second touch channel includes a second electrode. The wiring area has a first end wiring and a second end wiring of the first electrode, and a first end wiring of the second electrode. The projection of the first end wiring of the second electrode in the first direction does not overlap with the projection of the first end wiring of the first electrode in the first direction, but overlaps with the projection of the second end wiring of the first electrode in the first direction. The projection of the second end wiring of the first electrode on the first end wiring of the second electrode overlaps with the first end wiring of the second electrode. Using this application can improve the accuracy of capacitive writing pen strokes.

The invention discloses a composite switch for reactive compensation capacitor bank switching and a control method thereof, and relates to the technical field of capacitor switching, and the method comprises the steps: detecting the capacity and switching data of each branch in a back-to-back capacitor bank through a reactive compensation controller, and determining a group capacitor to be subjected to switching operation according to a preset switching control condition; the reactive compensation controller determines the switching time sequence of each phase of each group capacitor according to the confirmed input / output operation instruction to be executed and the reference voltage of each group capacitor; and calculating the reactive state and the switching state of the switched power system through the reactive compensation controller. Compared with a conventional switching control method, the automatic phase selection switching control method has the advantages that closing inrush current and overvoltage are lower, the accuracy of phase control switching of the capacitor bank can be improved, high-frequency inrush current and pre-breakdown arcing phenomena can be reduced, meanwhile, the probability of rebreakdown can be reduced, and the service life of the capacitor bank can be prolonged. And the performance of the composite switch switched capacitor bank is improved.

The utility model discloses a silicon capacitor electrode structure and a silicon capacitor, which can further improve the capacitance of a capacitor in a limited space by nesting, combining and arranging a plurality of groups of element arrays distributed in a quadrilateral grid mode more reasonably and precisely, so that the capacitor can store more charges.

The invention discloses a capacitor implosion risk analysis method and system based on time sequence characteristics, and relates to the technical field of risk analysis, and the method comprises the steps: collecting the current, temperature and equivalent series resistance data in the operation process of a capacitor, and constructing an operation parameter time sequence data set; first-order instant change features are extracted in each time window, and second-order time sequence features are obtained based on continuous window analysis; identifying abnormal change features and counting occurrence times, duration and multi-parameter joint modes to form an enhanced implosion risk representation vector; and classifying each time window based on implosion risk characteristics, judging implosion risks to be low, medium and high levels, and generating a detailed risk early warning sequence and corresponding processing suggestions. According to the method, multi-parameter and multi-time-dimension continuous risk analysis and graded early warning can be realized, the operation safety of the capacitor is effectively improved, implosion accidents are prevented, and the overall risk management and control efficiency is improved.

The application discloses a preparation method of a high-density and high-stability conductive polymer film based on electrochemical polymerization, and comprises the following steps: using an oxidant solution and a BFDO monomer solution to pretreat a formed foil to obtain a working electrode, then immersing the working electrode and a reference electrode into an electrolyte to perform electrochemical oxidation polymerization, and obtaining the high-density and high-stability conductive polymer film based on electrochemical polymerization. The pretreated formed foil containing N-type conductive polymer PBFDO is prepared by using a chemical in-situ polymerization method on the formed foil, and when the pretreated formed foil is applied in the field of capacitors, the conductivity and electron transport capacity of the capacitor can be improved, and the stability problem caused by the coupling of positive and negative charges in the traditional capacitor is greatly improved.

A method for manufacturing a multi-layer ceramic capacitor (MLCC) end electrode and printing a full-area inner electrode protective layer is disclosed. The method uses thin dielectric ceramic layer thickness and a plurality of nickel inner electrode stacks to achieve high capacitance. The method produces high-density electrode-to-ceramic ratio end edges and side edges. The method uses an ultralow-temperature electrochemical deposition coating technology to manufacture a low-stress multi-layer ceramic capacitor end electrode and an insulating protective layer, thereby improving the yield of the multi-layer ceramic capacitor and reducing manufacturing costs.

The invention belongs to the field of semiconductors, and discloses a novel ferroelectric memcapacitor based on an MFIS structure and a preparation method thereof, a substrate of the novel ferroelectric memcapacitor comprises a first doped region and a second doped region, and the doping type of the first doped region is p-type; the insulating layer, the ferroelectric layer and the top electrode layer are arranged on the substrate from bottom to top and cover the first doped region of the substrate; an uncovered area on the surface of the substrate is a second doped area, and the doping type of the second doped area is n type; the bottom electrode layer is located in the second doped region of the substrate and is far away from the first doped region; the channel is located in the second doped region of the substrate and is close to the first doped region; the invention also provides a corresponding preparation method, according to the ferroelectric memcapacitor prepared by using the method, because the semiconductor layer has a PN junction depletion region, the ferroelectric film can be fully overturned by using a band-to-band tunneling mechanism without large voltage, and meanwhile, the capacitance of the depletion region of the PN junction on one side of the semiconductor is adjusted, so that a relatively high capacitance-to-switch ratio is obtained while low power consumption is ensured.

The invention relates to a glue pouring positioning tool for a capacitor, which comprises a positioning frame, more than one positioning block and at least two locking strips, and is characterized in that the positioning frame is sleeved outside a shell of the capacitor and is positioned at the upper part of the shell; the locking bar is used for fixing the positioning frame on the upper part of the shell; the two end parts of the positioning block are connected with the upper end of the positioning frame, and the middle part of the positioning block is locked with a connecting terminal of a core group of the capacitor. According to the invention, the glue filling positioning tool is applied to the preparation process of the capacitor, so that the upper cover of the capacitor can be welded after glue filling is completed, the glue filling liquid level height and the glue curing effect can be confirmed in the glue filling process of the capacitor, and the glue filling liquid level height and the glue curing effect can meet the requirements; therefore, the yield of the capacitor is improved.

The invention discloses a flexible capacitive pressure sensor and a preparation method, and relates to the technical field of flexible capacitive pressure sensors.The flexible capacitive pressure sensor comprises a shell, a second binding post arranged at one end of the shell, a shell cover arranged at the other end of the shell and a first binding post arranged on the shell cover, an upper packaging layer is arranged in the shell, an upper electrode layer is arranged on one side of the upper packaging layer, and a lower electrode layer is arranged on the other side of the upper packaging layer; a middle dielectric layer is arranged on one side of the upper electrode layer, a lower electrode layer is arranged on one side of the middle dielectric layer, and a lower packaging layer is arranged on one side of the lower electrode layer; conductive film structures are arranged between the lower electrode layer and the middle dielectric layer and between the upper electrode layer and the middle dielectric layer; a sealing assembly is arranged in the shell cover; an extrusion assembly is further arranged in the shell cover; by using the sealing assembly, the sealing performance between the shell and the shell cover is improved, external moisture and dust are prevented from entering the shell, the accuracy of capacitance measurement is improved, and the service life of the flexible capacitive pressure sensor is further prolonged.

The disclosure provides a semiconductor structure defect monitoring method and device, and relates to the technical field of semiconductors. The semiconductor structure defect monitoring method comprises the following steps: acquiring a overlay accuracy offset of a capacitor column and a support structure; acquiring an etching opening size of an etching film layer; determining a corresponding relationship between the overlay accuracy offset and the etching opening size; and monitoring a structure defect in a semiconductor production process based on the corresponding relationship. The technical problem of poor defect monitoring effect of the capacitor is solved, and the technical effect of improving the defect monitoring effect of the capacitor is achieved.

This invention provides a multilayer ceramic capacitor with improved internal electrode connectivity, high capacitance, and excellent reliability, as well as a method for manufacturing the same. [Solution] A multilayer ceramic capacitor according to one embodiment includes a capacitor body comprising a dielectric layer and an internal electrode layer, and an external electrode disposed on the outside of the capacitor body, wherein the internal electrode layer comprises nickel (Ni), aluminum (Al), and silicon (Si), and the Al / Si weight ratio is 0.01 to 1.

The invention relates to a capacitance detection circuit, device and method, a first power supply circuit and a second power supply circuit respectively provide the same voltage for a counting oscillation circuit and a detection oscillation circuit, so that the counting oscillation circuit and the detection oscillation circuit work in the same power supply environment, and capacitance detection is realized. By configuring the power supply circuit in the capacitance detection circuit for power supply, the interference of the environmental space on the power supply can be effectively reduced. Meanwhile, the counting oscillation circuit and the detection oscillation circuit are respectively provided with a power supply circuit, crosstalk between a counting channel and a detection channel can be avoided, and capacitance detection can be accurately achieved when the frequency of the detection oscillation circuit is close to the integral multiple frequency of the counting oscillation circuit. Therefore, the anti-interference capability of the capacitance detection circuit can be improved, and the problem that the detection sensitivity is reduced due to interference is solved.

This invention relates to the field of CMOS integrated circuit manufacturing processes and discloses a method for fabricating a PIP capacitor. First, the WSi of the lower electrode of the PIP capacitor is reduced by implantation. x Thin film stress is reduced, and then parasitic SiO2 on the surface of the lower electrode of the PIP capacitor is reduced by dry etching. WSi on the lower electrode is reduced by implantation. x Thin-film stress can improve the reliability of PIP capacitors; the principle for selecting the injection energy is to maximize the depth (R0) of the injection Gaussian distribution. p +3ΔR p ) to reach the entire WSi x 80% of the film thickness; WSi after implantation x The stress in the thin film was reduced by an order of magnitude by selecting phosphorus to eliminate WSi. x Thin film stress is a concern because phosphorus is frequently used for N-type polycrystalline doping. Simultaneously, phosphorus implantation also increases the polycrystalline doping concentration and reduces polycrystalline depletion.

The invention relates to a capacitor formed foil capacity detection method and device, computer equipment, a computer readable storage medium and a computer program product. The method comprises the following steps: acquiring the thickness information of an oxidation film generated in the production process of the capacitor formed foil; detecting hole microcosmic parameter information of formation holes in the capacitor formed foil according to the thickness information of the oxide film and the corrosion foil hole radius information of the capacitor formed foil; and detecting the capacity of the capacitor formed foil according to the oxide film thickness information and the hole microscopic parameter information. By adopting the method, the capacitor capacity detection accuracy can be improved.

The invention provides a method and a system for improving the partial discharge measurement sensitivity of a capacitor power-taking device, and the method comprises the steps: a measurement impedance coupling capacitor and a measurement impedance are connected in series and then are connected with a measured capacitor power-taking device in parallel, and pulse current generated by the partial discharge of the measured capacitor power-taking device enters a detection loop through the coupling capacitor; applying a pre-applied voltage to the tested capacitor power-taking device, wherein the duration time is a first preset time; reducing the voltage to the measurement voltage of partial discharge, and measuring the first open-circuit and short-circuit partial discharge capacity of the secondary end of the measured capacitor power taking device under open circuit and short circuit through the detection loop; reducing the voltage to a second preset measurement voltage, and measuring second open-circuit and short-circuit partial discharge amounts of the measured capacitor power taking device at the secondary end under open circuit and short circuit through the detection loop; and based on the first open circuit and short circuit partial discharge capacity and the second open circuit and short circuit partial discharge capacity, determining the partial discharge capacity of the capacitor power taking device. And the sensitivity and the accuracy of partial discharge measurement are improved.

The present invention provides a method and a device structure for forming a device structure that eliminates the need for additional masks, thereby reducing production costs and process complexity, while ensuring improved performance and scalability of the memory array and peripheral circuits. [Solution] An efficient method for simultaneously forming a memory node capacitor 60 and a voltage stabilization capacitor 160 in a semiconductor structure including a memory array region 100 and a peripheral device region 200, wherein these capacitors are integrated within a lower-level dielectric material layer 760 and a lower-level metal wiring structure 780, and high capacitance is achieved with a minimal device footprint by utilizing a dielectric capping layer 10 having memory region openings and peripheral region openings.

The present disclosure provides an integrated circuit device in which a capacitor is connected between two vias through a passivation stack to couple a power supply contact to a metal interconnect structure. By providing enough high capacitance and enough low equivalent series resistance for the capacitor, the noise in the power supply can be effectively filtered. The capacitor may have a trench capacitance structure as part of a solution for providing sufficiently high capacitance. Placing all or part of the capacitor within the passivation stack allows the capacitor to be implemented without moving the wiring or device in the metal interconnect structure.

This invention provides a solid electrolytic capacitor that can achieve high capacitance. [Solution] The solid electrolytic capacitor comprises a capacitor element containing a conductive polymer. The capacitor element comprises an anode, a first dielectric layer containing a first dielectric (excluding a composite oxide of titanium and aluminum) covering at least a portion of the surface of the anode, a second dielectric layer containing a second dielectric covering at least a portion of the surface of the first dielectric layer, and the conductive polymer covering at least a portion of the surface of the second dielectric layer. The second dielectric is an oxide containing at least one element selected from the group consisting of silicon, aluminum, and zinc. The dielectric constant D1 of the first dielectric is higher than the dielectric constant D2 of the second dielectric. The thickness T2 of the second dielectric layer is 0.003T1 or more and 0.170T1 or less with respect to the thickness T1 of the first dielectric layer.

The invention discloses a processing method for improving the compaction density of capacitor carbon and the volume specific capacity of an electrode material, and the method comprises the steps: carrying out the grinding and shaping of an activated and pore-formed capacitor carbon raw material, and obtaining the spherical capacitor carbon powder; carrying out washing and roasting pretreatment on the sphere-like capacitance carbon powder to obtain pretreated capacitance carbon; mixing the pretreated capacitor carbon to obtain uniform mixed capacitor carbon powder; and calcining the mixed capacitor carbon powder for 0.5-2 hours at the temperature of 500-900 DEG C in a protective gas atmosphere to finally obtain a capacitor carbon finished product with improved compaction density and volume specific capacity. By accurately controlling particle size distribution and proportion of raw materials and combining a shaping process and a heat treatment process, accumulation gaps among capacitor carbon particles are reduced, and the compaction density is improved; the optimized particle morphology enhances the fluidity of the material and the forming strength of the electrode, so that the volume specific capacity of the electrode material is obviously improved.

The utility model relates to the technical field of capacitor cabinets, in particular to a capacitor cabinet with a cooling air duct structure, which comprises a cabinet body, the cabinet body comprises a main frame, a front door plate assembly and a rear door plate assembly, a cooling fan is arranged in the middle of the rear door plate assembly, and a first ventilation fence is arranged at the top of the rear door plate assembly. A second ventilation fence is arranged at the bottom of the rear door plate assembly, the front door plate assembly comprises a plurality of heat dissipation areas, and a plurality of first heat dissipation holes which are tightly arranged are formed in the heat dissipation areas. The heat dissipation fan, the first ventilation fence, the second ventilation fence and the first heat dissipation holes form an air flowing system; in addition, the first ventilation fence and the second ventilation fence are oppositely arranged at the upper end and the lower end of the heat dissipation fan, the first heat dissipation holes are located between the first ventilation fence and the second ventilation fence, through the structure, the exchange efficiency of air in the cabinet body and external air is improved, and then the heat dissipation efficiency of the capacitor cabinet is improved.

The invention provides a capacitive vacuum gauge and a semiconductor device, and the capacitive vacuum gauge comprises a detection cavity, one side of which is provided with a through hole; the first end of the air inlet pipe is communicated with the through hole, and the second end of the air inlet pipe is communicated with a cavity to be measured; and the insulating pipe is connected to any position of the air inlet pipe, so that the detection cavity is grounded without passing through the air inlet pipe. According to the capacitive vacuum gauge and the semiconductor equipment provided by the embodiment of the invention, the detection cavity is not electrically connected with the outside through the air inlet pipe by virtue of the insulating pipe, so that the precision of a capacitance acquisition circuit is improved, and the precision of air pressure measurement is improved.

The present application relates to a capacitive pressure sensor and a manufacturing method therefor. The capacitive pressure sensor comprises: a substrate; a variable capacitor located on the substrate; and a reference capacitor located on the substrate on one side of the variable capacitor. The variable capacitor and the reference capacitor both comprise a bottom electrode, a top electrode, and a capacitor dielectric located between the bottom electrode and the top electrode. The capacitor dielectric of the variable capacitor comprises an air cavity, and the capacitor dielectric of the reference capacitor comprises a dielectric layer provided with an air groove. The capacitive pressure sensor of the present application comprises the variable capacitor and the reference capacitor at the same time, thereby adding the calibration function, and improving the test precision of the capacitive pressure sensor; the air groove is formed in the dielectric layer of the reference capacitor, so that the capacitance of the reference capacitor can be adjusted by changing the size of the air groove, thereby improving the controllability of the reference capacitor; and since the controllability of the reference capacitor is high, by accurately controlling the reference capacitor according to requirements, the test precision of the capacitive pressure sensor can be improved.

The invention discloses processing equipment for capacitor elements, the processing equipment comprises a rack, a plurality of unwinding rollers, winding rollers and an alignment assembly, the unwinding rollers are rotatably arranged on the vertical side wall of the rack in parallel, and the winding rollers are rotatably arranged on the side wall, provided with the unwinding rollers, of the rack; a driving part used for driving the unwinding roller and the winding roller to rotate is arranged on the rack, the alignment assembly is arranged on the rack and comprises an alignment plate and a guide rod, the alignment plate is vertically arranged on the side, provided with the unwinding roller, of the rack in parallel, and a plurality of first communicating openings are formed in the alignment plate; the multiple first communicating ports and the multiple unwinding rollers are arranged in a one-to-one correspondence mode, the unwinding rollers are slidably connected with the alignment plate through the first communicating ports, and the guide rod is perpendicularly arranged on the side, close to the rack, of the alignment plate. The method has the effect of improving the processing quality and the processing precision of the capacitor element.

The invention relates to an equipotential core clamping plate for mounting a capacitive voltage transformer, which is applied to the technical field of capacitors and comprises a clamping plate body, a binding belt groove, a binding belt, a brass insert, a fastening screw, a conductor ring, a connecting screw, a concave groove and a buffer ring. The fixing stability of the brass inserts to the binding belt is effectively improved, the fastening operation of the clamping plate body and the binding belt is simple, the binding efficiency of the capacitor core stacking module is effectively improved, and the brass inserts are connected in series through the conductor ring and are enabled to be at the same potential, so that the potential difference between different embedding barrels is reduced, the discharge risk is reduced, and the reliability of the capacitor core stacking module is improved. And the brass insert and the conductor ring are connected in series into a whole, so that the integral pouring manufacturing of the brass insert and the clamping plate body is effectively improved, and the mass production processing of the clamping plate body is facilitated.

Our invention is about synthesis, fabrication, assembly, packaging, testing of asymmetric flexible supercapacitors utilizing bacterial cellulose, conducting polymer, activated carbon, aqueous electrolyte, having state-of-art pseudocapacitive properties; namely, high-power, high energy and high cycle life. The high capacitive performance of these types of supercapacitors is controlled by the chemical, physical, and electrical properties of the materials used for synthesis and fabrication methods for device assembly and packaging as described here-in. Bacterial cellulose is exposed as a high surface area, fibrous nanomaterial used as a source of carbon fiber for the fabrication of high-performance supercapacitor electrodes. The use of pyrolyzed bacterial cellulose, conducting polymer materials, aqueous electrolytes, non-toxic binders such as carboxy methyl cellulose dispersed in water, device fabrication, and packaging techniques produces batch production of flexible supercapacitors with high performance characteristics.

The invention provides a ferroelectric memory and a forming method thereof, a capacitor structure in the ferroelectric memory is in a groove type and is arranged in a matrix, and the capacitor structure at least penetrates through an intermetallic dielectric layer and an interlayer dielectric layer and extends into a shallow groove isolation structure. The groove type capacitor structure is integrated at the rear section, the bottom end of the groove type capacitor structure at least extends into the shallow groove isolation structure, the depth and the surface area of the capacitor are increased through the groove type capacitor structure, a read-write window is further improved, and the groove type capacitor structure is not limited by the number of metal layers at the rear section. And one transistor and a plurality of capacitor structures are adopted, and a groove type capacitor structure matrix is formed above the shallow groove isolation structure, so that the capacitance density and the process uniformity can be improved.

This disclosure relates to a multiphase hybrid converter. A multiphase hybrid DC-DC converter using switching capacitor technology is described. The multiphase hybrid converter can reduce the volt-seconds across the converter's inductors, thereby reducing the inductor size. Furthermore, the multiphase hybrid converter can utilize the inductor as a current source to charge and discharge the flying capacitor, which can reduce the size of the intermediate capacitor and increase the solution density. Since the charging and discharging operations are performed by the inductor, the multiphase hybrid converter can eliminate capacitor-to-capacitor charge transfer. Therefore, the multiphase hybrid converter does not require high capacitance to achieve efficient operation, which further increases the solution density.