316 results about "High capacitance" patented technology

The utility model discloses a silicon capacitor electrode structure and a silicon capacitor, which can further improve the capacitance of a capacitor in a limited space by nesting, combining and arranging a plurality of groups of element arrays distributed in a triangular grid mode more reasonably and precisely, so that the capacitor can store more charges.

The utility model discloses a silicon capacitor electrode structure and a silicon capacitor, which can further improve the capacitance of a capacitor in a limited space by nesting, combining and arranging a plurality of groups of element arrays distributed in a quadrilateral grid mode more reasonably and precisely, so that the capacitor can store more charges.

The invention discloses a capacitor implosion risk analysis method and system based on time sequence characteristics, and relates to the technical field of risk analysis, and the method comprises the steps: collecting the current, temperature and equivalent series resistance data in the operation process of a capacitor, and constructing an operation parameter time sequence data set; first-order instant change features are extracted in each time window, and second-order time sequence features are obtained based on continuous window analysis; identifying abnormal change features and counting occurrence times, duration and multi-parameter joint modes to form an enhanced implosion risk representation vector; and classifying each time window based on implosion risk characteristics, judging implosion risks to be low, medium and high levels, and generating a detailed risk early warning sequence and corresponding processing suggestions. According to the method, multi-parameter and multi-time-dimension continuous risk analysis and graded early warning can be realized, the operation safety of the capacitor is effectively improved, implosion accidents are prevented, and the overall risk management and control efficiency is improved.

A method for manufacturing a multi-layer ceramic capacitor (MLCC) end electrode and printing a full-area inner electrode protective layer is disclosed. The method uses thin dielectric ceramic layer thickness and a plurality of nickel inner electrode stacks to achieve high capacitance. The method produces high-density electrode-to-ceramic ratio end edges and side edges. The method uses an ultralow-temperature electrochemical deposition coating technology to manufacture a low-stress multi-layer ceramic capacitor end electrode and an insulating protective layer, thereby improving the yield of the multi-layer ceramic capacitor and reducing manufacturing costs.

The disclosure provides a semiconductor structure defect monitoring method and device, and relates to the technical field of semiconductors. The semiconductor structure defect monitoring method comprises the following steps: acquiring a overlay accuracy offset of a capacitor column and a support structure; acquiring an etching opening size of an etching film layer; determining a corresponding relationship between the overlay accuracy offset and the etching opening size; and monitoring a structure defect in a semiconductor production process based on the corresponding relationship. The technical problem of poor defect monitoring effect of the capacitor is solved, and the technical effect of improving the defect monitoring effect of the capacitor is achieved.

This invention provides a multilayer ceramic capacitor with improved internal electrode connectivity, high capacitance, and excellent reliability, as well as a method for manufacturing the same. [Solution] A multilayer ceramic capacitor according to one embodiment includes a capacitor body comprising a dielectric layer and an internal electrode layer, and an external electrode disposed on the outside of the capacitor body, wherein the internal electrode layer comprises nickel (Ni), aluminum (Al), and silicon (Si), and the Al / Si weight ratio is 0.01 to 1.

This invention relates to the field of CMOS integrated circuit manufacturing processes and discloses a method for fabricating a PIP capacitor. First, the WSi of the lower electrode of the PIP capacitor is reduced by implantation. x Thin film stress is reduced, and then parasitic SiO2 on the surface of the lower electrode of the PIP capacitor is reduced by dry etching. WSi on the lower electrode is reduced by implantation. x Thin-film stress can improve the reliability of PIP capacitors; the principle for selecting the injection energy is to maximize the depth (R0) of the injection Gaussian distribution. p +3ΔR p ) to reach the entire WSi x 80% of the film thickness; WSi after implantation x The stress in the thin film was reduced by an order of magnitude by selecting phosphorus to eliminate WSi. x Thin film stress is a concern because phosphorus is frequently used for N-type polycrystalline doping. Simultaneously, phosphorus implantation also increases the polycrystalline doping concentration and reduces polycrystalline depletion.

The invention provides a method and a system for improving the partial discharge measurement sensitivity of a capacitor power-taking device, and the method comprises the steps: a measurement impedance coupling capacitor and a measurement impedance are connected in series and then are connected with a measured capacitor power-taking device in parallel, and pulse current generated by the partial discharge of the measured capacitor power-taking device enters a detection loop through the coupling capacitor; applying a pre-applied voltage to the tested capacitor power-taking device, wherein the duration time is a first preset time; reducing the voltage to the measurement voltage of partial discharge, and measuring the first open-circuit and short-circuit partial discharge capacity of the secondary end of the measured capacitor power taking device under open circuit and short circuit through the detection loop; reducing the voltage to a second preset measurement voltage, and measuring second open-circuit and short-circuit partial discharge amounts of the measured capacitor power taking device at the secondary end under open circuit and short circuit through the detection loop; and based on the first open circuit and short circuit partial discharge capacity and the second open circuit and short circuit partial discharge capacity, determining the partial discharge capacity of the capacitor power taking device. And the sensitivity and the accuracy of partial discharge measurement are improved.

The present invention provides a method and a device structure for forming a device structure that eliminates the need for additional masks, thereby reducing production costs and process complexity, while ensuring improved performance and scalability of the memory array and peripheral circuits. [Solution] An efficient method for simultaneously forming a memory node capacitor 60 and a voltage stabilization capacitor 160 in a semiconductor structure including a memory array region 100 and a peripheral device region 200, wherein these capacitors are integrated within a lower-level dielectric material layer 760 and a lower-level metal wiring structure 780, and high capacitance is achieved with a minimal device footprint by utilizing a dielectric capping layer 10 having memory region openings and peripheral region openings.

This invention provides a solid electrolytic capacitor that can achieve high capacitance. [Solution] The solid electrolytic capacitor comprises a capacitor element containing a conductive polymer. The capacitor element comprises an anode, a first dielectric layer containing a first dielectric (excluding a composite oxide of titanium and aluminum) covering at least a portion of the surface of the anode, a second dielectric layer containing a second dielectric covering at least a portion of the surface of the first dielectric layer, and the conductive polymer covering at least a portion of the surface of the second dielectric layer. The second dielectric is an oxide containing at least one element selected from the group consisting of silicon, aluminum, and zinc. The dielectric constant D1 of the first dielectric is higher than the dielectric constant D2 of the second dielectric. The thickness T2 of the second dielectric layer is 0.003T1 or more and 0.170T1 or less with respect to the thickness T1 of the first dielectric layer.

The invention discloses a processing method for improving the compaction density of capacitor carbon and the volume specific capacity of an electrode material, and the method comprises the steps: carrying out the grinding and shaping of an activated and pore-formed capacitor carbon raw material, and obtaining the spherical capacitor carbon powder; carrying out washing and roasting pretreatment on the sphere-like capacitance carbon powder to obtain pretreated capacitance carbon; mixing the pretreated capacitor carbon to obtain uniform mixed capacitor carbon powder; and calcining the mixed capacitor carbon powder for 0.5-2 hours at the temperature of 500-900 DEG C in a protective gas atmosphere to finally obtain a capacitor carbon finished product with improved compaction density and volume specific capacity. By accurately controlling particle size distribution and proportion of raw materials and combining a shaping process and a heat treatment process, accumulation gaps among capacitor carbon particles are reduced, and the compaction density is improved; the optimized particle morphology enhances the fluidity of the material and the forming strength of the electrode, so that the volume specific capacity of the electrode material is obviously improved.

The utility model relates to the technical field of capacitor cabinets, in particular to a capacitor cabinet with a cooling air duct structure, which comprises a cabinet body, the cabinet body comprises a main frame, a front door plate assembly and a rear door plate assembly, a cooling fan is arranged in the middle of the rear door plate assembly, and a first ventilation fence is arranged at the top of the rear door plate assembly. A second ventilation fence is arranged at the bottom of the rear door plate assembly, the front door plate assembly comprises a plurality of heat dissipation areas, and a plurality of first heat dissipation holes which are tightly arranged are formed in the heat dissipation areas. The heat dissipation fan, the first ventilation fence, the second ventilation fence and the first heat dissipation holes form an air flowing system; in addition, the first ventilation fence and the second ventilation fence are oppositely arranged at the upper end and the lower end of the heat dissipation fan, the first heat dissipation holes are located between the first ventilation fence and the second ventilation fence, through the structure, the exchange efficiency of air in the cabinet body and external air is improved, and then the heat dissipation efficiency of the capacitor cabinet is improved.

The invention provides a capacitive vacuum gauge and a semiconductor device, and the capacitive vacuum gauge comprises a detection cavity, one side of which is provided with a through hole; the first end of the air inlet pipe is communicated with the through hole, and the second end of the air inlet pipe is communicated with a cavity to be measured; and the insulating pipe is connected to any position of the air inlet pipe, so that the detection cavity is grounded without passing through the air inlet pipe. According to the capacitive vacuum gauge and the semiconductor equipment provided by the embodiment of the invention, the detection cavity is not electrically connected with the outside through the air inlet pipe by virtue of the insulating pipe, so that the precision of a capacitance acquisition circuit is improved, and the precision of air pressure measurement is improved.

The invention discloses processing equipment for capacitor elements, the processing equipment comprises a rack, a plurality of unwinding rollers, winding rollers and an alignment assembly, the unwinding rollers are rotatably arranged on the vertical side wall of the rack in parallel, and the winding rollers are rotatably arranged on the side wall, provided with the unwinding rollers, of the rack; a driving part used for driving the unwinding roller and the winding roller to rotate is arranged on the rack, the alignment assembly is arranged on the rack and comprises an alignment plate and a guide rod, the alignment plate is vertically arranged on the side, provided with the unwinding roller, of the rack in parallel, and a plurality of first communicating openings are formed in the alignment plate; the multiple first communicating ports and the multiple unwinding rollers are arranged in a one-to-one correspondence mode, the unwinding rollers are slidably connected with the alignment plate through the first communicating ports, and the guide rod is perpendicularly arranged on the side, close to the rack, of the alignment plate. The method has the effect of improving the processing quality and the processing precision of the capacitor element.

Our invention is about synthesis, fabrication, assembly, packaging, testing of asymmetric flexible supercapacitors utilizing bacterial cellulose, conducting polymer, activated carbon, aqueous electrolyte, having state-of-art pseudocapacitive properties; namely, high-power, high energy and high cycle life. The high capacitive performance of these types of supercapacitors is controlled by the chemical, physical, and electrical properties of the materials used for synthesis and fabrication methods for device assembly and packaging as described here-in. Bacterial cellulose is exposed as a high surface area, fibrous nanomaterial used as a source of carbon fiber for the fabrication of high-performance supercapacitor electrodes. The use of pyrolyzed bacterial cellulose, conducting polymer materials, aqueous electrolytes, non-toxic binders such as carboxy methyl cellulose dispersed in water, device fabrication, and packaging techniques produces batch production of flexible supercapacitors with high performance characteristics.

The invention provides a ferroelectric memory and a forming method thereof, a capacitor structure in the ferroelectric memory is in a groove type and is arranged in a matrix, and the capacitor structure at least penetrates through an intermetallic dielectric layer and an interlayer dielectric layer and extends into a shallow groove isolation structure. The groove type capacitor structure is integrated at the rear section, the bottom end of the groove type capacitor structure at least extends into the shallow groove isolation structure, the depth and the surface area of the capacitor are increased through the groove type capacitor structure, a read-write window is further improved, and the groove type capacitor structure is not limited by the number of metal layers at the rear section. And one transistor and a plurality of capacitor structures are adopted, and a groove type capacitor structure matrix is formed above the shallow groove isolation structure, so that the capacitance density and the process uniformity can be improved.

This disclosure relates to a multiphase hybrid converter. A multiphase hybrid DC-DC converter using switching capacitor technology is described. The multiphase hybrid converter can reduce the volt-seconds across the converter's inductors, thereby reducing the inductor size. Furthermore, the multiphase hybrid converter can utilize the inductor as a current source to charge and discharge the flying capacitor, which can reduce the size of the intermediate capacitor and increase the solution density. Since the charging and discharging operations are performed by the inductor, the multiphase hybrid converter can eliminate capacitor-to-capacitor charge transfer. Therefore, the multiphase hybrid converter does not require high capacitance to achieve efficient operation, which further increases the solution density.

The utility model relates to the technical field of ceramic capacitors, in particular to a multilayer ceramic capacitor. A plurality of layers of stacked suspension electrodes for resisting deformation are arranged between a plurality of adjacent parallel-plate capacitors, and the capability of resisting the inverse piezoelectric effect of the central area of the capacitor is enhanced through the toughness and the strength of the suspension electrodes, so that the failure probability caused by the inverse piezoelectric effect in the use process of the capacitor is greatly reduced; the suspension electrode is arranged in the middle area in the height direction of the capacitor, so that the anti-deformation capability of the area with the maximum deformation degree can be greatly improved, and the stability of the capacitor in the using process is improved; and the phenomenon that the existing high-voltage and high-capacitance multilayer ceramic capacitor is easy to fail due to the inverse piezoelectric effect in the use process is improved.

The invention discloses a battery monomer and a manufacturing method thereof, a battery device, an energy storage device and a power utilization device. The battery monomer comprises a shell and at least one electrode assembly, the shell comprises a top plate and a bottom plate which are opposite to each other along a first direction, an accommodating cavity is arranged between the top plate and the bottom plate, and the size of the shell along the first direction is within a range of 110-250 mm; the electrode assembly is arranged in the containing cavity and borne on the bottom plate, the electrode assembly comprises at least two stacked pole pieces, each pole piece comprises a current collector and an active substance layer arranged on at least one surface of the current collector, and the surface, opposite to the current collector, of each active substance layer is sunken towards the current collector to form at least one sunken part; the recessed part is arranged at one end of the active material layer close to the top plate. The battery monomer and the manufacturing method thereof, the battery device, the energy storage device and the power utilization device provided by the invention have high capacitance.

The application discloses a kind of based on DC side pre-charging's MMC submodule capacitor monitoring method, the capacitor monitoring method includes the following steps;All submodule capacitors in bridge arm are discharged to zero voltage;Charging is carried out to each submodule in turn;The time constant of RC charging loop is calculated to obtain submodule capacitor capacity value;Distinguish whether each submodule capacitor capacity value is less than threshold value, decide whether the submodule capacitor needs to be replaced, until the pre-charging and capacitor monitoring of all submodules are completed.The application can carry out submodule capacitor monitoring synchronously in the pre-charging link before MMC is put into use, so as to effectively monitor the state of each submodule capacitor and replace the fault capacitor in time.Compared with conventional capacitor monitoring method, the application does not involve additional measurement circuit, sensor and complex control algorithm, avoids heavy calculation burden, and can reduce the influence of measurement error, improve capacitor monitoring precision.

The utility model relates to the technical field of thin-film capacitors, in particular to a high-temperature-resistant thin-film capacitor, which comprises a battery core layer, the battery core layer comprises a thin-film layer and a gold-plated layer, a second packaging layer is arranged on the outer layer of the battery core layer, a shell layer is arranged on the outer side of the second packaging layer, and the gold-plated layer is evaporated on the side wall of the thin-film layer. According to the utility model, the thin film layer and the gold plating layer are redesigned, the contact area of the gold spraying layer and the cell layer is increased, the contact resistance is reduced, the high-frequency loss value is reduced, and the current-carrying capability of the electrode is improved, so that the working current bearing peak value of the capacitor is improved; and through the design of the moisture-proof layer, the second packaging layer and the shell layer, the overall heat-conducting property and the high-temperature-resistant property can be improved, so that the situation that the two ends are burnt and damaged can be reduced.

The utility model belongs to the technical field of capacitor aluminum shells, and discloses an efficient heat dissipation capacitor aluminum shell which comprises a hollow capacitor aluminum shell body, a sealing cover is installed at the lower end of the capacitor aluminum shell body, the sealing cover is made of aluminum materials, a capacitor body is installed in the capacitor aluminum shell body, and the capacitor aluminum shell body is internally provided with a heat dissipation device. The lower end of the capacitor body penetrates through the sealing cover and extends out of the sealing cover, and a heat dissipation device used for dissipating heat of the capacitor body is installed in the capacitor aluminum shell body. The capacitor has the effect of prolonging the service life of the capacitor body.

This invention relates to the field of nickel electrode paste preparation technology, and discloses an ultrafine roller-printed nickel paste for ultra-high capacitance MLCCs and its preparation method. The nickel paste includes nickel powder, Ni3Sn-coated nickel powder, diffusion barrier phase, resin, solvent, dispersant, and rheology modifier. The Ni3Sn-coated nickel powder is obtained by chemical plating, where Sn is bonded to Ni in the form of an intermetallic compound. The diffusion barrier phase is selected from nano-ZrO2 or TiO2 particles. After pre-dispersing each solid component with a portion of the dispersant and solvent, the mixture is ground and dispersed using a gradient grinding process, then mixed with an organic carrier to form a paste. After vacuum degassing and filtration, the nickel paste is obtained. This invention uses Ni3Sn-coated nickel powder to replace elemental Sn powder, inhibiting the formation of a dense SnO2 passivation layer. Combined with the blocking effect of the diffusion barrier phase at the grain boundaries and the protection of the coating layer integrity by the gradient grinding process, this invention solves the problem of long-term reliability degradation of MLCCs caused by Sn storage.

The invention discloses a characteristic parameter identification method and device of a capacitor, equipment and a storage medium. The method comprises the following steps: collecting multi-round charging and discharging data of the capacitor; on the basis of first-round charging and discharging data in the multi-round charging and discharging data, parameter initial values and parameter search intervals of first-round charging and discharging are determined, and parameters are characteristic parameters extracted from the charging and discharging data; and utilizing a genetic algorithm and a Kalman filtering algorithm to perform characteristic parameter inversion based on the parameter initial value and the parameter search interval of the first round of charging and discharging and the multi-round charging and discharging data to obtain the characteristic parameters of the capacitor. According to the method, the Kalman filtering algorithm is utilized, the parameter prior dynamic convergence is realized according to the parameter initial value and the parameter search interval of the first round of charging and discharging, so that the characteristic parameters of the capacitor are identified more quickly and accurately, and the health state of the capacitor is determined based on the characteristic parameters of the capacitor. And the identification efficiency and accuracy of the health condition of the capacitor are improved.

The application provides a silicon-based three-dimensional capacitor and a manufacturing method thereof. The manufacturing method comprises the following steps: preparing a dielectric mask layer on the surface of a silicon substrate, etching a plurality of spaced-apart etching micropores on the dielectric mask layer until the silicon substrate is exposed, etching the plurality of spaced-apart etching micropores by using a deep silicon etching process to form a plurality of spaced-apart first deep holes, removing the remaining dielectric mask layer, preparing a first polysilicon layer on the silicon substrate with the plurality of spaced-apart first deep holes, etching the first polysilicon layer in the first deep holes by using a deep silicon etching process to form second deep holes in the first polysilicon layer in the first deep holes, and the bottom surface and the side surface of the second deep holes are provided with the first polysilicon layer, and growing an insulating dielectric layer, a second polysilicon layer and an electrode layer on the first polysilicon layer on the surface of the first silicon substrate and in all the spaced-apart second deep holes in sequence. The silicon-based three-dimensional capacitor prepared by the application can improve the density of the capacitor.

The application discloses a capacitor and an electric vehicle. The capacitor comprises a capacitor core group, wherein the capacitor core group comprises a plurality of array-arranged capacitor cores; each capacitor core comprises an electrode, and the electrode comprises a first electrode and a second electrode with opposite polarities; each capacitor core comprises oppositely arranged first and second surfaces; the first surface comprises at least two first electrodes; the second surface comprises at least two second electrodes; and the electrodes of the capacitor cores in the same row are arranged in the same way. The extension direction of the connection line between the first electrode and the second electrode in the same capacitor core intersects with a first direction; and the first direction is the direction in which the first surface is vertically directed to the second surface. The relative position relationship between the first electrode and the second electrode in the same capacitor core is reasonably arranged, the uniformity of current transmission in the capacitor core is improved, the compactness of the capacitor core arrangement is ensured, the space occupation area is reduced, and the power density is improved.

The present application relates to the technical field of electronics. Provided are a memory array and a manufacturing method therefor, and a memory and an electronic device, which are used for solving the problem of a capacitor structure in a memory having a low density of integration. The memory array comprises: a substrate, and a capacitor unit arranged on the substrate. The capacitor unit comprises a first electrode, a second electrode and a third electrode, wherein the first electrode, the second electrode and the third electrode all extend in the thickness direction of the substrate, the first electrode is arranged around the second electrode, and the second electrode is arranged around the third electrode. The capacitor unit further comprises a first dielectric layer and a second dielectric layer, wherein the first dielectric layer is arranged between the first electrode and the second electrode, and the second dielectric layer is arranged between the second electrode and the third electrode. The memory array is used for improving the density of integration of a capacitor structure.

This utility model relates to the field of capacitor technology, specifically to a combined thin-film capacitor that can improve capacitor reliability. It includes a housing, within which capacitor cores are disposed. The capacitor cores are arranged side-by-side at intervals. The positive electrodes of the two capacitor cores are arranged facing each other and are respectively connected to positive electrode leads. The positive electrode leads are connected to an upper electrode plate, which has two positive electrode leads. The negative electrodes of the two capacitor cores are respectively connected to the two ends of a negative electrode lead, which has two negative electrode leads. An insulating pad is disposed between the upper electrode plate and the negative electrode lead.

The utility model discloses a high-capacity low-ESR laminated solid-state aluminum capacitor which comprises a shunt capacitor body, and the shunt capacitor body comprises a plurality of capacitor split bodies which are stacked up and down and connected in parallel. Each capacitor split body comprises a plurality of capacitor chips, a conduction frame and a shell, the capacitor chips and the conduction frame are arranged in the shell, the two surfaces of the conduction frame are both provided with a plurality of superposed capacitor chips, an anode pin and a cathode pin are respectively led out from the two sides, facing the shell, of the conduction frame, and the anode pin and the cathode pin are connected with the shell. The anode pins of the plurality of capacitor split bodies are connected in a conductive manner, and the cathode pins of the plurality of capacitor split bodies are connected in a conductive manner. According to the invention, the plurality of capacitor split bodies which are stacked up and down and connected in parallel are arranged, and the anode pin and the cathode pin of each capacitor split body are connected in a conducting manner, so that the capacity and the yield of the capacitor can be effectively improved.

The present application provides a power conversion device capable of improving the cooling effect of a capacitor. The power conversion device has: a capacitor having first and second terminal electrodes facing each other; a power module having a power semiconductor element; a terminal base for electrically connecting the capacitor and the power module to each other; first and second bus bars connecting the first and second terminal electrodes and the terminal base, respectively; and a board member on which the capacitor, the power module, and the terminal base are placed and which has a flow path of a cooling medium that cools the capacitor and the terminal base, the capacitor having the first terminal electrode facing the flow path side and the second terminal electrode facing the opposite side of the flow path, the terminal base having a first connecting portion connected to the first bus bar and a second connecting portion connected to the second bus bar, and having a higher thermal conductivity between the capacitor and the flow path than the first connecting portion.