Novel ferroelectric memory capacitor based on MFIS structure and preparation method thereof

Abstract

The invention belongs to the field of semiconductors, and discloses a novel ferroelectric memcapacitor based on an MFIS structure and a preparation method thereof, a substrate of the novel ferroelectric memcapacitor comprises a first doped region and a second doped region, and the doping type of the first doped region is p-type; the insulating layer, the ferroelectric layer and the top electrode layer are arranged on the substrate from bottom to top and cover the first doped region of the substrate; an uncovered area on the surface of the substrate is a second doped area, and the doping type of the second doped area is n type; the bottom electrode layer is located in the second doped region of the substrate and is far away from the first doped region; the channel is located in the second doped region of the substrate and is close to the first doped region; the invention also provides a corresponding preparation method, according to the ferroelectric memcapacitor prepared by using the method, because the semiconductor layer has a PN junction depletion region, the ferroelectric film can be fully overturned by using a band-to-band tunneling mechanism without large voltage, and meanwhile, the capacitance of the depletion region of the PN junction on one side of the semiconductor is adjusted, so that a relatively high capacitance-to-switch ratio is obtained while low power consumption is ensured.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductors, and particularly relates to a novel ferroelectric memistor based on an MFIS structure and a preparation method thereof. BACKGROUND

[0002] With the rise of artificial intelligence, neuromorphic computing, sensing and edge computing, the traditional von Neumann architecture has been unable to meet the demand for high parallelism and low power consumption processing, and the memistor has gradually become an important research object of the next generation of computing and storage fusion systems due to its low power consumption, non-volatility and other characteristics. The current research on the implementation of the memistor is developing in the direction of higher integration, lower power consumption and better stability.

[0003] Currently, a memistor based on charge tunneling, a memistor based on two-dimensional materials and a memistor based on ferroelectric materials have been proposed. Among them, the memistor constructed by a novel ferroelectric material has attracted widespread attention. The charge tunneling memistor uses trap states in the dielectric layer to capture charges, thereby changing the dielectric response and changing the capacitance state. The two-dimensional material memistor uses black phosphorus, molybdenum disulfide, graphene and other two-dimensional semiconductor materials to construct a heterojunction, and changes the capacitance state by charge transfer between material layers. However, the reliability problems of the two technical solutions cannot be ignored. The stability of the charge tunneling memistor is seriously affected by the defect state density and charge leakage, and the weak adhesion between the two-dimensional material layers and the poor environmental stability also limit its application.

[0004] The ferroelectric memistor utilizes the polarization hysteresis characteristics of the ferroelectric material to present nonlinear response and hysteresis effect of capacitance under different excitation voltages, thereby realizing the regulation of the capacitance state. Compared with the above two kinds of memistors, the ferroelectric memistor has stable material properties, and the capacitance value is adjustable by voltage, which has great application advantages. Current ferroelectric capacitors mostly use novel ferroelectric materials such as hafnium-zirconium oxide and hafnium-aluminum oxide. Compared with traditional ferroelectric materials such as PZT and BaTiO3, they have the advantages of being fully compatible with CMOS process and not requiring high-temperature process, which is suitable for large-scale integration and can meet the needs of current advanced process nodes.

[0005] In terms of ferroelectric memistor structure, MFM structure ferroelectric memistor and MFMS structure ferroelectric memistor are widely studied. The MFM structure ferroelectric memistor has the advantages of simple preparation process, small working voltage and low power consumption, and has potential for large-scale integration application. The capacitance on-off ratio of the MFM structure ferroelectric memistor depends on the capacitance change of the ferroelectric layer itself, and the on-off ratio is small, which requires high precision of the peripheral control circuit in actual application and is easy to cause signal misreading.

[0006] The ferroelectric memistor of the MFMS structure introduces a layer of semiconductor material (silicon, oxide semiconductor, etc.) below the metal. When a positive bias voltage is applied, the total capacitance size is mainly affected by the ferroelectric capacitance size. When a reverse bias voltage is applied, the surface of the semiconductor material is partially depleted, and a small depletion layer capacitance is introduced into the total capacitance, so that the total capacitance size is affected by the depletion layer capacitance, thereby increasing the capacitance switching ratio of the device. The capacitance size of the ferroelectric memistor of the MFMS structure is basically unchanged when a fixed positive bias voltage is applied. The depletion layer capacitance of the semiconductor interface is reduced by applying a large reverse bias voltage, thereby reducing the size of the total capacitance. The MFMS structure introduces a single layer of semiconductor material with single polarity, which causes the ferroelectric layer to be unable to completely flip on one side when flipping, and the thickness of the depletion region is limited, so that the ability to increase the switching ratio is limited, and the inherent non-volatility advantage cannot be fully utilized. In order to form a depletion region, a high voltage is required, which increases power consumption.

[0007] Therefore, it is necessary to provide a new ferroelectric memistor which can fully flip the ferroelectric thin film without a large voltage, adjust the depletion layer capacitance of the PN junction on one side of the semiconductor, and obtain a higher capacitance switching ratio while ensuring low power consumption. SUMMARY

[0008] In view of the technical problems in the background art, the purpose of the present application is to provide a new ferroelectric memistor based on the MFIS structure and a preparation method thereof. The new ferroelectric memistor is based on the MFIS (Metal-Ferroelectric-Insulator-Semiconductor) structure, which can fully flip the ferroelectric thin film without a large voltage, adjust the depletion layer capacitance of the PN junction on one side of the semiconductor, and obtain a higher capacitance switching ratio while ensuring low power consumption.

[0009] In order to achieve the above-mentioned purpose, the present application adopts the following technical means: In a first aspect of the present application, a new ferroelectric memistor based on the MFIS structure is provided, which includes a semiconductor substrate, an insulating layer, a ferroelectric layer, and a top electrode layer and a bottom electrode layer. The semiconductor substrate includes a first doped region and a second doped region, and the doping type of the first doped region is p-type. The insulating layer, the ferroelectric layer, and the top electrode layer are arranged on the semiconductor substrate from bottom to top and cover the first doped region of the semiconductor substrate. The uncovered area of the semiconductor substrate surface is the second doped region, and the doping type of the second doped region is n-type. The bottom electrode layer is located at the outer edge of the second doped region of the semiconductor substrate. The channel is located inside the second doped region of the semiconductor substrate.

[0010] Further, the semiconductor substrate is an SOI substrate or a Si substrate.

[0011] Further, the SOI substrate is stacked by a Si layer, a SiO2 layer and a p-type Si layer.

[0012] Further, the insulating layer is a SiO2 insulating layer with a thickness of 1-3 nm.

[0013] Further, the deposition thin film material used by the ferroelectric layer is one of HfZrO x , HfAlO x ; the thickness of the ferroelectric layer is 3-12 nm.

[0014] Further, the top electrode layer and the bottom electrode layer are metal layers formed by sputtering using one of metal W and TiN, with a thickness of 10-100 nm.

[0015] Further, the channel doping concentration is 1e13 cm -3 -1e17 cm -3 .

[0016] Further, when a positive pulse voltage is applied on the top electrode layer, the p-type region below the top electrode layer is inverted into an n-type region, the PN junction space charge region disappears, the total capacitance of the device is the sum of the ferroelectric capacitance and the insulating layer capacitance in parallel, and is in a high capacitance state; when a negative pulse voltage is applied on the top electrode layer, the p-type region below the top electrode layer generates accumulation of holes through band-to-band tunneling, the PN junction space charge region widens, the PN junction capacitance decreases, and the total capacitance of the device is the sum of the ferroelectric capacitance, the insulating layer capacitance and the PN junction depletion region capacitance in parallel, and is in a low state capacitance.

[0017] The second aspect of the present application provides a preparation method of the novel ferroelectric memcapacitor based on the MFIS structure according to the first aspect, comprising the following steps: S1, providing a semiconductor substrate and cleaning it; S2, using rapid thermal oxidation RTO treatment to passivate the upper surface of the semiconductor substrate to form a SiO2 insulating layer; S3, using atomic layer deposition ALD to deposit a ferroelectric layer on the SiO2 insulating layer; S4, performing rapid thermal processing RTP in a N2 atmosphere to crystallize the ferroelectric layer; S5, using physical vapor deposition PVD to sputter metal on the ferroelectric layer to deposit a top electrode layer; S6, removing the top electrode layer, the ferroelectric layer and the insulating layer on the top electrode layer by photolithography and plasma etching to form a window in the active region of the semiconductor substrate; S7, injecting N-type impurities into the active region window in an ion implantation mode, and forming an N-type active region through doping; S8, performing rapid thermal processing (RTP) to activate the doping of the N-type active region; S9, sputtering metal on the N-type active region window formed through photolithography using physical vapor deposition (PVD), and locally depositing to form a bottom electrode layer, thereby obtaining a new ferroelectric memistor, wherein the channel of the new ferroelectric memistor is located on the semiconductor substrate.

[0018] Further, the semiconductor substrate is an SOI substrate or a Si substrate.

[0019] Further, the SOI substrate is formed by stacking a Si layer, a SiO2 layer and a p-type Si layer.

[0020] Further, the semiconductor substrate is cleaned using a wet chemical cleaning RCA process.

[0021] Further, in step S2, the thickness of the SiO2 insulating layer is 1nm-3nm.

[0022] Further, in step S3, the thin film material of the deposited ferroelectric layer is one of HfZrO x , HfAlO x ; and the thickness of the deposited ferroelectric layer is 3nm-12nm.

[0023] Further, in step S4, the temperature of the RTP processing is 300℃-600℃, and the time is 30s-60s.

[0024] Further, in steps S5 and S9, the sputtered metal is one of W and TiN, and the thickness of the formed metal layer is 10nm-100nm.

[0025] Further, in step S9, the doping concentration of the channel is 1e13 cm -3 -1e17 cm -3 .

[0026] Compared with the prior art, the present application has the following beneficial effects: The new ferroelectric memistor of the present application introduces a PN junction structure in the Si layer of the SOI substrate, replaces the unipolar semiconductor layer used in the traditional MFMS structure, the PN junction forms an n+ doped region in the p-type silicon through an ion implantation process, thereby constructing an adjustable space charge region in the channel region, and at the same time, an MFIS (metal-ferroelectric layer-insulating layer-semiconductor) stack is constructed on the SOI substrate.

[0027] The novel ferroelectric memcapacitor has a PN junction depletion region due to the existence of the semiconductor layer, utilizes the band-to-band tunneling mechanism, and can fully flip the ferroelectric thin film without a large voltage, while adjusting the depletion region capacitance of the PN junction on the semiconductor side, so as to obtain a higher capacitance switching ratio while ensuring low power consumption. The band-to-band tunneling mechanism is used to control the low-power ferroelectric polarization, and the capacitance switching ratio is significantly improved through the PN junction depletion region capacitance adjustment, which takes into account non-volatility, low power consumption and high switching ratio, and is a key improvement of the traditional ferroelectric memcapacitor structure.

[0028] In the channel, there is a PN junction space charge region between the p-type region and the n+ heavily doped active region. When a positive pulse voltage is applied to the top electrode layer, the p-type region below the top electrode layer is inverted to an n-type region, the PN junction space charge region disappears, and the total capacitance of the device is the sum of the parallel connection of the ferroelectric capacitance and the insulating layer capacitance, which is the high capacitance state. When a negative pulse voltage is applied to the top electrode layer, the p-type region below the top electrode layer accumulates holes through band-to-band tunneling, the PN junction space charge region widens, and the PN junction capacitance decreases. At this time, the total capacitance of the device is the sum of the parallel connection of the ferroelectric capacitance, the insulating layer capacitance and the PN junction depletion region capacitance, which is the low state capacitance. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 The structure schematic diagram of the MFIS structure ferroelectric memcapacitor in the first embodiment of the application is shown. Figure 2 The structure schematic diagram of the MFIS structure ferroelectric memcapacitor in the second embodiment of the application is shown. Figure 3 The flow chart of the preparation method of the MFIS structure ferroelectric memcapacitor in the first embodiment of the application is shown. Figure 4 The structure schematic diagram of each stage of the preparation method of the MFIS structure ferroelectric memcapacitor in the first embodiment of the application is shown. Figure 5 The capacitance equivalent diagram of the MFIS structure ferroelectric memcapacitor in the first embodiment of the application under the action of a positive pulse voltage and a positive pulse voltage is shown. DETAILED DESCRIPTION

[0030] In order to make the technical problems, technical solutions and beneficial effects solved by the application more clear and explicit, the application will be further described in detail below in combination with embodiments.

[0031] EMBODIMENT

[0032] The following examples are put forth so as to provide those of ordinary skill in the art with the best understanding of how to make and use the application, and are not to be construed as limiting the same. The examples disclosed herein represent preferred techniques for practicing the application, and thus can be considered to be preferred embodiments of the application. However, those of ordinary skill in the art will appreciate that many modifications can be made to the examples disclosed herein without departing from the spirit or scope of the application.

[0033] In the description of the present application, it should be noted that the terms "upper", "lower", "vertical", "horizontal" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance.

[0034] In the following, many specific details of the present application are described, such as the structure, materials, dimensions, processing and techniques of the device, in order to make the present application more clearly understood. However, as those skilled in the art can understand, the present application can be implemented without these specific details, unless otherwise specified, and each part of the device can be composed of materials known to those skilled in the art, or materials with similar functions developed in the future.

[0035] As shown in Figure 1 The first embodiment of the present application is based on a new ferroelectric memcapacitor structure with MFIS structure.

[0036] As shown in Figure 1 The new ferroelectric memcapacitor includes a p-type SOI substrate, an insulating layer 103, a ferroelectric layer 104, and a top electrode layer 105, a bottom electrode layer 107. In the present embodiment, the p-type SOI substrate is composed of a first Si layer 100, a SiO2 layer 101 and a second Si layer 102; the doping type of the second Si layer 102 is p-type.

[0037] The SOI substrate includes a first doped region and a second doped region, the insulating layer 104, the ferroelectric layer 105 and the top electrode layer 105 are arranged on the p-type SOI substrate from bottom to top, covering the first doped region of the substrate, and the doping type of the first doped region is p-type.

[0038] The insulating layer 103 is a SiO2 insulating layer, and the thickness of the insulating layer 103 is 1 nm, 2 nm, 3 nm or any value between 1 nm and 3 nm.

[0039] The ferroelectric layer 104 is made of material HfZrO x The HfAlO deposited x The thin film layer. In another embodiment of the present application, the ferroelectric layer 104 is made of material HfAlO x The HfAlO deposited x The thin film layer. The thickness of the ferroelectric layer 104 is any integer or non-integer value between 3 nm and 12 nm.

[0040] The uncovered region of the SOI substrate surface is the active region, and the active region is formed into an n-type active region 106 by n-type impurity injection; that is, the second doped region, and the doping type of the second doped region is n-type.

[0041] The bottom electrode layer 107 is located in the second doped region of the SOI substrate and away from the first doped region; that is, the bottom electrode layer is located at the outer edge of the n-type active region 106 of the SOI substrate.

[0042] The channel is located in the second doped region of the substrate and close to the first doped region; that is, the channel is located inside the n-type active region 106 of the substrate.

[0043] The channel doping concentration is any integer or non-integer value between 1e13 cm -3 and 1e17 cm -3 .

[0044] The top electrode layer 105 and the bottom electrode layer 107 are metal layers formed by sputtering of one of the metals W and TiN, and the thickness is any integer or non-integer value between 10 nm and 100 nm.

[0045] In some embodiments of the present application, the top electrode layer 105 is a W metal layer formed by sputtering of metal W, and the bottom electrode layer 107 is a W metal layer formed by sputtering of metal W; in another embodiment of the present application, the top electrode layer 105 is a TiN metal layer formed by sputtering of metal TiN, and the bottom electrode layer 107 is a W metal layer formed by sputtering of metal W; in another embodiment of the present application, the top electrode layer 105 is a W metal layer formed by sputtering of metal W, and the bottom electrode layer 107 is a TiN metal layer formed by sputtering of metal TiN; in another embodiment of the present application, the top electrode layer 105 is a TiN metal layer formed by sputtering of metal TiN, and the bottom electrode layer 107 is a TiN metal layer formed by sputtering of metal TiN.

[0046] As shown in FIG. 2, the second embodiment of the present application is a new ferroelectric memistor structure based on the MFIS structure. Figure 2

[0047] As shown in FIG. 2, the second embodiment of the present application is a new ferroelectric memistor structure based on the MFIS structure. Figure 2 ​As shown, a novel ferroelectric memistor based on MFIS structure includes a p-type Si substrate 100, an insulating layer 103, a ferroelectric layer 104, and a top electrode layer 105 and a bottom electrode layer 107. The Si substrate includes a first doped region and a second doped region, the insulating layer 103, the ferroelectric layer 104, and the top electrode layer 105 are arranged on the p-type Si substrate from bottom to top, covering the first doped region of the substrate, and the first doped region is of p-type.

[0048] The insulating layer 103 is a SiO2 insulating layer, and the thickness of the insulating layer 103 is 1 nm, 2 nm, 3 nm, or any value between 1 nm and 3 nm.

[0049] The deposition thin film material of the ferroelectric layer 104 is one of HfZrO x and HfAlO x In this embodiment, the ferroelectric layer 104 is a HfAlO x thin film layer deposited by using the material HfAlO x In another embodiment of the present application, ， the ferroelectric layer 104 is a HfAlO x thin film layer deposited by using the material HfAlO x The thickness of the ferroelectric layer 104 is any integer or non-integer value between 3 nm and 12 nm.

[0050] The uncovered region of the Si substrate surface is an active region, and the active region is formed into an n-type active region 106 by n-type impurity injection; that is, a second doped region, and the second doped region is of n-type.

[0051] The bottom electrode layer 107 is located in the second doped region of the Si substrate and away from the first doped region; that is, the bottom electrode layer 107 is located at the outer edge of the n-type active region 106 of the Si substrate.

[0052] The channel is located in the second doped region of the Si substrate and close to the first doped region; that is, the channel is located inside the n-type active region 106 of the Si substrate.

[0053] The channel doping concentration is any integer or non-integer value between 1e13 cm -3 and 1e17 cm -3 .

[0054] The top electrode layer 105 and the bottom electrode layer 107 are metal layers formed by sputtering one of metal W and TiN, and the thickness is any integer or non-integer value between 10 nm and 100 nm.

[0055] In some embodiments of the present application, the top electrode layer 105 is a W metal layer formed by sputtering of metal W, and the bottom electrode layer 107 is a W metal layer formed by sputtering of metal W; in another embodiment of the present application, the top electrode layer 105 is a TiN metal layer formed by sputtering of metal TiN, and the bottom electrode layer 107 is a W metal layer formed by sputtering of metal W; in another embodiment of the present application, the top electrode layer 105 is a W metal layer formed by sputtering of metal W, and the bottom electrode layer 107 is a TiN metal layer formed by sputtering of metal TiN; in another embodiment of the present application, the top electrode layer 105 is a TiN metal layer formed by sputtering of metal TiN, and the bottom electrode layer 107 is a TiN metal layer formed by sputtering of metal TiN.

[0056] Figure 3 A flow chart of a method for preparing a new ferroelectric memistor of an MFIS structure of a first embodiment of the present application is shown, Figure 4 -A to Figure 4 -H shows Figure 3 The structure of the semiconductor device in each step is shown in the structure diagram of the semiconductor device. Figure 4 -A to Figure 4 -H The manufacturing method of the semiconductor device of the first embodiment of the present application is described in detail.

[0057] In step S1, a semiconductor substrate is provided, and an RCA cleaning process is performed thereon. Specifically, as shown in Figure 4 -A, the semiconductor substrate is a p-type SOI substrate, which is composed of a Si layer 100, a SiO2 layer 101, and a p-type Si layer 102. The RCA cleaning process is as follows: organic matter is removed in an NH4OH-H2O2-H2O solution, a natural oxide layer is removed in an HF diluent, and metal ions are removed in an HCl-H2O2-H2O solution. The temperature during the cleaning process is controlled at 75-80 ℃, and then pure water is used for rinsing and nitrogen is used for drying. In some other embodiments, the semiconductor substrate is a p-type Si substrate.

[0058] In step S2, an RTO process is performed to passivate the upper surface of the SOI substrate to form a SiO2 insulating layer. Specifically, rapid thermal oxidation is performed in a dry oxygen atmosphere at a temperature of 900 ℃ for 30-60 s to passivate the upper surface of the SOI substrate to form a SiO2 insulating layer 103. The thickness of the formed SiO2 insulating layer is 1-3 nm, and the structure is shown in Figure 4 -B.

[0059] In step S3, a ferroelectric layer 104 is deposited on the SiO2insulating layer 103 by ALD, specifically, using alternating pulse tetramethylhafnium (TDMA-Hf) and tetramethylzirconium (TDMA-Zr) as precursors, with water vapor as an oxidant, the deposition temperature is controlled at 250°C, about 0.1 nm is deposited per ALD cycle, nitrogen is used as the carrier gas, the flow rate is maintained at 100 sccm, the precursor pulse time is 0.5 seconds, and the inert gas purge time between pulses is 10 seconds. The thin film material of the deposited ferroelectric layer 104 is one of HfZrOx, HfAlOx, the thickness of the ferroelectric layer 104 is 3 nm to 12 nm, and the structure after the formation of the ferroelectric layer 104 is as shown in FIG. 1C. Figure 4 In some other embodiments, alternating pulse tetramethylhafnium (TDMA-Hf) and aluminum precursor trimethylaluminum (TMA, Al(CH3)3) are used as precursors.

[0060] In step S4, RTP treatment is performed in an N2atmosphere to crystallize the ferroelectric layer 104, specifically, the RTP treatment temperature is 300°C to 600°C, and the time is 30 s to 60 s in an N2atmosphere; the structure after the treatment is as shown in FIG. 1D. Figure 4

[0061] In step S5, a top electrode layer 105 is deposited and formed on the ferroelectric layer 104 by using PVD sputtering metal; specifically, the PVD sputtering vacuum degree is 5 × 10 -7 Torr, the target sputtering metal is W or TiN in an argon atmosphere, the sputtering power is 100 W to 300 W, the chamber temperature is room temperature, the thickness of the formed metal layer is 10 nm to 100 nm, and the structure after the deposition and formation of the top electrode layer 105 is as shown in FIG. 1E. Figure 4

[0062] In step S6, an active region window on the SOI substrate is formed on the top electrode layer 105 by plasma etching, the etching selects CF4and Ar mixed gas (CF4 30 sccm, Ar 20 sccm), the radio frequency power is set to 200 W to 300 W, and the structure after the etching is as shown in FIG. 1F. Figure 4 In some other embodiments, photolithography etching is used.

[0063] In step S7, N-type impurities are injected into the active region window by ion implantation to form an N-type active region 106 by doping, specifically, the ion implantation energy is 30 keV to 100 keV, the ion implantation gas uses P + or As + ion beam, and the structure after the ion implantation is as shown in FIG. 1G. Figure 4

[0064] ​​​In step S8, RTP processing is performed, and activation of the doping is performed at 900-1050°C for 10-30 seconds.

[0065] In step S9, a PVD sputtering metal W or TiN is used to form a bottom electrode layer 107 with a thickness of 10-100 nm, and a channel is formed on the semiconductor substrate, and the structure is as shown in Figure 4 -H, that is, a new ferroelectric memcapacitor is obtained.

[0066] In some embodiments of the present application, the top electrode layer 105 is a W metal layer formed by sputtering of metal W, and the bottom electrode layer 107 is a W metal layer formed by sputtering of metal W; in another embodiment of the present application, the top electrode layer 105 is a TiN metal layer formed by sputtering of metal TiN, and the bottom electrode layer 107 is a W metal layer formed by sputtering of metal W; in another embodiment of the present application, the top electrode layer 105 is a W metal layer formed by sputtering of metal W, and the bottom electrode layer 107 is a TiN metal layer formed by sputtering of metal TiN; in another embodiment of the present application, the top electrode layer 105 is a TiN metal layer formed by sputtering of metal TiN, and the bottom electrode layer 107 is a TiN metal layer formed by sputtering of metal TiN.

[0067] Figure 5 An application of a new ferroelectric memcapacitor based on the MFIS structure disclosed in the fourth embodiment of the present application is shown. When a positive pulse voltage is applied to the top electrode layer 105, the p-type region below the top electrode layer 105 is inverted into an n-type region, the PN junction space charge region disappears, and the total capacitance of the device is the sum of the ferroelectric capacitance and the insulating layer capacitance in parallel, as shown in Figure 5 (A), which is a high-capacitance state; when a negative pulse voltage is applied to the top electrode layer 105, the p-type region below the top electrode layer 105 generates accumulation of holes through band-to-band tunneling, the PN junction space charge region widens, and the PN junction capacitance decreases, and the total capacitance of the device is the sum of the ferroelectric capacitance, the insulating layer capacitance, and the PN junction depletion region capacitance in parallel, as shown in Figure 5 (B), which is a low-capacitance state.

[0068] All the documents mentioned in the present application are incorporated by reference in the present application, as if each document is individually incorporated by reference. In addition, it should be understood that, after reading the above description of the present application, those skilled in the art can make various modifications or changes to the present application, and these equivalent forms also fall within the scope of the appended claims of the present application.

Claims

1. A novel ferroelectric memcapacitor based on the MFIS structure, characterized by: It includes a substrate, an insulating layer, a ferroelectric layer, a top electrode layer, and a bottom electrode layer; A substrate, comprising a first doping region and a second doping region, wherein the first doping region is of p-type doping type; The insulating layer, the ferroelectric layer and the top electrode layer are arranged from bottom to top on the substrate, covering the first doped region of the substrate; The uncovered area on the substrate surface is a second doped area, and the doping type of the second doped area is n-type; The bottom electrode layer is located in the second doping region of the substrate and is away from the first doping region; The channel is located in the second doping region of the substrate and is close to the first doping region.

2. The novel ferroelectric memcapacitor based on the MFIS structure according to claim 1, characterized in that: The substrate is an SOI substrate or a Si substrate.

3. The novel ferroelectric memcapacitor based on the MFIS structure according to claim 2, characterized in that: The SOI substrate is formed by stacking a Si layer, a SiO2 layer and a p-type Si layer.

4. The novel ferroelectric memcapacitor based on the MFIS structure according to claim 1, characterized in that: The insulating layer is a SiO2 insulating layer with a thickness of 1 nm to 3 nm.

5. The novel ferroelectric memcapacitor based on the MFIS structure according to claim 1 is characterized in that: The deposited thin film material used in the ferroelectric layer is HfZrO x 、HfAlO x One of the above; the thickness of the ferroelectric layer is 3nm to 12nm.

6. The novel ferroelectric memcapacitor based on the MFIS structure according to claim 1, characterized in that: The top electrode layer and the bottom electrode layer are metal layers formed by sputtering one of metal W and TiN, and have a thickness of 10 nm to 100 nm.

7. The novel ferroelectric memcapacitor based on the MFIS structure according to claim 1, characterized in that: The channel doping concentration is 1e13 cm -3 ~1e17 cm -3 .

8. The novel ferroelectric memcapacitor based on the MFIS structure according to claim 1, characterized in that: When a positive pulse voltage is applied to the top electrode layer, the p-type region below the top electrode layer is inverted to an n-type region, the PN junction space charge region disappears, and the total capacitance of the device is the sum of the ferroelectric capacitance and the insulating layer capacitance in parallel, which is a high capacitance state; when a negative pulse voltage is applied to the top electrode layer, the p-type region below the top electrode layer accumulates holes through band-to-band tunneling, the PN junction space charge region widens, the PN junction capacitance decreases, and the total capacitance of the device is the sum of the ferroelectric capacitance, the insulating layer capacitance, and the PN junction depletion region capacitance in parallel, which is a low capacitance.

9. The method for preparing a novel ferroelectric memristor based on the MFIS structure according to any one of claims 1 to 8, characterized in that: The steps include: S1. Provide a semiconductor p-type substrate; S2, passivating the upper surface of the semiconductor substrate to form an insulating layer; S3, depositing a ferroelectric layer on the insulating layer; S4, treating in an N2 atmosphere to crystallize the ferroelectric layer; S5, sputtering metal on the ferroelectric layer to deposit and form a top electrode layer; S6. forming an active area window on the substrate by etching the top electrode layer; S7, implanting n-type impurities into the active area window by ion implantation to form an n-type active area by doping; S8, activating the doping; S9. Sputtering metal on the n-type active area window, partially depositing to form a bottom electrode layer, and forming a channel in the undeposited part, thus obtaining a new ferroelectric memristor.

10. The method for preparing a novel ferroelectric memristor based on the MFIS structure according to claim 9, characterized in that: The thickness of the insulating layer is 1nm to 3nm; the thickness of the ferroelectric layer is 3nm to 12nm; the thickness of the top electrode layer and the bottom electrode layer is 10nm to 100nm; the channel doping concentration is 1e13 cm -3 ~1e17 cm -3 .

Images