499 results about "Switching time" patented technology

The invention provides an HPLC (High Performance Liquid Chromatography) station area cooperative communication method based on clock synchronization, which comprises the following steps: step 1, multi-dimensional data acquisition and broadcasting: each concentrator periodically acquires clock precision, stability and reliability data, and sends a beacon frame containing a timestamp and a health degree score through a power line carrier broadcasting channel; step 2, dynamically calculating the index distinction degree by using an entropy weight method, adaptively allocating weights, and electing an optimal main CCO in real time; step 3, dual-mode PID cooperative control: the main CCO adopts a dual-mode switching strategy of a dynamic PID algorithm and a chaotic fractional order PID algorithm; 4, monitoring a synchronization state in real time by constructing a clock check network, and optimizing a fault isolation strategy in combination with weighted scoring to realize that the state switching time of the master node and the slave node is less than or equal to 50ms; cooperative communication is realized on the basis of completing synchronization of the concentrators CCO in the whole network. Redundant message transmission is reduced through a dynamic parameter resynchronization mechanism, and the utilization rate of network resources is optimized.

The invention relates to the technical field of gallium nitride gate drivers, and discloses a design method and system of a gallium nitride gate driver, and the method comprises the steps: carrying out the working signal collection of the gallium nitride gate driver, obtaining original waveform sampling data, and building a signal integrity model under the action of electromagnetic interference; separating the original waveform sampling data into an effective driving signal, a low-frequency interference signal and a high-frequency noise signal, and extracting characteristic parameters to obtain a signal characteristic parameter set; switching time and circuit power consumption are set as optimization variables, constraint conditions are set according to the signal integrity model, and an optimization objective function is obtained; performing online identification and optimization calculation on the driving parameters to obtain a driving control parameter sequence; according to the method, the adaptive capacity of the driver to the change of the working condition is improved, and meanwhile, the stability and the reliability of the driving waveform are ensured.

The invention discloses a motor and a control method and device thereof, a storage medium and a computer program product, and the method comprises the steps: enabling the actual q-axis current of the motor to be equal to the given q-axis current of the motor, employing a preset current-frequency starting mode, and controlling the open-loop starting of the motor in a speed loop; determining target switching time, switching point q-axis current and a target rotor angle of the motor according to the target torque, the set rotor angular speed and the actual rotor angle of the motor; and in combination with the given q-axis current of the motor, the switching point q-axis current, the target switching time, the actual rotor angle and the target rotor angle, adopting a preset sectional gentle reduction control strategy to control the given q-axis current of the motor to be reduced to the switching point q-axis current of the motor in a sectional manner, and switching from an open loop to a closed loop to realize stable starting of the motor. According to the scheme, the q-axis current is reduced in a three-section gentle slope mode, speed open-loop starting gentle slope smooth switching to closed-loop control is achieved, and the motor is started stably.

The invention relates to the technical field of drivers, and discloses a low-delay control method, system, equipment and medium for a gallium nitride gate driver, and the method comprises the steps: carrying out the feature extraction and nonlinear mapping processing of the driving voltage, gate charge and switching time sequence parameters of the gate driver, and obtaining time domain characteristic data and a parameter distribution model; duty ratio modulation function calculation is carried out to obtain a rising edge duty ratio parameter and a falling edge duty ratio parameter; performing dynamic planning solution on the state transition equation to obtain an optimal control sequence; performing driving control on a gate driver according to the optimal control sequence, and acquiring running state data through a plurality of monitoring points to obtain an actual driving delay value and an actual switching loss value; the Gaussian process model is constructed based on the actual driving delay value and the actual switching loss value, the updated control parameters are obtained through iterative sampling calculation, the optimal control sequence considering multivariable constraints is obtained, and the accuracy of driving control is remarkably improved.

The invention discloses a method for switching between a first communication mode and a second communication mode, and the method comprises the steps: determining a dual-mode phase difference between a first mode baseband signal and a second mode parameter based on the first mode baseband signal and the second mode parameter; generating an interleaved phase coding sequence in response to the dual-mode phase difference; pre-modulating the first mode signal in parallel before switching by using the coding sequence, and generating a pre-activated second mode virtual signal; switching from the first mode to the second mode is executed based on a parallel fusion phase track generated after the phases of the two preprocessed signals are subjected to time-varying weighted fusion. According to the method, a smooth switching track is constructed through parallel phase preview and phase domain fusion, phase continuity and frequency stability in the switching process are ensured, switching time delay and the data error rate are remarkably reduced, and the communication service quality of the heterogeneous network is improved.

The invention discloses a time division duplex multi-carrier synchronous transmission method based on 5G, which relates to the technical field of communication, and comprises the following steps of: establishing a carrier mapping table, respectively mapping a plurality of logic carriers to predefined physical resource blocks, and marking uplink and downlink switching time slots according to a time division mode; after a user terminal receives a synchronization signal, alignment is carried out through a high-precision local clock and the reference time of a main base station, and a synchronization reference point is recorded with a nanosecond-level time resolution. According to the invention, through the dynamic synchronization control and frequency domain interference suppression technology, the synchronization stability and the data transmission reliability in a high-speed scene are significantly improved; a synchronous load scoring mechanism is introduced to realize efficient scheduling and conflict avoidance of synchronous resources in a multi-user concurrent environment; and in combination with interference weight estimation and an adaptive filtering strategy, the anti-interference capability and environment adaptability of the system are effectively enhanced, and the requirements of key services such as the Internet of Vehicles and industrial control on low-delay and high-reliability communication are comprehensively met.

The invention discloses a standby power supply intelligent monitoring and switching control system and method based on the Internet of Things, and relates to the technical field of standby power supply intelligent switching, and the method comprises the following steps: setting an optimal reference switching time threshold in combination with the historical operation data, load characteristics and technical specifications of standby power supply switching; an initial secure handover period is defined. According to the invention, the key jump from timed switching to state sensing driving switching is realized, so that the system can comprehensively sense the phase synchronization state between the main power supply and the standby power supply before switching, and the phase jump trend is dynamically predicted and intelligently judged in combination with a machine learning model; therefore, impact current, equipment damage and regional tripping risks caused by forced switching due to inconsistent phases are effectively avoided, and the safety, the accuracy and the intelligent level of the switching process of the standby power supply are remarkably improved.

The invention provides a mainboard power supply output voltage stability test method and system, and the method comprises the steps: generating a dynamic stepped load current based on a load demand parameter and a limit working condition defined by a hardware specification when a mainboard operates in a preset multi-mode switching state, and setting a first synchronization window before each step switching moment, setting a second synchronization window after the step switching time, collecting voltage waveform data, inputting the voltage waveform data into a preset filtering algorithm, extracting an overshoot amplitude and recovery time, constructing an asymmetric coupling model, and taking a difference value between the overshoot amplitude and a preset fluctuation range as a first stability index; the ratio of the recovery time to the response time threshold value is used as a second stability index, nonlinear weight distribution of the two indexes in multiple step intervals is calculated, a stability grade judgment result is generated in combination with a circuit board wiring impedance characteristic library, and the test compatibility of high-density mainboard multi-phase power supply and high-frequency devices is improved.

The invention discloses a communication method, device and system and a storage medium, relates to the technical field of communication, and can ensure that all non-AP stations compete for a new TXOP at the same time after the TXOP is finished, and keep medium synchronization. The method comprises the following steps: a non-AP station obtains switching time indication information, and switches from a first channel to a second channel comprising a main 20MHz channel based on the switching time indication information. Wherein the first channel and the second channel are not overlapped, and the switching time is not later than the first time. The first moment is the latest moment when the non-AP station is switched from the first channel to the second channel. The first channel comprises one or more 20MHz channels used for communication between the non-AP station and the AP station in the current TXOP.

The invention discloses a function switching device for transformer testing and a testing system thereof, relates to the technical field of transformer testing, is used for solving the problem of low testing efficiency, and is used for setting a switching time reference by acquiring transformer capacity information and detecting the number of closed relays of testing nodes and loop resistance. Analyzing a resistance fluctuation index and loop harmonic characteristics by combining historical loop resistance data, correcting a switching time reference, detecting three-phase winding current, generating a current balance index, evaluating a fault risk level, screening and marking to-be-tested nodes according to the fault risk level, and after the current test node is tested, determining the current test node according to the fault risk level. And performing test processing on the marked to-be-tested nodes based on the corrected switching time reference, thereby realizing intelligent selection of a transformer test sequence, improving test efficiency and ensuring electrical state stability and test precision of each test node.

The invention relates to the technical field of keyboard pairing, and discloses a keyboard multimode pairing method and device, equipment and a storage medium. The method comprises the following steps: establishing a switching time calculation model of a keyboard according to the reference switching time of keyboard hardware, a protocol node cooperation coefficient, an equipment response weight coefficient and a pre-connection optimization coefficient; calculating the theoretical optimal switching time of the current switching scene; selecting a working mode of single-node direct switching, double-node pre-connection or three-node parallel pre-connection of a keyboard Bluetooth node, a 2.4 GHz node and a USB node; activating a corresponding communication node, sending a connection handshake signal to the target equipment and establishing a communication link pre-connection state; and switching keyboard input and output from the current equipment to the target equipment to finish quick connection switching between the equipment. According to the invention, a pre-connection mechanism is adopted, the target equipment connection is established in advance before the user completes the switching instruction, passive response switching is converted into active prediction switching, and instantaneous equipment switching is realized.

The invention provides a communication method and a communication device, which can be applied to a non-ground communication network, such as a satellite network, an unmanned aerial vehicle platform, a high-altitude platform and the like. In the method, a source access network device transmits the information to a target access network device through at least one of information of a transmission path between the source access network device and the target access network device, time information, or position information of the source access network device. And determining to switch the terminal equipment to the target equipment by adopting a switching mode based on an interface between the access network equipment or a switching mode based on an interface between the access network equipment and the core network equipment. The switching time delay of the terminal equipment can be reduced.

The invention discloses an OEO amplifier with a high-speed hard switching function and an optical transmission system, and relates to the technical field of optical amplifiers, the OEO amplifier comprises three magneto-optical switches, an optical splitter group, a photoelectric detector group, a real-time comparison circuit, a logic gate control circuit and a driving circuit; the photoelectric detector group collects optical signal power to generate an electric signal; the real-time comparison circuit performs voltage threshold judgment on the electric signal; the logic gate control circuit is connected with the output end of the real-time comparison circuit so as to synchronously control the switching states of the three magneto-optical switches according to a voltage threshold judgment result; the driving circuit is used for driving the magneto-optical switch to synchronously execute a switching action; when the OEO amplifier detects that optical signals in any direction are interrupted, all the magneto-optical switches finish synchronous switching within 100 microseconds, and the end-to-end optical signal switching time difference is smaller than 2 picoseconds. The method is suitable for a single-fiber bidirectional optical communication environment requiring high frequency, high precision and high stability.

The invention provides an uninterrupted redundant communication method and system, equipment and a medium, and belongs to the technical field of vehicle-mounted network communication.The method comprises the steps that data frames from two communication paths are received through two network interfaces respectively, CRC verification is carried out, wrong data frames are discarded, and the data frames passing verification are obtained; extracting the serial number of each data frame passing the verification as a target serial number, and comparing the target serial number with an expected serial number; if the target serial number is equal to the expected serial number, submitting the data frame to an upper application, and adding 1 to the expected serial number; wherein the data frame is generated by adding a globally unique and monotonically increasing serial number to each key application data frame by the sending end processing unit. According to the invention, fault switching delay is eliminated fundamentally, zero switching time is realized, and a crucial communication guarantee is provided for automatic driving of L4 and above.

A method can include transmitting, by a wireless device, a user equipment (UE) capability message indicating a switching time for a sounding reference signal (SRS) frequency hopping. The method can also include receiving one or more configuration parameters indicating an SRS resource for the SRS frequency hopping. The method can further include receiving, via a physical downlink control channel (PDCCH) monitoring occasion, a downlink control information (DCI) scheduling an uplink transmission. The method can additionally include transmitting the uplink transmission and dropping an SRS transmission, via the SRS resource, based on a time interval being at least a preparation time for the uplink transmission plus a switching time. The time interval can be between a last symbol of the PDCCH monitoring occasion and an SRS symbol. The SRS symbol can overlap with the uplink transmission.

The invention relates to an RF series switching device with switching time acceleration. An RF switching device includes: a shunt switch having a first RF terminal, a second RF terminal coupled to ground, a main control input, and an acceleration control input; a series switch having a first RF terminal coupled to the first RF terminal of the shunt switch, a second RF terminal, a main control input, and an acceleration control input; and a switching time acceleration circuit having a positive acceleration path input, a negative acceleration path input, and a first output coupled to the main control input of the series switch.

The invention discloses a half-bridge driving circuit and method in a multi-level topology based on an FPGA (Field Programmable Gate Array), the half-bridge driving circuit comprises an MCU (Microprogrammed Control Unit), an FPGA logic circuit and a signal isolation circuit, the FPGA logic circuit gathers fault signals of other circuits in a complete machine, when other circuits fail, the circuit is notified to carry out shutdown operation, and when the other circuits fail, the FPGA logic circuit does not fail, the signal isolation circuit does not fail. In the process of switching on to switching off and the process of switching off to switching on, a transition state that switching-on voltage and switching-off voltage are invalid exists in a period of time, impact in the state switching process is solved, soft switching-off of an outer tube and an inner tube of a power main device in the multi-level topology from outside to inside is achieved in case of a fault, and soft switching-off of the outer tube and the inner tube of the power main device in the multi-level topology is achieved. The gate driver has the advantages that the gate driver is simple in structure, combinational logic and complex sequential logic functions can be realized at low cost, the signal isolation circuit is used for controlling conversion and isolation of PWM (pulse-width modulation) pulse to voltage required by gate control signals of a power device of a main circuit, peak voltage limitation and inner and outer tube switching time sequences are realized, various faults can be monitored, and fault protection can be safely implemented.

The invention discloses a communication method and device which can be applied to a receiving end to receive a reference signal from a sending end in a frequency hopping mode. The method comprises: a network device sending a reference signal in a first time unit in a first frequency hopping unit, the first frequency hopping unit comprising the first time unit and a first switching time, the first time unit being used for transmitting the reference signal, and the first time unit and the first switching time not overlapping in a time domain; and the terminal equipment receives the reference signal in the first time unit. According to the method, the terminal equipment receives the reference signal from the network equipment in a frequency hopping mode, waste of reference signal resources can be reduced, the reference signal from the network equipment can be received through frequency hopping for many times, and the receiving bandwidth of the received reference signal is larger.

The disclosure concerns a control method for operating a multi-phase converter with a number N of phases, N being at least three, said converter including a transformer, a primary side circuit which includes primary switch legs with primary switches connected to a primary side of the transformer, and a secondary side circuit which includes secondary switch legs each with at least one secondary switch connected to a secondary side of the transformer, the method including: a boost operation mode including a shorting step of shorting the secondary side circuit by controlling a plurality of secondary switches of separate secondary switch legs to be simultaneously ON, said shorting step is repeated periodically within one switching time period T; and / or a phase-modification operation mode including a phase-reduction step of reducing an operating phase of said converter by controlling all primary switches of at least one primary switch leg to be simultaneously OFF.

The invention discloses a method for modulating two parallel converters based on zero common-mode voltage and zero-sequence circulating current suppression, which comprises the following steps of: firstly, analyzing the influence of 64 switch combinations on zero-sequence circulating current and common-mode voltage, simultaneously considering common-mode voltage elimination and zero-sequence circulating current suppression, and screening out 18 optimal switch combinations; secondly, in order to eliminate the low-frequency zero-sequence circulating current, designing six switch sequence templates which are symmetrical in a quarter period, and limiting the average value of the zero-sequence circulating current of each switch period to be 0; then, on the basis of the sequence template, starting from the angle of zero-sequence circulating current peak value minimization and switching loss optimization, a vector plane is divided into six large sectors, each large sector comprises six sub-sectors, and the optimal switching sequence of each area is obtained; and finally, a modulation wave is calculated for the optimal switching time sequence, a switching action mode is designed, and a driving signal of the switch is obtained. According to the invention, the problems of low-frequency zero-sequence circulating current and large zero-sequence circulating current peak value existing in the existing zero common-mode voltage modulation algorithm are solved.

The invention discloses a heterogeneous device hybrid ANPC converter junction temperature equalization method. The method comprises the following steps: S1, optimizing junction temperatures among ANPC devices; s2, if the maximum junction temperature appears in the hybrid device, entering S3; s3, optimizing the internal junction temperature of the hybrid device; the PWM rotation strategy of the ANPC converter and the hybrid device switch time sequence switching strategy are combined, the junction temperature between devices is relatively balanced by adjusting the switch loss distribution of the converter, the power output capacity of the converter is improved, and it is guaranteed that the converter can operate safely and reliably under different working conditions.

The invention discloses a dynamic comparator and a voltage calibration method thereof, relates to the field of dynamic comparators, and is used for improving the comparison precision of the dynamic comparator in a mode of not sacrificing the power consumption and the efficiency of the dynamic comparator. A kickback noise suppression circuit is connected to a tail current tube of an input geminate transistor to adjust the switching time of a clock signal, a calibration crystal geminate transistor is connected to a regeneration node of the input geminate transistor, and a reference voltage is adjusted through a resistor string DAC to calibrate an offset voltage. The kickback noise is effectively suppressed by adjusting the slew rate of the clock signal of the tail current tube, the calibration speed is increased through the two-stage resistor string DAC, the crystal pair tube is controlled and calibrated by multiplexing the adjusted clock signal, and the calibration precision is improved.

The invention discloses a high-speed fixed-point multiplication circuit. The multiplication circuit is mainly composed of a multiplier coding module, a partial product generation module, a partial product compression module and a traveling wave carry adder module. The multiplier coding module is composed of a radix-4-Booth coding algorithm and an opposite number generation module, and is used for carrying out three-bit block coding on input multiplication data and generating an opposite number of a multiplicand in advance. The partial product generation module generates a plurality of groups of partial products with symbol extension according to the multiplicand coded signal. And the partial product compression module adopts an improved Wallace compression structure to perform layered compression on the partial product. And the traveling wave carry adder module sums the two groups of results output by compression and outputs a multiplication result. According to the invention, multiplication accumulation series can be reduced, the switching times of invalid signals in the circuit can be reduced, and the longest delay path in an operation link can be shortened, so that fixed-point multiplication which is high in speed, low in power consumption and more favorable for a comprehensive tool in structure is realized.

The invention relates to a scale out network backup path fast switching notification system and method, and aims to solve the problem that the existing VRRP / BFD protocol switching time cannot meet the high real-time requirement of an AI server scale out network. The scheme is realized through a collaborative architecture of a CPU (Central Processing Unit), an inspection FPGA (Field Programmable Gate Array) and power supply monitoring: the CPU runs a VRRP / BFD (Bidirectional Forwarding Detection) protocol stack and maintains a state table, and the FPGA is responsible for detecting a power supply fault, a port fault and GPU alarm in real time, and generating and sending a pre-installed message in one main frequency period; and the power supply monitoring module ensures that power supply is maintained for more than or equal to 5ms after sudden power failure through the energy storage capacitor, so that complete transmission of fault messages is ensured. The system has the advantages that the system supports multi-scale out interface redundancy, the end-to-end delay of fault detection and backup path switching is smaller than or equal to 1ms by adopting a low-power-consumption switching chip and independent minimum power domain design, the fault response speed and reliability of an AI server scale out network are remarkably improved, and the system is suitable for guaranteeing the network continuity of a high-density AI training cluster.

A station (STA) includes a memory and a processor, the processor to cause receive, a frame associated with initiating a non-primary channel access (NPCA) operation from an access point (AP) that supports NPCA operation, the frame indicating a NPCA primary channel that the AP and the STA switch to for the NPCA operation. The processor is further to cause switching, at a switch time, from a basis service set (BSS) primary channel to the NPCA primary channel based at least in part on receiving the frame. The processor is further to cause initiating a transmission on the NPCA primary channel based on an enhanced distributed channel access (EDCA) parameters associated with the NPCA primary channel. The processor is further to cause an end of transmission on the NPCA primary channel and to cause switching to the BSS primary channel.

The invention discloses a power consumption mode switching system, a power consumption mode switching method and a system on chip. The system comprises a task core used for generating an entry request of a preset power consumption mode; the power consumption management core is used for configuring a switching time sequence of a preset power consumption mode; the power consumption controller is connected with the task core and the power consumption management core and is used for receiving the entry request or generating an exit request of a preset power consumption mode according to the received wake-up request; the power consumption mode controller is connected with the power consumption controller and is used for executing a switching time sequence according to the entry request or the exit request so as to generate a control signal; and the plurality of hardware control devices are respectively connected with the power consumption mode controller and are used for entering a preset power consumption mode or exiting the preset power consumption mode according to the control signal, and the control types of different hardware control devices are different. The technical problem that the switching effect of the power consumption mode is poor in the prior art is solved.

The invention relates to an intelligent power supply switching method suitable for a power station, and aims at solving the problems that an existing spare power automatic switching device is low in response speed, single in starting condition, incomplete in switching-on logic and the like. According to the invention, parameters such as voltage, frequency, phase and current of the power supply are monitored in real time, and various switching logics such as rapid closing, synchronous capture closing, residual voltage closing and long delay closing are combined, so that rapid and safe switching between the main power supply and the standby power supply is realized. The system supports various triggering modes such as manual starting, protection starting, voltage loss starting, reverse power starting and non-current starting, and can adapt to complex scenes such as single-bus segmentation, single-bus and isolated network operation. Through an embedded hardware platform, a DSP + ARM + CPLD architecture is adopted, the system has efficient data acquisition and logic operation capability, and the switching time can be shortened to be within 10 milliseconds. Meanwhile, multiple safety mechanisms such as overcurrent protection, reverse power protection and decoupling protection are provided, and misoperation and parallel operation risks in the switching process are avoided.

The invention provides a signal conditioning circuit, an analog-to-digital conversion system and a gain adjusting method and device, and belongs to the technical field of analog-to-digital conversion. The signal conditioning circuit comprises a switching module and a plurality of signal conditioning modules, and each signal conditioning module is connected with the switching module. The switching module is used for switching the signal conditioning modules connected with the analog-to-digital converter in the analog-to-digital conversion system according to the switching instruction, so that during each analog-to-digital conversion, only one signal conditioning module is used as a working signal conditioning module to be connected with the analog-to-digital converter; the switching instruction is generated according to a prediction gain gear and a prediction signal; the signal conditioning module is used for acquiring a to-be-converted signal, adjusting the to-be-converted signal to obtain an adjusted signal, and inputting the adjusted signal to the analog-to-digital converter for analog-to-digital conversion. The working signal conditioning module is switched through the switching module, the switching time is shortened, data availability in the sampling process is guaranteed, and therefore the conversion precision is improved.

The invention provides a 2M non-framing double-path protection intelligent switching method and system based on redundancy check, and relates to the technical field of communication, and the method comprises the steps: obtaining double-path 2M non-framing code streams, carrying out the alignment processing, generating a check result through employing cyclic redundancy check, carrying out the statistics of error code feature vectors in a sliding time window, and constructing a link quality track. According to the method, the quality degradation early warning signal is extracted, the stage switching strategy is constructed based on the early warning signal, the switching time sequence is determined in combination with the neural network evaluator, link switching is executed, self-adaptive optimization of the switching strategy is achieved, and the intelligence and reliability of link switching are improved.

The invention belongs to the technical field of motor control, and discloses a control method for switching an open loop to a closed loop of a permanent magnet synchronous motor, which is used for switching the permanent magnet synchronous motor from speed loop open-loop operation to rotating speed current double-closed-loop operation. Calculating an included angle delta between the shafting of the virtual synchronous rotating coordinate system dvirqvir and the shafting of the real rotor synchronous coordinate system dq; and then instantaneous switching of a command value of a current regulator, instantaneous switching of a current space voltage vector, switching of an angle variable used by coordinate transformation, initialization of a previous value of a low-pass filter, initialization of an integral term of the current regulator and initialization of an integral term of a speed regulator are executed in sequence, and open-loop switching and closed-loop switching of the permanent magnet synchronous motor are completed. According to the invention, the switching time is effectively shortened, and the switching stability and universality are improved.