65 results about "Memory systems" patented technology

Example systems and methods for data migration in memory systems are disclosed. One example method includes receiving, by a memory controller of a memory system, a command comprising a first logical address and a second logical address. In response to the command, a correspondence of data to the second logical address is established based on a correspondence of the data to the first logical address. The first logical address is deallocated based on the command.

Methods, systems, and devices for power stabilization for memory systems are described. A memory system may be implemented with a power source that is configured to adjust one or more aspects of its regulation based on an indication associated with a power consumption for one or more operations to be performed by the memory system. For example, a memory system may include a controller configured to determine the power consumption for performing upcoming operations (e.g., based on the quantity of operations and the type of operations), and transmit an indication associated with the power consumption to the power source (e.g., as a proactive or feed-forward control indication). The power source may adjust its regulation based on the indication from the controller, which may include adjusting gains, circuitry, or other regulation configurations or characteristics associated with providing the power for performing the upcoming operations (e.g., at a regulated voltage).

A memory system with adaptive refresh commands is disclosed. In one aspect, a memory system or device that has multiple banks within a channel may receive a per bank command that indicates a first bank to be refreshed and provides additional information about a second bank to be refreshed. In a further exemplary aspect, a quad bank refresh command may be sent that indicates a first bank to be refreshed and provides additional information about second through fourth banks to be refreshed. In a further exemplary aspect, an octa bank refresh command may be sent that indicates a first bank to be refreshed and provides additional information about second through eighth banks to be refreshed. The three new refresh commands allow adjacent or spaced banks to be refreshed.

This disclosure relates to programming voltage management in storage devices and systems. An example method for programming memory cells of a storage device is provided. The method includes increasing the voltage of a first word line of the storage device from a first voltage to a second voltage during a first time period. The method further includes increasing the voltage of the first word line from the second voltage to a target programming voltage during a second time period. The method also includes increasing the voltage of a second word line of the storage device from a third voltage to a fourth voltage. The second word line is adjacent to the first word line. After the voltage of the first word line reaches the voltage of the second word line, the voltage of the second word line increases starting from the third voltage.

Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to debug a memory sub-system. The controller receives, from a host over a first bus, authentication information associated with unlocking the debugging component and, in response to successfully authenticating the host based on the authentication information, unlocks a debugging component. The debugging component receives one or more debug commands from the host via a second bus and transmits, to the host via the second bus, debugging information in response to receiving the one or more debug commands.

Methods, systems, and devices for low-power boot-up for memory systems are described. A memory system may be configured to receive, over a first conductive path of a second communication interface, a first indication to boot-up a memory system and a first communication interface associated with the memory system, wherein the first communication interface includes a plurality of conductive paths; receive, over a second conductive path of the second communication interface, a second indication whether to perform a boot-up operation of the memory system using a low-power mode or a high-power mode based at least in part on receiving the first indication; and boot the memory system according to the low-power mode or the high-power mode based at least in part on receiving the second indication.

Methods, systems, and devices for peak power control of a memory system are described. The method may include operating the memory system according to a first policy for managing power consumed by the memory system. In some examples, the first policy may be based on a ratio between a peak power consumed by the memory system and an average power consumed by the memory system over a duration. Further, the method may include monitoring one or more power characteristics associated with operating the memory system and operating the memory system according to a second policy for managing the power consumed by the memory system based on the one or more power characteristics satisfying a condition. In some examples, operating the memory system according to the second policy may include activating a peak power management (PPM) feature of the memory system.

The invention relates to the technical field of plant disease recognition, and discloses an oriental cherry leaf spot disease recognition method and system based on a deep convolutional network, and the method comprises the steps: building a dual dynamic system mathematical model of plant growth and model evolution, constructing a feature extractor, a progressive knowledge base, a dual-memory system, a concept drift detector and a meta-learning optimizer for sensing the growth stage, and integrating a biotechnology co-adaptation framework to realize long-term cooperation between the oriental cherry leaf spot identification system and the oriental cherry growth cycle; according to the method, long-term cooperation of the identification system and the oriental cherry growth cycle is realized, the problem of contradiction between stability and adaptability of a traditional deep learning method in long-term plant monitoring is solved, the oriental cherry leaf spot identification system can be kept efficient and stable in the application process for many years, and frequent manual intervention and model updating are not needed.

Various embodiments provide for deferring adjustment of a zone in a memory system or sub-system that supports zones. In particular, some embodiments provide for deferred adjustment of a zone based on detection of an error in a block of an unassigned block set, which can be tracked using a counter.

This invention discloses a method, device, electronic device, storage medium, and process for implementing an emotional intelligent agent and its memory system based on a state machine, belonging to the field of artificial intelligence and human-computer interaction technology. The method includes: constructing a multi-dimensional emotional state machine, defining state vectors containing basic and advanced emotions, and combining a natural decay mechanism and an empathy adjustment algorithm to achieve dynamic emotion updates; establishing a hierarchical memory system with emotion binding, binding emotional states as metadata to memory entries, and achieving memory compression, archiving, and enhanced retrieval through a three-level architecture of short-term, medium-term, and long-term combined with importance scoring; adopting a hierarchical streaming response mechanism, splitting the response process into two layers: rapid emotional feedback and substantive content generation, and reducing interaction latency using streaming output and speculative execution; and using emotional states as the core driving source to synchronously control text tone, speech synthesis intonation, and virtual character animation. This invention, by integrating an emotional state machine and a hierarchical memory architecture, enhances the agent's personality continuity and long-term companionship ability, achieving low-latency, multimodal synchronous natural human-computer interaction.

Embodiments of the present disclosure provide a memory device, an operation method thereof, and a memory system. The memory device includes: a memory cell array including a plurality of blocks; and a peripheral circuit coupled to the memory cell array and configured to: apply a plurality of different erasure verification voltages to a selected block among the plurality of blocks after applying a first effective erasure voltage to the selected block; and determine a second effective erasure voltage applied to the selected block according to a plurality of erasure verification results corresponding to the plurality of different erasure verification voltages, where the second effective erasure voltage is greater than the first effective erasure voltage.

The present disclosure relates to program voltage management in memory devices and systems. An example method for programming memory cells of a memory device is provided. The method includes increasing a voltage of a first word line of the memory device from a first voltage to a second voltage in a first time period. The method further includes increasing the voltage of the first word line from the second voltage to a target program voltage in a second time period. The method further includes increasing a voltage of a second word line of the memory device from a third voltage to a fourth voltage. The second word line is adjacent to the first word line. The voltage of the second word line starts to increase from the third voltage after the voltage of the first word line reaches the second.

The invention discloses a memory, a memory control method and a memory system, and belongs to the technical field of storage. The control method comprises the steps that a peripheral circuit receives erasing instructions and records the number of the received erasing instructions, and the erasing instructions are used for indicating the peripheral circuit to erase one storage block in a storage unit array. The peripheral circuit responds to the fact that the number reaches a number threshold value, one storage page is selected from a first storage block of the storage unit array to execute programming processing, the number threshold value is equal to the total number of erasure instructions which need to be received for executing preset times of erasure on all second storage blocks except the first storage block in the storage unit array, and the number threshold value is equal to the total number of erasure instructions which need to be received for executing preset times of erasure on all the second storage blocks except the first storage block in the storage unit array. The number of the storage pages subjected to programming processing in the first storage block is used for indicating the erasing frequency of the second storage block. By adopting the method and the device, the pressure of the memory controller for maintaining the erasing times can be reduced.

The embodiments of the present disclosure disclose a memory system and an operation method thereof, a memory controller, and a memory. The memory system includes a memory. The memory includes a memory cell array and a peripheral circuit coupled to the memory cell array. The memory cell array includes memory cells capable of storing m bits of information, where m is a positive integer greater than 1. The operation method includes the steps of: determining, by the peripheral circuit, a (n+1)th group of page data according to a received prefix command and the received n groups of page data, where n is a positive integer and n+1 is a positive integer less than or equal to m; and determining, by the peripheral circuit, a (n+1)th group of page data according to a received prefix command and the received n groups of page data, where n is a positive integer and n+1 is a positive integer less than or equal to m; n and writing the n groups of the page data and the (n+1)th group of the page data to the memory cell array to generate n different data states.

Methods, systems, and devices for block replacement using combined blocks are described. A memory system may receive a command to perform an access operation on a block of the memory system. The memory system may determine whether a block pool includes a second block configured to replace the block based on a failure to perform the access operation. The memory system may generate a combined block for replacing the block based on determining an absence of the second block in the block pool. The combined block may be generated by combining two half good blocks (HGBs) in a same plane of the memory system as the block. In some cases, a second block pool may be generated and the combined block may be stored to the second block pool. The memory system may select the combined block from the second block pool and replace the block with the combined block.

To provide a memory system for adjusting operation so that power consumption may not exceed supplied power, and an information processing system.SOLUTION: A memory system includes a nonvolatile memory and a controller which controls operation of the nonvolatile memory. The memory system can operate in one of multiple operation modes different in power consumption. The nonvolatile memory stores data indicating relationships between power consumption and the multiple operation modes. The controller reads the data from the nonvolatile memory, and selects at least one of the operation modes.SELECTED DRAWING: Figure 3

The invention relates to an interleaved self-refresh operation in a memory system. A memory system may include a stack of memory dies including an interface memory die coupled with a substrate and at least one memory die stacked on the interface memory die. The interface memory die may receive a self-refresh entry command, and trigger the interface memory die to enable a self-refresh enable command to the at least one memory die. Accordingly, the interface memory die may perform a first internal refresh operation, and the at least one memory die may perform a second internal refresh operation based on an offset relative to the interface memory die. In such examples, the first internal refresh operation may be temporally interleaved with the second internal refresh operation based on the offset.

The invention discloses an operation method of a memory, the memory, a storage system and an electronic system, and belongs to the technical field of storage. The method comprises the steps of applying a target voltage to a first word line within a first voltage adjustment duration, so that the voltage on the first word line is adjusted to the target voltage; applying a target voltage to the second word line within the second voltage adjustment duration so as to adjust the voltage on the second word line to the target voltage; wherein the first voltage adjustment duration is smaller than the second voltage adjustment duration, and the distance between the first word line and the source line of the memory is larger than the distance between the second word line and the source line. According to the technical scheme provided by the invention, power resources can be saved on the basis of ensuring that the voltage on the word line is successfully adjusted to the target voltage, so that the operation performance of the voltage adjustment operation of the word line is improved, and the efficiency of the processes of reading, programming, verification and the like of the voltage adjustment operation is further improved.

Various embodiments provide for deferring adjustment of a zone in a memory system or sub-system that supports zones. In particular, some embodiments provide for deferred adjustment of a zone based on detection of an error in a block of an unassigned block set, which can be tracked using a counter.

The application relates to the technical field of plant disease identification, and discloses a cherry leaf spot disease identification method and system based on a deep convolutional network, wherein the cherry leaf spot disease identification method based on the deep convolutional network comprises the following steps: establishing a double dynamic system mathematical model of plant growth and model evolution, constructing a growth stage perception feature extractor, a progressive knowledge base, a double memory system, a concept drift detector and a meta-learning optimizer, integrating a biological technology co-adaptation framework, and realizing long-term cooperation between a cherry leaf spot disease identification system and a cherry growth cycle; the application realizes long-term cooperation between the identification system and the cherry growth cycle, solves the contradiction between stability and adaptability of a traditional deep learning method in long-term plant monitoring, and enables the cherry leaf spot disease identification system to maintain high efficiency and stability in a multi-year application process without frequent manual intervention and model updating.

A method of operating a memory system includes performing a first read operation with a first read voltage of a first single read stage; determining an actual mode of bit count at the first read voltage of the first single read stage; and in response to a difference between an expected pattern of bit count at the first read voltage of the first single read stage and an actual pattern of the bit count being equal to or below a first threshold, determining that the first read voltage is a first optimal read voltage. The first single read stage of a first page is under a multi-stage architecture.

The present disclosure provides: METHOD FOR OPERATING A MEMORY SYSTEM, A MEMORY SYSTEM, AND A STORAGE MEDIUM This method providing a logical block management table, the logical block management table including a first sequence corresponding to identities of M first logical blocks, the identities of the M first logical blocks being structured as a ring queue, and the allocation status of the M first logical blocks being managed via the logical block management table; Toto Allocating one first logical block whose allocation state is a first state representing an unallocated state to one second logical block among the N second logical blocks according to the order of the identities of the M first logical blocks in the ring queue, where N is an integer greater than M, and updating the allocation state of the first logical block from the first state to a second state representing an allocated state. Toto , including.

Methods, systems, and devices for partial block read level design for a memory system are described. The memory system may store offsets for inner word lines and outer word lines of a partial block for use in read operations. For example, the memory system may read a boundary word line of the partial block using a read voltage configured with a boundary word line offset. Alternatively, the memory system may read an inner word line of the partial block using a read voltage configured with an inner word line offset. The offsets may avoid an error limit for a read operation being exceeded even in the event of a misidentification by the memory system of an inner word line as a boundary word line, of a boundary word line as an inner word line, or both.

This application relates to the field of data security technologies, and in particular, to a storage controller and a control method thereof, a storage system, and a micro controller unit, to resolve a problem of excessively large area overheads caused because a register configured to store permission information is configured in the storage controller. The storage controller includes: a bus parser, configured to parse an operation instruction sent by a primary device by using a bus, to obtain a to-be-performed operation and a target address of the operation; an authentication control circuit, configured to: obtain permission information of a sub-region in which the target address is located from a memory, and determine, based on the permission information, whether permission of the operation meets a requirement; and an interface adapter, configured to send the operation instruction to the memory when the permission of the operation meets the requirement, so that the memory executes the operation instruction.

Example memory systems, methods, and media for aggregating responses from memory systems to mitigate interrupt overhead in hosts coupled to the memory systems are disclosed. One example method includes receiving multiple commands from a host. Multiple responses are sent to the host at a time instant, where each of the responses is generated in a memory system during a time period and responsive to a respective one of the commands.

Methods, systems, and devices for command and address (CA) sampling are described. A memory system may implement a sampler that performs a first comparison of a CA sample with a first reference voltage and a second comparison of a CA sample with a second reference voltage. Such comparisons may be performed at the memory system using a first decision circuit and a second decision circuit. The memory system may determine to activate one of the first decision circuit or the second decision circuit based on a value of a previous CA sample. After activating the respective decision circuit, an output of the decision circuit may be input to a latch circuit, and the latch may determine a logical value of the CA sample. The latch circuit may send the output of the latch circuit as feedback to the first decision circuit and the second decision circuit.

The invention discloses an operation method of a memory, the memory and a memory system, and belongs to the technical field of storage. According to the method, in the process of executing the pre-programming operation on a to-be-erased storage block, if a pause command for pausing the pre-programming operation is received, the pre-programming operation is not immediately paused under the condition that the pre-programming operation is not executed for a certain period of time, but the pre-programming operation is paused when the pre-programming operation is executed for a certain period of time; according to the method, the pre-programming operation is performed to respond to the pause command, so that the response duration of the pause command in the pre-programming operation process is increased, the pause times of the pre-programming operation can be reduced, and the reliability and performance of the memory reduced by multiple pauses of the pre-programming operation can be improved.

Methods, systems, and devices for detecting information modification in a memory system are described. A system may generate a first value, such as a first hash value, from information stored in storage component. The system may then generate a second value, such as a second hash value, from content stored in the storage component. After generating the second value, the system may compare the second value to the first value. The system may then determine the modification status of the information based on the comparison, and implement one or more operations based on the modification status.

In some implementations, a memory system may perform a staggered access operation on a first access line of a first one or more access lines and a second access line of a one or more second access lines, the second access line coupled to the first access line, wherein the staggered access operation comprises a first activation of the first access line during a first duration and a second activation of the second access line during a second duration subsequent to the first duration.