52 results about "Memory systems" patented technology

Methods, systems, and devices for power stabilization for memory systems are described. A memory system may be implemented with a power source that is configured to adjust one or more aspects of its regulation based on an indication associated with a power consumption for one or more operations to be performed by the memory system. For example, a memory system may include a controller configured to determine the power consumption for performing upcoming operations (e.g., based on the quantity of operations and the type of operations), and transmit an indication associated with the power consumption to the power source (e.g., as a proactive or feed-forward control indication). The power source may adjust its regulation based on the indication from the controller, which may include adjusting gains, circuitry, or other regulation configurations or characteristics associated with providing the power for performing the upcoming operations (e.g., at a regulated voltage).

A memory system with adaptive refresh commands is disclosed. In one aspect, a memory system or device that has multiple banks within a channel may receive a per bank command that indicates a first bank to be refreshed and provides additional information about a second bank to be refreshed. In a further exemplary aspect, a quad bank refresh command may be sent that indicates a first bank to be refreshed and provides additional information about second through fourth banks to be refreshed. In a further exemplary aspect, an octa bank refresh command may be sent that indicates a first bank to be refreshed and provides additional information about second through eighth banks to be refreshed. The three new refresh commands allow adjacent or spaced banks to be refreshed.

This disclosure relates to programming voltage management in storage devices and systems. An example method for programming memory cells of a storage device is provided. The method includes increasing the voltage of a first word line of the storage device from a first voltage to a second voltage during a first time period. The method further includes increasing the voltage of the first word line from the second voltage to a target programming voltage during a second time period. The method also includes increasing the voltage of a second word line of the storage device from a third voltage to a fourth voltage. The second word line is adjacent to the first word line. After the voltage of the first word line reaches the voltage of the second word line, the voltage of the second word line increases starting from the third voltage.

Methods, systems, and devices for low-power boot-up for memory systems are described. A memory system may be configured to receive, over a first conductive path of a second communication interface, a first indication to boot-up a memory system and a first communication interface associated with the memory system, wherein the first communication interface includes a plurality of conductive paths; receive, over a second conductive path of the second communication interface, a second indication whether to perform a boot-up operation of the memory system using a low-power mode or a high-power mode based at least in part on receiving the first indication; and boot the memory system according to the low-power mode or the high-power mode based at least in part on receiving the second indication.

Methods, systems, and devices for peak power control of a memory system are described. The method may include operating the memory system according to a first policy for managing power consumed by the memory system. In some examples, the first policy may be based on a ratio between a peak power consumed by the memory system and an average power consumed by the memory system over a duration. Further, the method may include monitoring one or more power characteristics associated with operating the memory system and operating the memory system according to a second policy for managing the power consumed by the memory system based on the one or more power characteristics satisfying a condition. In some examples, operating the memory system according to the second policy may include activating a peak power management (PPM) feature of the memory system.

Various embodiments provide for deferring adjustment of a zone in a memory system or sub-system that supports zones. In particular, some embodiments provide for deferred adjustment of a zone based on detection of an error in a block of an unassigned block set, which can be tracked using a counter.

This invention discloses a method, device, electronic device, storage medium, and process for implementing an emotional intelligent agent and its memory system based on a state machine, belonging to the field of artificial intelligence and human-computer interaction technology. The method includes: constructing a multi-dimensional emotional state machine, defining state vectors containing basic and advanced emotions, and combining a natural decay mechanism and an empathy adjustment algorithm to achieve dynamic emotion updates; establishing a hierarchical memory system with emotion binding, binding emotional states as metadata to memory entries, and achieving memory compression, archiving, and enhanced retrieval through a three-level architecture of short-term, medium-term, and long-term combined with importance scoring; adopting a hierarchical streaming response mechanism, splitting the response process into two layers: rapid emotional feedback and substantive content generation, and reducing interaction latency using streaming output and speculative execution; and using emotional states as the core driving source to synchronously control text tone, speech synthesis intonation, and virtual character animation. This invention, by integrating an emotional state machine and a hierarchical memory architecture, enhances the agent's personality continuity and long-term companionship ability, achieving low-latency, multimodal synchronous natural human-computer interaction.

Embodiments of the present disclosure provide a memory device, an operation method thereof, and a memory system. The memory device includes: a memory cell array including a plurality of blocks; and a peripheral circuit coupled to the memory cell array and configured to: apply a plurality of different erasure verification voltages to a selected block among the plurality of blocks after applying a first effective erasure voltage to the selected block; and determine a second effective erasure voltage applied to the selected block according to a plurality of erasure verification results corresponding to the plurality of different erasure verification voltages, where the second effective erasure voltage is greater than the first effective erasure voltage.

The present disclosure relates to program voltage management in memory devices and systems. An example method for programming memory cells of a memory device is provided. The method includes increasing a voltage of a first word line of the memory device from a first voltage to a second voltage in a first time period. The method further includes increasing the voltage of the first word line from the second voltage to a target program voltage in a second time period. The method further includes increasing a voltage of a second word line of the memory device from a third voltage to a fourth voltage. The second word line is adjacent to the first word line. The voltage of the second word line starts to increase from the third voltage after the voltage of the first word line reaches the second.

The embodiments of the present disclosure disclose a memory system and an operation method thereof, a memory controller, and a memory. The memory system includes a memory. The memory includes a memory cell array and a peripheral circuit coupled to the memory cell array. The memory cell array includes memory cells capable of storing m bits of information, where m is a positive integer greater than 1. The operation method includes the steps of: determining, by the peripheral circuit, a (n+1)th group of page data according to a received prefix command and the received n groups of page data, where n is a positive integer and n+1 is a positive integer less than or equal to m; and determining, by the peripheral circuit, a (n+1)th group of page data according to a received prefix command and the received n groups of page data, where n is a positive integer and n+1 is a positive integer less than or equal to m; n and writing the n groups of the page data and the (n+1)th group of the page data to the memory cell array to generate n different data states.

Methods, systems, and devices for block replacement using combined blocks are described. A memory system may receive a command to perform an access operation on a block of the memory system. The memory system may determine whether a block pool includes a second block configured to replace the block based on a failure to perform the access operation. The memory system may generate a combined block for replacing the block based on determining an absence of the second block in the block pool. The combined block may be generated by combining two half good blocks (HGBs) in a same plane of the memory system as the block. In some cases, a second block pool may be generated and the combined block may be stored to the second block pool. The memory system may select the combined block from the second block pool and replace the block with the combined block.

To provide a memory system for adjusting operation so that power consumption may not exceed supplied power, and an information processing system.SOLUTION: A memory system includes a nonvolatile memory and a controller which controls operation of the nonvolatile memory. The memory system can operate in one of multiple operation modes different in power consumption. The nonvolatile memory stores data indicating relationships between power consumption and the multiple operation modes. The controller reads the data from the nonvolatile memory, and selects at least one of the operation modes.SELECTED DRAWING: Figure 3

The invention relates to an interleaved self-refresh operation in a memory system. A memory system may include a stack of memory dies including an interface memory die coupled with a substrate and at least one memory die stacked on the interface memory die. The interface memory die may receive a self-refresh entry command, and trigger the interface memory die to enable a self-refresh enable command to the at least one memory die. Accordingly, the interface memory die may perform a first internal refresh operation, and the at least one memory die may perform a second internal refresh operation based on an offset relative to the interface memory die. In such examples, the first internal refresh operation may be temporally interleaved with the second internal refresh operation based on the offset.

Various embodiments provide for deferring adjustment of a zone in a memory system or sub-system that supports zones. In particular, some embodiments provide for deferred adjustment of a zone based on detection of an error in a block of an unassigned block set, which can be tracked using a counter.

Methods, systems, and devices for partial block read level design for a memory system are described. The memory system may store offsets for inner word lines and outer word lines of a partial block for use in read operations. For example, the memory system may read a boundary word line of the partial block using a read voltage configured with a boundary word line offset. Alternatively, the memory system may read an inner word line of the partial block using a read voltage configured with an inner word line offset. The offsets may avoid an error limit for a read operation being exceeded even in the event of a misidentification by the memory system of an inner word line as a boundary word line, of a boundary word line as an inner word line, or both.

This application relates to the field of data security technologies, and in particular, to a storage controller and a control method thereof, a storage system, and a micro controller unit, to resolve a problem of excessively large area overheads caused because a register configured to store permission information is configured in the storage controller. The storage controller includes: a bus parser, configured to parse an operation instruction sent by a primary device by using a bus, to obtain a to-be-performed operation and a target address of the operation; an authentication control circuit, configured to: obtain permission information of a sub-region in which the target address is located from a memory, and determine, based on the permission information, whether permission of the operation meets a requirement; and an interface adapter, configured to send the operation instruction to the memory when the permission of the operation meets the requirement, so that the memory executes the operation instruction.

Methods, systems, and devices for command and address (CA) sampling are described. A memory system may implement a sampler that performs a first comparison of a CA sample with a first reference voltage and a second comparison of a CA sample with a second reference voltage. Such comparisons may be performed at the memory system using a first decision circuit and a second decision circuit. The memory system may determine to activate one of the first decision circuit or the second decision circuit based on a value of a previous CA sample. After activating the respective decision circuit, an output of the decision circuit may be input to a latch circuit, and the latch may determine a logical value of the CA sample. The latch circuit may send the output of the latch circuit as feedback to the first decision circuit and the second decision circuit.

The invention discloses an operation method of a memory, the memory and a memory system, and belongs to the technical field of storage. According to the method, in the process of executing the pre-programming operation on a to-be-erased storage block, if a pause command for pausing the pre-programming operation is received, the pre-programming operation is not immediately paused under the condition that the pre-programming operation is not executed for a certain period of time, but the pre-programming operation is paused when the pre-programming operation is executed for a certain period of time; according to the method, the pre-programming operation is performed to respond to the pause command, so that the response duration of the pause command in the pre-programming operation process is increased, the pause times of the pre-programming operation can be reduced, and the reliability and performance of the memory reduced by multiple pauses of the pre-programming operation can be improved.

In some implementations, a memory system may perform a staggered access operation on a first access line of a first one or more access lines and a second access line of a one or more second access lines, the second access line coupled to the first access line, wherein the staggered access operation comprises a first activation of the first access line during a first duration and a second activation of the second access line during a second duration subsequent to the first duration.

This application provides a three-dimensional storage device and its manufacturing method and storage system. The three-dimensional storage device includes: a stacked structure having a stacking direction and a first extending direction perpendicular to the stacking direction; an isolation pillar extending in the stacked structure along the stacking direction; and a first gate line slot structure penetrating the stacked structure along the stacking direction and extending along the first extending direction, including a plurality of sub-gate line slot structures spaced apart along the first extending direction, wherein a portion of the sub-gate line slot structures extends into the isolation pillar.

Methods, systems, and devices for latency reduction of boot procedures for memory systems are described. A memory system may receive a first command to perform a first reset of one or more components as part of a first phase of a boot procedure of a host system. The memory system may initiate an initialization process of a second phase of the boot procedure upon determining whether the value of a flag has been set from a first value to a second value. Upon completing the initialization process, the flag may be set to the first value. Parameters corresponding to the characteristics of the memory system may be communicated to the host system based on receiving a second command. The memory system may perform a configuration operation of a logical-to-physical mapping concurrently with communicating the parameters with the host system.

A memory system with adaptive refresh commands is disclosed. In one aspect, a memory system or device that has multiple banks within a channel may receive a per bank command that indicates a first bank to be refreshed and provides additional information about a second bank to be refreshed. In a further exemplary aspect, a quad bank refresh command may be sent that indicates a first bank to be refreshed and provides additional information about second through fourth banks to be refreshed. In a further exemplary aspect, an octa bank refresh command may be sent that indicates a first bank to be refreshed and provides additional information about second through eighth banks to be refreshed. The three new refresh commands allow adjacent or spaced banks to be refreshed.

The invention discloses a hierarchical memory self-adaptive forgetting control system and method for a guest room service robot, and relates to the technical field of intelligent service robots. According to the system, a layered memory architecture composed of an instantaneous memory layer, a short-term memory area and a long-term memory area is constructed, and vision, voice and environment data are converted into structured semantic memory units by using multi-modal feature processing, cross-modal alignment and a hybrid coding structure. Short-term memory is calculated through a memory value evaluation function, so that high-value memory is migrated to a long-term memory area; and updating the long-term memory and deleting the low-intensity memory through the memory intensity evaluation function. The system sets semantic retrieval, task association screening and context weighting mechanisms to extract task related memories, and dynamically adjusts a memory value threshold and a forgetting threshold according to an overall memory state through a threshold adaptive adjustment structure. According to the method, semantic expression, effective retention and timely forgetting of the robot in long-term operation can be realized, and the storage efficiency and the task execution performance are improved.

This disclosure provides a memory operation method, a memory, and a memory system, relating to the field of memory technology. The method includes: applying a bias voltage to the bottom select line of a second memory block, including a memory block adjacent to a first memory block, during a first time period to turn on the bottom select transistor of the second memory block; then performing a first erase operation during a second time period after the first time period. This includes providing an erase operating voltage to the source line of the first memory block and setting the bottom select line of the second memory block to a floating state. This reduces the voltage drop caused by the parasitic capacitance of the common source array wall as the word line of the second memory block rises with channel voltage coupling, thereby allowing it to recover to a voltage closer to that before the voltage boost during the discharge phase. This reduces the voltage difference between the word line and the channel of the second memory block after multiple erase cycles, and reduces the loss of the memory's read window margin or the sum of voltage distribution intervals during the erase process.

The invention relates to the technical field of emotional accompanying robot memory systems, in particular to a long-term emotional memory and optimization method and system based on an intelligent agent, and the method mainly comprises the steps of fusion of an over-dynamic attention mechanism and a structural causal model (SCM), realization of deep interaction and fusion of multi-modal emotional features, and realization of long-term emotional memory and optimization of the long-term emotional memory and optimization of the long-term emotional memory and optimization of the long-term emotional memory and optimization of the long-term emotional memory. Based on a Bayesian network decision model of an age-sensitive Bayesian cognitive development stage theory, whether a user enters a new cognitive stage or not is judged, a migration process is triggered, a neural symbol mixed memory management architecture is adopted, the memory weight is dynamically adjusted according to emotional characteristics and causal relationships, and short-term and long-term memories are distinguished. A neural symbol knowledge distillation technology is utilized, and multi-dimensional evaluation indexes are combined, so that seamless migration of emotion memory is realized. By means of the method, the system can continuously adapt to growth changes of the user, and coherent and deep emotion interaction experience is provided.

Programming techniques disclosed herein may be used to recover from potential plane and / or die level failures. The memory system may detect evidence of a plane or die level failure that impacts memory operations performed in a target region of the blocks if a first programming technique is used in the target region. For example, the memory system may note that a significant number of blocks have memory operation failures in the target region. The storage system switches to a second programming technique for programming the target region responsive to detecting evidence of a plane or die level failure. The blocks may be tested for a reliability criterion after programming using the second programming technique in the target region of the block. The second programming technique may overcome the plane or die level failure such that blocks may continue to be used with the second programming technique.

Methods, systems, and devices for detecting information modification in a memory system are described. A system may generate a first value, such as a first hash value, from information stored in storage component. The system may then generate a second value, such as a second hash value, from content stored in the storage component. After generating the second value, the system may compare the second value to the first value. The system may then determine the modification status of the information based on the comparison, and implement one or more operations based on the modification status.

This application relates to temperature tracking for a memory system. A set of temperature ranges and a set of partitions in the memory system can be stored. Each temperature range in the set of temperature ranges can be mapped to one or more corresponding partitions in the set of partitions in the memory system. A command to read a partition in the set of partitions can be received. It can then be determined whether temperature data associated with the set of temperature ranges for the partition indicates that data is written to the partition outside a threshold temperature. Data can then be read from the partition based on whether the determined temperature data associated with the set of temperature ranges indicates that the data is written to the partition outside the threshold temperature.

Example memory systems, methods, and controllers for reducing power consumption in memory systems are disclosed. One example method includes determining, by a controller of a memory system and based on multiple commands received by the memory system during a first period of time, that a condition is met. A frequency or a voltage applied to one or more processors of the controller is reduced by the controller in response to determining that the condition is met.