40 results about "Memory performance" patented technology

The invention relates to the technical field of large models, in particular to a method and system for improving the memory amount of a large model, and the method comprises the steps: deploying a monitoring module in a training or reasoning process, carrying out the statistics of the number of memory errors and the total task amount of each component, and calculating the initial memory performance of the components; based on the performance evaluation result of each component, quantifying the overall initial memory amount of the model as an optimization starting point; utilizing a dynamic sensitivity analysis algorithm to mine the influence degree of each component parameter on the memory performance, and calculating a dynamic sensitivity factor; and in combination with the sensitivity factor, the current parameter state and the memory performance, model parameters are adaptively adjusted through dynamic parameter optimization and an iterative lifting algorithm, an iterative verification mechanism is introduced, and the memory ability of each component and the whole machine is subjected to closed-loop optimization. According to the method, fine quantization and parameter-level dynamic regulation and control on the memory performance of the model are realized, and the memory stability and long-term dependence processing capability of the large model in tasks such as knowledge keeping and context understanding are effectively improved.

The application discloses a memory abnormality early warning method and device based on data mining and a medium, relates to the technical field of memory abnormality early warning, and comprises the following steps: performing semantic element mapping on memory running semantic data, and outputting a semantic state time sequence vector; performing cross-domain time sequence alignment and associated feature extraction on the semantic state time sequence vector and memory performance index data, and outputting memory associated rules; performing cause-effect analysis on the memory performance index data, constructing a graph structure on a cause-effect edge set through a PC algorithm, and outputting a memory index cause-effect graph; performing memory behavior deduction on real-time memory running semantic data according to the memory associated rules, outputting memory abnormality early warning data, performing cause-effect tracing and report integration on the memory abnormality early warning data through the memory index cause-effect graph, and outputting a memory abnormality early warning report. The application realizes interpretable early warning and root cause positioning of memory abnormality through the cooperation of semantic state time sequence vector construction and memory index cause-effect graph generation.

The application provides a memory performance test method and device, a microprocessor architecture and a storage medium, and is applied to the technical field of computers. After obtaining a memory mapping request of a user state program, the method obtains target page table attributes associated with a target file descriptor carried by the memory mapping request and allocates target physical memory. Then, the method configures page table entries of a memory page table according to the target page table attributes, establishes address mapping between the target physical memory and a virtual address space in the memory page table, and finally feeds back address information of the virtual address space to the user state program, so that the user state program performs memory testing based on the obtained address information. The file descriptor is associated with target page table attributes preconfigured by the user state program. By initiating a memory mapping request carrying different file descriptors, virtual address spaces mapped according to different page table attributes can be obtained, the test process is greatly simplified, the flexibility of the test process is improved, and the test efficiency is improved.

The invention discloses a memory abnormity early warning method and device based on data mining and a medium, and relates to the technical field of memory abnormity early warning, and the method comprises the following steps: carrying out semantic element mapping on memory operation semantic data, and outputting a semantic state time sequence vector; performing cross-domain time sequence alignment and associated feature extraction on the semantic state time sequence vector and the memory performance index data, and outputting a memory association rule; performing causal analysis on the memory performance index data, performing graph structure construction on the causal edge set through a PC algorithm, and outputting a memory index causal graph; and performing memory behavior deduction on the real-time memory operation semantic data according to a memory association rule, outputting memory abnormality early warning data, performing causal tracing and report integration on the memory abnormality early warning data through a memory index causal graph, and outputting a memory abnormality early warning report. According to the method, interpretable early warning and root cause positioning of memory anomalies are realized through dual-mechanism cooperation of semantic state time sequence vector construction and memory index cause and effect graph generation.

The embodiment of the application provides a memory voltage processing method and device, a storage medium and an electronic device, relates to the field of computers, and comprises the following steps: acquiring a first standard voltage output by a target power supply chip based on a substrate management controller integrated on a server mainboard, wherein the first standard voltage provides a memory voltage for a group of memory modules of the server; in response to a first triggering operation of a voltage adjustment instruction, transmitting the first standard voltage to a target operating system; determining N preset voltages based on the first standard voltage; performing a memory performance test based on the N preset voltages to obtain a target test result, wherein the target test result comprises N performance indexes corresponding to the N preset voltages; determining a target preset voltage from the N preset voltages based on the N performance indexes; and modifying a power supply voltage output by the target power supply chip from the first standard voltage to the target preset voltage.

The invention relates to a configuration parameter acquisition method and device, a configuration method and device, equipment, a medium and a product. The method comprises the following steps: acquiring multiple access performance indexes under N parameter configuration combinations in each access scene aiming at M access scenes in which a memory controller accesses a memory; for each parameter configuration combination in each access scene, based on a preset performance parameter weight, performing weighted summation on each access performance index to obtain a weighted performance value of the parameter configuration combination in the access scene; for each parameter configuration combination, based on a preset access scene weight, performing weighted summation on the weighted performance values under all the access scenes to obtain a comprehensive scene weighted value of the parameter configuration combination; and obtaining the optimal configuration parameters of the memory controller according to the comprehensive scene weighted values of all the parameter configuration combinations. The memory performance optimization method can solve the problems that an existing memory performance optimization method is high in subjectivity and cannot achieve global optimization.

The invention provides a decorative RGB assembly using a memory slot and a memory module. The decorative RGB assembly using the memory slot comprises a mainboard, a lamp group strip and a control unit, a plurality of slots which are parallel to one another are formed in the main board, and the lamp bank strip is detachably inserted into at least one slot; the lamp set strip is provided with a lamp set, and the control unit is connected with the lamp set and used for turning on the lamp set or adjusting the working state of the lamp set based on a control instruction. A plurality of first pins are arranged on the lamp group strips, and the lamp group strips are connected with the communication bus through the first pins to realize information interaction. According to the configuration, the decoration RGB assembly using the memory slot can be matched with a memory bank in pairs on the basis of not influencing the performance and the capacity of the memory, the decoration RGB assembly is inserted into the vacant memory slot, better attractiveness is provided, meanwhile, the decoration cost can be further reduced, and the decoration effect is improved. And the practicability of the decorative RGB component using the memory slot is improved.

This invention discloses a native parallel data packing method for 64-bit CPUs, belonging to the field of computer data representation and processing technology. This method packs eight 8-bit raw data columns into a standard 64-bit register, with each data column including 6 data bits and 2 carry bits. The raw data is expanded into a 64-bit data column through a bit extension step, and then packed into the 64-bit register using bit manipulation instructions to form 64-bit packed data. Inline functions are used to achieve zero function call overhead. The compiler automatically optimizes and generates efficient machine code, requiring no SIMD instruction set support. A lookup table method is used to achieve zero computational overhead packing; the lookup table contains 4096 entries. 64-byte cache row alignment is used to improve cache hit rate. Compared to traditional methods, packing and unpacking overhead is reduced by 6.6 times, from 11.3 ms to 1.7 ms. L1 cache hit rate is increased from 65% to 95%, memory access latency is reduced from 45 cycles to 12 cycles, and memory performance is improved by 3.75 times.

This invention provides a memory performance matching method, a memory storage device, and a memory control circuit unit. The method includes: receiving a performance matching command from a host system; adjusting the operating settings of the memory storage device in response to the performance matching command to match the performance requirements of the memory storage device with those of the host system; and interacting with the host system based on the adjusted operating settings. This improves the operational performance of the memory storage device and / or avoids compatibility issues between the memory storage device and the host system after it leaves the factory.

A memory includes a local control circuitry that manages scrub transactions using a set of sense amplifiers separate from those used for access (read and write) transactions. The local control circuitry interrupts scrub transactions to prioritize access requests, thereby offering improved memory performance. The local control circuitry also divides scrub transactions into phases and periods based on whether the scrub transaction requires access to bitlines used for read and write access. This division allows the local control circuitry to interleave and interrupt scrub transactions with access transactions in a manner that minimizes access interference.

The invention provides a game deep learning training method and system based on adaptive strategy adjustment, and belongs to the technical field of cognitive function training. Comprising the steps of 1, collecting operation data in a game process in real time, and constructing an operation data set; 2, constructing a machine learning model, inputting the processed operation data set into the machine learning model for analysis, and predicting the current cognitive state of the ith patient; step 3, constructing an event memory performance coefficient, an attention performance coefficient and an execution performance coefficient of the ith patient in the jth game, and constructing an event comprehensive cognitive ability coefficient of the ith patient in the jth game; and step 4, establishing a scoring unit. According to the method, the current cognitive state of the patient can be accurately predicted, the training difficulty of the game can be adjusted according to the training performance of the patient, and the cognitive impairment degree of the patient can be accurately recognized.

The invention provides a memory array and equipment with the same, the memory array comprises a plurality of 2T1R structures, each 2T1R structure comprises a first transistor, a first memory unit and a second transistor, the first end of the first transistor is connected with the first end of the first memory unit and the second end of the second transistor; the grid electrodes of the first transistors and the grid electrodes of the second transistors of the plurality of 2T1R structures in the same row are connected with the same word line; the second ends of the first memory units of the plurality of 2T1R structures located in the same column are connected with the same bit line, and the second ends of the first transistors and the first ends of the second transistors of the plurality of 2T1R structures located in the same column are connected with the same source line, so that the driving current is improved, the memory performance is improved, and the area of the memory device is reduced.

Methods, systems, and devices for single level cell write buffer extension control are described. A host device may indicate a delay to be observed between write operations to a memory system. The memory system may perform random read operations or read operations for garbage collection during these delays, which allow the memory system to allocate space for a write buffer, such as a single-level cell (SLC) write buffer, even when performing a large quantity of write commands as part of a sequential write command. Additionally, by allocating space for the write buffer, the memory system may be able to keep writing to memory cells in accordance with the first write operation type, such as an SLC type, for longer periods of time, which may improve the write speeds and decrease an overall latency associated with sequential write operations.

Embodiments herein disclose configurations of metal layers of an interconnect structure that can improve memory performance, such as static random access memory (SRAM) memory performance, and / or logic performance. For example, embodiments herein place bitlines in a metal one (M1) layer, which is the lowest metallization level of the interconnect structure of a memory cell, to minimize bitline capacitance, and configure the bitlines as the widest metal lines of the M1 layer to minimize bitline resistance. In some embodiments, the interconnect structure has a dual wordline structure to reduce wordline resistance. In some embodiments, the interconnect structure has a dual voltage line structure to reduce voltage line resistance. In some embodiments, steps are added to the wordlines and / or voltage lines to reduce their respective resistances. In some embodiments, via shapes of the interconnect structure are configured to reduce resistance of the interconnect structure. Embodiments of the invention also relate to integrated circuit structures and methods for forming a multi-layer interconnect structure of a memory.

The invention discloses a memory access performance evaluation method and device, equipment and a medium, and relates to the technical field of memory access performance tests.The memory access performance evaluation method comprises the steps that a preset memory random read-write code and a preset non-alignment test code are run on a to-be-tested server to obtain the three-level cache capacity of the to-be-tested server; setting the six-time three-level cache capacity as the memory data capacity of the memory of the to-be-tested server, running the preset pressure test source code, and performing a cyclic memory test on the memory of the server; verifying whether the memory data capacity supports memory reading and writing or not and verifying whether the memory reading and writing are correct or not to obtain a corresponding verification result; and outputting a memory performance test result based on the verification result. According to the method, the random read-write and data non-alignment read-write mode is operated on the to-be-tested server, and the memory access condition in a real scene can be effectively simulated through a specific test process and data processing, so that the to-be-tested server can obtain more accurate and comprehensive memory performance evaluation.

The invention provides an English vocabulary cognition training method and system based on an interval repetition memory method, and relates to the technical field of language cognition training, abnormal value elimination and normalization preprocessing are performed on collected data, a memory intensity coefficient is calculated, a memory intensity level is judged, and a final review interval is generated in combination with a vocabulary basic interval and a special adjustment rule; each layer is matched with a differentiated multi-modal training task, and the vocabulary adding proportion, cognitive layer dynamic switching and fatigue relieving links in the training process are controlled. According to the method, multi-dimensional data such as learning duration, memory performance and vocabulary difficulty and dynamic review intervals are fused, compared with fixed period review, the one-week memory retention rate of vocabularies is increased to 85%, the two-week memory retention rate reaches 72%, the long-term memory effect is remarkably enhanced, and the problem that multi-dimensional data such as intervals, non-fused reaction time and cognitive states are adjusted only based on correct rate is solved. And personalized and efficient vocabulary cognition training requirements cannot be met.

This application discloses a method and device for evaluating server performance levels, relating to the field of server technology. The method includes: performing performance testing on an accelerator card to obtain an accelerator card performance evaluation value; performing multi-type communication tests on multiple interconnect types corresponding to each device to obtain communication performance values; performing memory performance tests on the video memory unit to obtain memory performance values; testing the inference process and expert partitioning performance of the model deployed on the server to obtain a first separation fitness value and a second separation fitness value for the server; determining the server's total evaluation value based on the accelerator card performance evaluation value, communication performance value, memory performance value, first separation fitness value, second separation fitness value, and corresponding target weight values; and determining the server's target performance level from multiple performance levels based on the total evaluation value, thereby improving the accuracy of server performance level evaluation.

The invention belongs to the technical field of memory performance testing, and particularly relates to a high-performance benchmark testing system and method for UFS equipment, testing equipment and a storage medium, and the high-performance benchmark testing system for the UFS equipment can accurately and stably measure the performance limit of the UFS equipment. Due to the fact that the test system is executed in a kernel mode, an uninterrupted pure IO polling engine model is adopted, and a software lock on an IO path is eliminated, the software stack expenditure is reduced to the maximum extent, performance data very close to the physical limit of a UFS storage hardware subsystem can be measured, and the precision of a test result is remarkably higher than that of a traditional test method; a strict environment locking mechanism is executed through the test environment management module, a highly consistent test environment is created, external interference is eliminated, and a test result has extremely high stability and repeatability.

This application relates to an adaptive memory system. The described devices and methods control the voltage or temperature of a memory domain to balance memory performance and energy usage. In some aspects, an adaptive controller monitors memory performance metrics of a host processor corresponding to commands made to a memory domain of a memory system, the memory domain including a memory domain operating at a low temperature. Based on the memory performance metrics, the adaptive controller can determine a memory performance requirement, such as a latency requirement or a bandwidth requirement, of the host processor for the memory domain. The adaptive controller can use the determined performance requirement to alter the voltage or temperature of the memory domain to achieve memory access performance tailored to meet the requirement of the host processor. By doing so, the adaptive controller can manage various settings of the memory domain to address short-term or long-term changes in memory performance requirements.

The invention relates to the field of image processing, and discloses a three-dimensional image processing system for laser scanning, which comprises a point cloud acquisition module, a coordinate mapping module, a storage alignment module and a feature extraction module, and is characterized in that the coordinate mapping module quantizes point cloud coordinates according to voxel scales and generates logic address tags; a storage alignment module calls a hardware cache line alignment width value as an address offset step length, and distributes physical storage pages for point clouds with different characteristics according to reflection intensity distribution; according to the invention, a pseudo shared path between sampling point data blocks is cut off by using an address isolation mechanism, so that a processor is ensured to maintain a continuous access state, the effective bandwidth utilization rate of a memory bus is effectively improved, and the memory performance is improved. And the real-time dynamic matching of the storage access capability and the hardware access demand is ensured.

Methods, systems, and devices for single level cell write buffer extension control are described. A host device may indicate a delay to be observed between write operations to a memory system. The memory system may perform random read operations or read operations for garbage collection during these delays, which allow the memory system to allocate space for a write buffer, such as a single-level cell (SLC) write buffer, even when performing a large quantity of write commands as part of a sequential write command. Additionally, by allocating space for the write buffer, the memory system may be able to keep writing to memory cells in accordance with the first write operation type, such as an SLC type, for longer periods of time, which may improve the write speeds and decrease an overall latency associated with sequential write operations.

The present disclosure relates to improved memory performance during program suspend protocol. Systems and methods including a processing device operatively coupled to a memory device are disclosed. The processing device performs operations including receiving a sequence of read commands from a memory subsystem controller, retrieving first data by executing a first read command of a set of read commands, storing the first data in a first portion of a cache of the memory device, in response to determining that the memory device is in a suspend state, determining whether a first address range specified by the first read command overlaps with a second address range specified by a second read command of the set of read commands, in response to determining that the first address range does not overlap with the second address range, retrieving second data by executing the second read command and storing the second data in a second portion of the cache, transferring the first data and the second data to the controller.

This disclosure relates to a method, apparatus, computer-readable storage medium, and electronic device for determining memory power consumption, and pertains to the field of integrated circuit technology. The method for determining memory power consumption includes: receiving a memory control command; controlling an analog memory to enter different operating stages according to the memory control command; acquiring the original current variation curves of the analog memory in different operating stages; determining a target time period corresponding to a target operating stage according to the timing of the memory control command; extracting a stage current variation curve corresponding to the target operating stage from the original current variation curves according to the target time period to obtain a target current variation curve; selecting target performance parameters from a memory performance parameter table according to the target operating stage; and determining the memory power consumption based on the target performance parameters and the target current variation curve. This disclosure provides a method for determining memory power consumption.

This application relates to a method and apparatus for testing memory performance degradation. The method includes: monitoring user processes of a cloud host and a host machine, and terminating user processes when the user process load exceeds a first threshold, so that the cloud host and the host machine are in an idle state; repeatedly executing a first file, and sequentially executing a synchronization command and a cache clearing command after each execution of the first file to release slab objects and page caches of the cloud host; obtaining environment variables to limit the number of parallel threads and CPU affinity of the host machine; obtaining a control group to limit the memory usage of user processes on the host machine; repeatedly executing a first command, and sequentially executing a synchronization command and a cache clearing command after each execution of the first command to release slab objects and page caches of the host machine; statistically analyzing the execution results of the first file and the first command, and calculating the average memory bandwidth of the cloud host and the host machine; and calculating the memory performance degradation ratio of the cloud host based on the average memory bandwidth of the cloud host and the host machine.

The application relates to the technical field of large models, in particular to a method and system for improving the memory capacity of a large model, which deploys a monitoring module in the training or reasoning process, counts the memory error number and total task quantity of each component, and calculates the initial memory performance of the component; based on the performance evaluation result of each component, the initial memory capacity of the whole model is quantified as the optimization starting point; the influence degree of each component parameter on the memory performance is mined by using a dynamic sensitivity analysis algorithm, and a dynamic sensitivity factor is calculated; the model parameters are adaptively adjusted by combining the sensitivity factor, the current parameter state and the memory performance through a dynamic parameter optimization and iteration improvement algorithm, and an iteration verification mechanism is introduced to optimize the memory capacity of each component and the whole machine in a closed loop. The method realizes fine quantification and parameter-level dynamic regulation of the memory performance of the model, effectively improves the memory stability and long-term dependence processing capacity of the large model in knowledge retention, context understanding and other tasks.

Methods and apparatus for dynamically adjusting performance of partitioned memory. In one embodiment, the method includes receiving one or more configuration requests for the memory device, determining whether to grant the one or more configuration requests for the memory device, in response to the determining, implementing the one or more configuration requests within the memory device and operating the memory device in accordance with the implementing. The adjusting of the performance for the partitioned memory includes one or more of enabling / disabling refresh operations, altering a refresh rate for the partitioned memory, enabling / disabling error correcting code (ECC) circuitry for the partitioned memory, and / or altering a memory cell architecture for the partitioned memory. Systems and applications that may benefit from the dynamic adjustment of performance are also disclosed.

Systems, methods, and apparatus related to a memory system that manages an interface for a volatile memory device and a non-volatile memory device to control memory system power. In one approach, a controller evaluates a demand on memory performance. If the demand of a current computation task needed by the host is high, a DRAM device is powered-up to meet the demand. Otherwise, if the non-volatile memory device is adequate to meet the demand, the DRAM memory is partially or fully-powered down to save power. In another approach, a task performed for a host device uses one or more resources of a first memory device (e.g., DRAM). A performance capability of a second memory device (e.g., NVRAM) is determined. A controller of the memory system determines whether the performance capability of the second memory device is adequate to service the task. In response to determining that the performance capability is adequate, the controller changes a mode of operation of the memory system so that one or more resources of the second memory device are used to service the task.

The invention belongs to the field of probiotic functional food, and relates to lactobacillus gasseri BDUP and application thereof in improving or enhancing learning ability, multi-dimensional memory and / or attention. The Lactobacillus gasseri BDUP can promote nerve cells to secrete a plurality of neurotransmitters, can significantly improve short-term memory, long-term memory, spatial memory and other multi-dimensional memory-related behavior expressions in model organisms and normal adult mice, and also can up-regulate the expression levels of brain-derived neurotrophic factors and synaptic-related proteins in hippocampus tissues. After the BDUP is ingested, the learning efficiency, the attention level and the memory performance of student groups, adult mental workers and old people are remarkably improved. Through multi-level system verification of cells, model organisms, animals and people, the comprehensive enhancement effect of the lactobacillus gasseri BDUP on learning ability and multi-dimensional memory in a normal physiological state is comprehensively disclosed, and a new technical scheme is provided for development of cognitive support food.

The invention discloses a computing task management method and computing equipment. The method comprises the step of executing the following operations for the ith calculation stage in M calculation stages of a calculation task, wherein the ith calculation stage is any one of the M calculation stages. The management component obtains calculation feature information of the ith calculation stage based on a calculation subtask needing to be realized in the ith calculation stage; the management component determines a jth calculation core used for executing the ith calculation stage in the N calculation cores based on the calculation feature information of the ith calculation stage, and at least two calculation stages in the M calculation stages need to be executed by different calculation cores; the management component sends control information and executable codes of the calculation tasks to the jth calculation core; and the jth calculation core executes the ith calculation stage based on the control information and the executable code of the calculation task. According to the invention, the memory access performance in the operator execution process can be improved.

The application discloses a memory auxiliary training method based on a voice AI model, which is applied to a flash card learning App. The method is based on the recitation content preset by a user, questions related to the recitation content are obtained or generated by a voice AI model, and the user answers by voice. The AI model processes and analyzes the voice answer of the user, and carries out multi-round dialogue according to the answer result, and guides the user to finally obtain the correct answer. At the same time, the system comprehensively evaluates the performance of the user in the whole question and answer process, and obtains or directly generates the memory degree score of the user by the AI model. The memory degree score is taken as an input to drive the interval repetition memory algorithm (such as the FSRS algorithm) to dynamically adjust the review plan. The method improves the learning interactivity through voice interaction and multi-round questioning, and effectively improves the memory training effect and learning efficiency by combining the memory performance evaluation and the interval repetition algorithm linkage.