94 results about "Memory performance" patented technology

The invention provides a memory performance monitoring method and device, electronic equipment and a storage medium, and relates to the technical field of performance monitoring. The method comprises the following steps: collecting a plurality of pre-selected performance events; dividing the performance events into different signal categories based on the physical signal characteristics corresponding to the performance events; assigning the performance events to a predefined event group; and based on the signal category of each performance event, performing statistical operation corresponding to the signal category on the performance events in the event group. According to the scheme, classification processing of the performance events can be realized, and grouping statistical operation is performed by using the signal categories, so that the accuracy of memory performance monitoring and the resource utilization efficiency are improved.

The invention discloses a memory performance detection method, device and equipment and a memory medium, and relates to the technical field of memory performance detection. Memory with the same capacity of a data path port of a memory box is mapped to an endpoint port, the mapped memory is converted into an extended memory which can be identified by a host node, and then the memory performance of the extended memory is subjected to a consistency test, so that a memory mapping relationship can be quickly and effectively established; according to the embodiment of the invention, the host nodes can schedule the memory capacity required by the host nodes in the memory box, and the inconsistency caused by different mapped memory spaces is eliminated by configuring extended memories with the same capacity for the host nodes, so that the memory performance of the plurality of host nodes tends to be consistent on the premise, and the effectiveness of the consistency test is improved.

Automated memory overclocking is described. In accordance with the described techniques, one or more sets of overclocked memory settings of a memory are automatically selected for performance testing and stability testing of the memory. The one or more sets of the overclocked memory settings are tested for performance of the memory and a performance indication is output for each of the one or more sets of the overclocked memory settings. The one or more sets of the overclocked memory settings are tested for stability of the memory and a stability indication is output for each of the one or more sets of the overclocked memory settings. One of the one or more sets of the overclocked memory settings are selected as optimized overclocked memory settings for the memory.

The invention provides an advanced memory performance monitoring and anomaly detection method, system and device, and relates to the technical field of memory monitoring, and the method comprises the steps: capturing a current memory operation executed by a monitored kernel and corresponding operation data through a memory delay monitoring module based on a kernel tracking point mechanism, the memory delay alarm module is used for judging whether memory delay alarm is performed for a monitored kernel; under the condition that the judgment result is yes, constructing a memory delay diagnosis event corresponding to the monitored kernel based on the operation data through a diagnosis event generation module; and through a diagnosis event distribution module, the memory delay diagnosis event is added to the to-be-processed diagnosis event queue, so that the memory diagnosis framework processes the memory delay diagnosis event contained in the to-be-processed diagnosis event queue, and a performance monitoring and anomaly detection result corresponding to the monitored kernel is obtained. According to the method, the monitoring fine granularity can be remarkably improved, and the false alarm and missing alarm conditions in the performance monitoring and abnormity monitoring process are reduced.

The invention provides an AR (Augmented Reality) adaptive scene memory training system and method based on electroencephalogram neural feedback. The system comprises head display equipment and an EEG (Electroencephalogram) data acquisition module, the data processing and prediction module is used for outputting a memory state prediction result of the current test EEG to the self-adaptive adjustment and feedback module; the self-adaptive adjustment and feedback module is used for judging the memory performance of the user based on the familiarity and recall index in the memory state prediction result of the current test round, determining the required task scene difficulty parameter and the mnemonic strategy according to the memory performance of the user, and finally generating an adjustment instruction according to the task scene difficulty parameter and the mnemonic strategy; and a Unity 3D engine platform. According to the invention, a set of self-adaptive scene memory training system is constructed based on EEG (electroencephalogram) and AR (augmented reality) technologies, and the defects of low ecological efficiency, lack of real-time feedback and difficulty in personalized adjustment of an existing scene memory intervention system are effectively overcome.

The invention provides a front-end memory optimization method and system, electronic equipment and a storage medium. The front-end memory optimization method comprises the steps that in the page initialization stage, multiple pieces of first data needing to be rendered are acquired; determining a label of each piece of rendered first data; the first data of which the label is a first type label is taken as second data, and the first type label is a label for automatically performing event monitoring; and rendering the second data into third data with a second type label according to a preset front-end framework, and displaying the third data on the page, the second type label being a label which does not perform event monitoring. According to the method and the device, the memory performance bottleneck caused by page rendering is solved, such as the problems of large memory usage, page lagging, white screen and long page rendering time.

The invention discloses a garbage collection method, system and device for a multi-core CPU (Central Processing Unit) memory and a medium. The method comprises the following steps: acquiring a request instruction of a host; controlling a protocol layer CPU to apply for a target cache interval according to the request instruction; writing the target data into the target cache interval, and recording the target write-in data volume through the protocol layer CPU; under the condition that the target write-in data volume is greater than or equal to a write-in threshold value, the protocol layer CPU generates a garbage collection trigger signal, garbage target collection time and a target cache interval for stopping application; the garbage collection trigger signal is sent to an FTL layer CPU to start garbage collection and monitor the garbage collection state in real time; and when the garbage recycling state represents that the garbage recycling number is larger than or equal to the garbage target recycling number or the garbage recycling time is larger than or equal to the garbage target recycling time, garbage recycling is quitted. The timeliness and accuracy of garbage collection can be ensured, and the performance of a memory is improved.

A memory includes a local control circuitry that manages refresh transactions using a set of sense amplifiers separate from those used for access (read and write) transactions. The local control circuitry interrupts refresh transactions to prioritize access requests, thereby offering improved memory performance. The local control circuitry also divides refresh transactions into phases and periods based on whether the refresh transaction requires access to bitlines used for read and write access. This division allows the local control circuitry to interleave and interrupt refresh transactions with access transactions in a manner that minimizes access interference.

As part of the erase operation for a memory block, one or more post-erase tests can be incorporated into the erase operation to see whether the block has grown any defects. After erasing a block and verifying the erase, the post-erase tests can be performed on the block. As these test involve biasing the block and performing a sensing operation, these post erase tests come with a time penalty. To reduce the associated time penalty and improve memory performance while incorporating the defect tests into the erase process, when biasing the memory array for the post-erase defect tests different ramp rates can be used. In particular, faster ramp rates for bias levels, such those applied to the word lines of the block, are used for the post-erase tests than are used for the same bias level when performing the standard read, program verify, or read verify operations.

The embodiment of the invention provides a multi-channel differential pressure real-time measurement method and system, through cooperative interaction of a PS end and a PL end, the PS end receives and identifies an instruction of an upper computer, the PL end is responsible for instruction execution, corresponding closed-loop communication logic is formed, and the accuracy and reliability of data are improved. Besides, read-write parallelization is realized, two ports of the memory are controlled to perform independent data read-write through switching of identification values, read-write operations of the first port and the second port are completely separated, throughput is greatly improved, the two ports adopt a write priority mode and an independent address space design, read-write conflict risks are eliminated, and the memory performance is improved. And the number of concurrent detection channels and the detection frequency are improved.

The invention relates to the technical field of large models, in particular to a method and system for improving the memory amount of a large model, and the method comprises the steps: deploying a monitoring module in a training or reasoning process, carrying out the statistics of the number of memory errors and the total task amount of each component, and calculating the initial memory performance of the components; based on the performance evaluation result of each component, quantifying the overall initial memory amount of the model as an optimization starting point; utilizing a dynamic sensitivity analysis algorithm to mine the influence degree of each component parameter on the memory performance, and calculating a dynamic sensitivity factor; and in combination with the sensitivity factor, the current parameter state and the memory performance, model parameters are adaptively adjusted through dynamic parameter optimization and an iterative lifting algorithm, an iterative verification mechanism is introduced, and the memory ability of each component and the whole machine is subjected to closed-loop optimization. According to the method, fine quantization and parameter-level dynamic regulation and control on the memory performance of the model are realized, and the memory stability and long-term dependence processing capability of the large model in tasks such as knowledge keeping and context understanding are effectively improved.

Forming planar resistive memory devices on metal vias that are planed level with the surrounding insulating material may transfer dishing or other surface imperfections in the surface of the metal vias throughout the layers of the memory cell and degrade the performance of the device. A bottom electrode having a "hammerhead" shape may be formed by leaving a top portion of the metal layer over the insulating layer instead of polishing down to the insulating layer. The top portion of the electrode may be oxidized to form the switching layer for the memory cell itself. This hammerhead electrode may have a substantially flat surface on which to form the layers of the planar memory cell, resulting in better memory performance and heat dissipation. When oxidized, the hammerhead electrode also eliminates the metal / metal-oxide interface between the bottom electrode and the switching material.

The application discloses a memory abnormality early warning method and device based on data mining and a medium, relates to the technical field of memory abnormality early warning, and comprises the following steps: performing semantic element mapping on memory running semantic data, and outputting a semantic state time sequence vector; performing cross-domain time sequence alignment and associated feature extraction on the semantic state time sequence vector and memory performance index data, and outputting memory associated rules; performing cause-effect analysis on the memory performance index data, constructing a graph structure on a cause-effect edge set through a PC algorithm, and outputting a memory index cause-effect graph; performing memory behavior deduction on real-time memory running semantic data according to the memory associated rules, outputting memory abnormality early warning data, performing cause-effect tracing and report integration on the memory abnormality early warning data through the memory index cause-effect graph, and outputting a memory abnormality early warning report. The application realizes interpretable early warning and root cause positioning of memory abnormality through the cooperation of semantic state time sequence vector construction and memory index cause-effect graph generation.

The present disclosure relates to the field of integrated circuits and discloses a command generation circuit and memory. The command generation circuit includes a command receiving module and a command decoding module. The command receiving module is configured to receive a first command address signal, a first chip select signal, and a clock signal, and sample and register the first command address signal and the first chip select signal based on the clock signal to obtain a second command address signal and a second chip select signal. The command decoding module is connected to the command receiving module and configured to receive and decode an on-chip termination command based on the second command address signal and the second chip select signal. The on-chip termination command is used to control on-chip termination in a non-target chip when the target chip is performing any one of at least two operations. The present disclosure can simplify circuits, reduce circuit power consumption and occupied area, and thus improve memory performance.

The application relates to the technical field of artificial intelligence chips, and discloses a data processing method and device, a processor and electronic equipment. First, in the case of loading the block data of input data to a thread private register, a first jump step required for rearranging the block data is determined based on the block size of the input data in the first dimension; second, the block data is read by jumping according to the first jump step, and the read input elements are rearranged and loaded into the thread private register, so that the block data is stored in the thread private register in a transposed manner, and the thread direction is mapped on the second dimension, thus obtaining the data basis of convolution-related calculation, and then performing convolution-related calculation based on the transposed data in the thread private register and the weight data in the thread private register, so that repeated data reading in the calculation process is reduced, and the operator is changed from a memory performance bottleneck operation to a calculation performance bottleneck operation.

An embodiment of the present disclosure provides a memory, which includes a buffer unit, and the buffer unit includes multiple sub-buffer units, wherein: the wiring layer of the memory includes at least a first wiring layer and a second wiring layer, and the second wiring layer is located above the first wiring layer, a first type of signal wiring is formed in the first wiring layer, and a second type of signal wiring is formed in the second wiring layer; the multiple sub-buffer units include multiple first sub-buffer units and multiple second sub-buffer units, and the multiple first sub-buffer units are connected to the first type of signal wiring, and the multiple second sub-buffer units are connected to the second type of signal wiring, wherein every two first sub-buffer units are distributed on both sides of a second sub-buffer unit, thereby making the connection of the first type of signal wiring and the second type of signal wiring more convenient and ensuring signal integrity, thereby improving memory performance and saving memory area.

This application provides a method, system, electronic device, and medium for caching codebooks based on vector quantization. The method includes: acquiring a codebook to be processed; sorting the codebook to be processed to obtain a target codebook index; obtaining an index boundary based on the target codebook index and a codebook cache; the codebook cache being a cache for storing the codebook to be processed; comparing the index boundary and the target codebook index to obtain a judgment result; and storing the codebook to be processed in the corresponding cache within the codebook cache based on the judgment result. This application improves memory performance and execution efficiency by placing codebook entries at different locations in the GPU's memory hierarchy based on the codebook's usage frequency, thus solving the problems of low efficiency in shared memory and global memory.

A memory includes a local control circuitry that manages scrub transactions using a set of sense amplifiers separate from those used for access (read and write) transactions. The local control circuitry interrupts scrub transactions to prioritize access requests, thereby offering improved memory performance. The local control circuitry also divides scrub transactions into phases and periods based on whether the scrub transaction requires access to bitlines used for read and write access. This division allows the local control circuitry to interleave and interrupt scrub transactions with access transactions in a manner that minimizes access interference.

The application provides a memory performance test method and device, a microprocessor architecture and a storage medium, and is applied to the technical field of computers. After obtaining a memory mapping request of a user state program, the method obtains target page table attributes associated with a target file descriptor carried by the memory mapping request and allocates target physical memory. Then, the method configures page table entries of a memory page table according to the target page table attributes, establishes address mapping between the target physical memory and a virtual address space in the memory page table, and finally feeds back address information of the virtual address space to the user state program, so that the user state program performs memory testing based on the obtained address information. The file descriptor is associated with target page table attributes preconfigured by the user state program. By initiating a memory mapping request carrying different file descriptors, virtual address spaces mapped according to different page table attributes can be obtained, the test process is greatly simplified, the flexibility of the test process is improved, and the test efficiency is improved.

The invention discloses a memory abnormity early warning method and device based on data mining and a medium, and relates to the technical field of memory abnormity early warning, and the method comprises the following steps: carrying out semantic element mapping on memory operation semantic data, and outputting a semantic state time sequence vector; performing cross-domain time sequence alignment and associated feature extraction on the semantic state time sequence vector and the memory performance index data, and outputting a memory association rule; performing causal analysis on the memory performance index data, performing graph structure construction on the causal edge set through a PC algorithm, and outputting a memory index causal graph; and performing memory behavior deduction on the real-time memory operation semantic data according to a memory association rule, outputting memory abnormality early warning data, performing causal tracing and report integration on the memory abnormality early warning data through a memory index causal graph, and outputting a memory abnormality early warning report. According to the method, interpretable early warning and root cause positioning of memory anomalies are realized through dual-mechanism cooperation of semantic state time sequence vector construction and memory index cause and effect graph generation.

The embodiment of the application provides a memory voltage processing method and device, a storage medium and an electronic device, relates to the field of computers, and comprises the following steps: acquiring a first standard voltage output by a target power supply chip based on a substrate management controller integrated on a server mainboard, wherein the first standard voltage provides a memory voltage for a group of memory modules of the server; in response to a first triggering operation of a voltage adjustment instruction, transmitting the first standard voltage to a target operating system; determining N preset voltages based on the first standard voltage; performing a memory performance test based on the N preset voltages to obtain a target test result, wherein the target test result comprises N performance indexes corresponding to the N preset voltages; determining a target preset voltage from the N preset voltages based on the N performance indexes; and modifying a power supply voltage output by the target power supply chip from the first standard voltage to the target preset voltage.

The invention relates to a configuration parameter acquisition method and device, a configuration method and device, equipment, a medium and a product. The method comprises the following steps: acquiring multiple access performance indexes under N parameter configuration combinations in each access scene aiming at M access scenes in which a memory controller accesses a memory; for each parameter configuration combination in each access scene, based on a preset performance parameter weight, performing weighted summation on each access performance index to obtain a weighted performance value of the parameter configuration combination in the access scene; for each parameter configuration combination, based on a preset access scene weight, performing weighted summation on the weighted performance values under all the access scenes to obtain a comprehensive scene weighted value of the parameter configuration combination; and obtaining the optimal configuration parameters of the memory controller according to the comprehensive scene weighted values of all the parameter configuration combinations. The memory performance optimization method can solve the problems that an existing memory performance optimization method is high in subjectivity and cannot achieve global optimization.

The invention provides a network page memory management method, a network page memory management device and electronic equipment, relates to the technical field of computers, can comprehensively know the running state of a server by collecting multi-dimensional running data in the server, and provides a rich and accurate data basis for subsequent memory performance prediction and health degree evaluation. Feature extraction and analysis are carried out on the operation data to obtain a network page memory performance prediction value, and possible problems such as memory insufficiency and memory leakage of the memory can be predicted in advance, so that corresponding processing is carried out on the server memory according to different memory health degree related data, memory use can be effectively optimized, and the service life of the server is prolonged. And the performance and the stability of the server are improved.

The invention provides a decorative RGB assembly using a memory slot and a memory module. The decorative RGB assembly using the memory slot comprises a mainboard, a lamp group strip and a control unit, a plurality of slots which are parallel to one another are formed in the main board, and the lamp bank strip is detachably inserted into at least one slot; the lamp set strip is provided with a lamp set, and the control unit is connected with the lamp set and used for turning on the lamp set or adjusting the working state of the lamp set based on a control instruction. A plurality of first pins are arranged on the lamp group strips, and the lamp group strips are connected with the communication bus through the first pins to realize information interaction. According to the configuration, the decoration RGB assembly using the memory slot can be matched with a memory bank in pairs on the basis of not influencing the performance and the capacity of the memory, the decoration RGB assembly is inserted into the vacant memory slot, better attractiveness is provided, meanwhile, the decoration cost can be further reduced, and the decoration effect is improved. And the practicability of the decorative RGB component using the memory slot is improved.

The invention provides a three-dimensional memory device, a preparation method thereof and electronic equipment. The three-dimensional memory device comprises a substrate; a plurality of memory cell layers and a plurality of isolation layers; each storage unit layer at least comprises a plurality of storage unit groups, each storage unit group at least comprises a common word line and a plurality of storage units, each storage unit comprises a transistor and a capacitor, and the transistor is a surrounding gate transistor. The three-dimensional stacking technology is introduced, the memory units are stacked in the vertical direction to improve the overall density of the memory, meanwhile, the indium gallium zinc oxide with the wide-band-gap characteristic is used as a channel material to reduce transistor leakage current, so that the data retention time is prolonged, in addition, the structures of the memory units are optimized, and the memory performance is improved. The problem that capacitance signals of a bottom layer device are difficult to read is solved by utilizing a vertical bit line design, meanwhile, the grid control capability is enhanced by combining a surrounding grid transistor structure, the performance of a transistor device is improved, and performance optimization and stability improvement of a memory device are realized.

This invention discloses a native parallel data packing method for 64-bit CPUs, belonging to the field of computer data representation and processing technology. This method packs eight 8-bit raw data columns into a standard 64-bit register, with each data column including 6 data bits and 2 carry bits. The raw data is expanded into a 64-bit data column through a bit extension step, and then packed into the 64-bit register using bit manipulation instructions to form 64-bit packed data. Inline functions are used to achieve zero function call overhead. The compiler automatically optimizes and generates efficient machine code, requiring no SIMD instruction set support. A lookup table method is used to achieve zero computational overhead packing; the lookup table contains 4096 entries. 64-byte cache row alignment is used to improve cache hit rate. Compared to traditional methods, packing and unpacking overhead is reduced by 6.6 times, from 11.3 ms to 1.7 ms. L1 cache hit rate is increased from 65% to 95%, memory access latency is reduced from 45 cycles to 12 cycles, and memory performance is improved by 3.75 times.

The present disclosure relates to a memory and a manufacturing method thereof, and an electronic device. The memory includes a substrate and one or more repeating units and a plurality of word lines arranged on the substrate. The repeating unit includes: two bit lines extending along a first direction and spaced apart, and an isolation layer arranged in the space between the two bit lines; a support layer arranged on the side wall of the bit line away from the isolation layer; the support layer includes a plurality of sub-support portions spaced apart in the first direction, and the space between adjacent sub-support portions constitutes a word line hole; the transistor is located in the word line hole and includes a semiconductor layer surrounding the side wall of the word line and a gate insulating layer arranged between the side wall of the word line and the inner side wall of the semiconductor layer; the outer side wall of the semiconductor layer away from the corresponding bit line is flush with the side wall of the adjacent sub-support portion away from the same bit line. The present disclosure can greatly reduce the difficulty of the subsequent process of removing parasitic transistors, thereby improving memory performance.

This invention provides a memory performance matching method, a memory storage device, and a memory control circuit unit. The method includes: receiving a performance matching command from a host system; adjusting the operating settings of the memory storage device in response to the performance matching command to match the performance requirements of the memory storage device with those of the host system; and interacting with the host system based on the adjusted operating settings. This improves the operational performance of the memory storage device and / or avoids compatibility issues between the memory storage device and the host system after it leaves the factory.

A memory includes a local control circuitry that manages scrub transactions using a set of sense amplifiers separate from those used for access (read and write) transactions. The local control circuitry interrupts scrub transactions to prioritize access requests, thereby offering improved memory performance. The local control circuitry also divides scrub transactions into phases and periods based on whether the scrub transaction requires access to bitlines used for read and write access. This division allows the local control circuitry to interleave and interrupt scrub transactions with access transactions in a manner that minimizes access interference.

The present application provides a method for manufacturing a memory, a memory, and a memory system, the method comprising: forming a stacked layer on a substrate, the stacked layer having a first side close to the substrate and a second side away from the substrate; forming a memory channel hole penetrating the stacked layer and extending into the substrate; removing the substrate; forming a memory channel structure in the memory channel hole from the first side, the memory channel structure comprising a memory function layer and a channel layer, and having a second end close to the second side; removing the memory function layer in the second end and exposing the channel layer in the second end; forming a semiconductor layer on the second side of the stacked layer, the semiconductor layer covering the exposed channel layer, thereby being able to manufacture a highly uniform memory channel structure without damaging the memory channel structure, thereby improving memory performance, and facilitating lowering channel hole manufacturing requirements and reducing process difficulty.