A memory uses multiple threshold levels in a
memory cell that are not a power of two, and further uses a
cell mapping technique wherein the read mapping is only a partial function The domain of read states for a single three-level
memory cell, for example, has three states, but only two of them can be uniquely mapped to a bit. The domain of read states for two three-level
memory cell, for example, has nine states, but only eight of them can be uniquely mapped to three bits. Although the read mapping is only partial, the
voltage margin for the three-level memory cells is larger that the
voltage margin available in the commonly used four-level memory cells. This increased
voltage margin facilitates memory
cell threshold voltage sensing, thereby increasing the reliability of the memory. Memory reliability may be further improved by increasing the voltage margin between the memory
cell 0 state and the 1 state relative to the voltage margin between the 1 state and the 2 state, which more effectively accommodates
charge loss from the 0 state through
electron leakage. Asymmetrical read and program mapping may also be used to improve read reliability in the presence of
ground noise or VCC
noise.