93 results about "Half cycle" patented technology

The invention discloses a single-phase differential Boost inverter voltage zero-crossing compensation method based on a DSP (Digital Signal Processor). According to the method provided by the invention, the single-phase differential Boost inverter works under a discontinuous modulation strategy, and two Boost circuit modules alternately output positive and negative half cycles of alternating current sinusoidal voltage, so that the differential total output is the required alternating current sinusoidal voltage; wherein in the last switching period before the positive-negative half-cycle switching, the bridge arm switch actively turns off the interrupted current so as to eliminate zero crossing point oscillation caused by the residual energy of the inductor after the positive-negative half-cycle zero crossing point; in a first switching period after negative-positive half cycle switching, an initial pulse is widened for eliminating zero crossing point oscillation caused by inductive current mutation after negative-positive half cycle zero crossing.

The invention discloses a self-powered synchronous rectification active bridge, a control method thereof and a power supply system. An active bridge belongs to the technical field of power electronics and comprises a full-bridge rectifying circuit composed of four switching devices, a self-powered circuit taking electricity from an alternating current input end and a control circuit. And the control circuit detects an alternating current input phase, generates a driving signal with dead time, and controls the switching device to be alternately conducted in positive and negative half cycles to realize synchronous rectification. The self-powered circuit is preferably a charge pump, and an external auxiliary power supply is not needed. Through integration of synchronous rectification, self-power supply and intelligent control, the rectification efficiency and the power density are remarkably improved, a traditional rectifier bridge is conveniently and directly replaced through the modular design, and the high-power rectifier bridge can be widely applied to high-power scenes.

A control method and a control circuit for a bidirectional resonant direct-current converter are provided. The control method includes determining a zero-crossing point of a secondary resonant current of the bidirectional resonant direct-current converter, determining, for a switching transistor to be turned off in the secondary circuit within each half cycle of the secondary resonant current, a turn-off start time instant of the switching transistor as an end time instant of a preset delay duration starting from the zero-crossing point; and determining, for a switching transistor to be turned on in the secondary circuit within each half cycle of the secondary resonant current, a turn-on start time instant of the switching transistor as an end time instant of a dead time starting from the turn-off start time instant of the switching transistor complementary to the switching transistor to be turned on.

The application provides an extended dual-port RAM communication device based on a PCIE bus and an implementation method, which communicates with a CPU through a PCIE bus, connects with external equipment through an interface, and realizes dual-port RAM communication between the PCIE bus CPU and the external equipment. The application can work independently or in parallel in a far-end mode and a near-end mode. The extended dual-port RAM communication device based on the PCIE bus supports physical connection with a dual-port RAM communication port of the external equipment through a plurality of optional types of interfaces, and matches the electrical characteristics of the dual-port RAM communication physical port of different external equipment. The extended dual-port RAM communication device based on the PCIE bus generates a square wave signal and transmits the square wave signal to the CPU and the external equipment at both ends of the dual-port RAM communication, so that the CPU and the external equipment respectively perform read and write access to the dual-port RAM in the positive half cycle and the negative half cycle of the square wave signal, and the conflict caused by simultaneous read and write of both parties to the same address unit in the dual-port RAM is avoided.

This invention relates to the field of motherboard programming, and in particular to a motherboard programming control method, device, and system. The method includes, during the programming process, controlling the level changes of the cache state machine and the block addressing state machine to determine whether the two state machines will simultaneously be in a metastable state during state updates. If so, a micropulse is generated and inserted into the oscillation half-cycle, so that the time when the two state machines are simultaneously in a metastable state is staggered from the clock edge before data is written. This avoids data rejection due to the continuous metastable state of the two state machines, effectively ensuring the integrity of data writing and thus guaranteeing the quality of motherboard programming.

A switching control system, including: switch units, configured to separately receive one of alternating currents and couple to a load; a detection unit, configured to detect the alternating currents; and a control unit, configured to, after receiving a switching signal, and in response to detecting that a power supply alternating current and a backup alternating current are in a polarity half cycle and a voltage difference is less than a preset voltage, perform: closing a first turn-on direction of a power supply switch unit; opening a second turn-on direction of a backup switch unit; closing a second turn-on direction of the power supply switch unit; and opening a first turn-on direction of the backup switch unit; where the first turn-on direction is opposite to a direction of the polarity half cycle, and the second turn-on direction is the same as the direction of the polarity half cycle.

The application provides a bootstrap driving control device and a control method. The device comprises a full-bridge circuit and a bootstrap driving circuit. The full-bridge circuit comprises first to fourth MOS transistors and first to fourth diodes. The bootstrap driving circuit comprises a bootstrap driving module, first and second bootstrap capacitors and a fifth diode. The bootstrap driving module is used to load the voltage of the first and second bootstrap capacitors to the gate of the second MOS transistor when the first MOS transistor changes from on to off and the fourth MOS transistor changes from on to off, and is also used to load the first power supply voltage and the voltage of the first bootstrap capacitor to the gate of the first MOS transistor when the second MOS transistor changes from on to off and the third MOS transistor changes from on to off. The bootstrap driving circuit is used to control the third and fourth MOS transistors to be continuously turned on in the respective working half cycles, so as to realize sufficient charging of the bootstrap capacitors, and to realize smooth turning on of the first and second MOS transistors when the full-bridge circuit enters a light load mode.

The application relates to the field of power electronics, and discloses a control method for wide-voltage operation of a CLLC resonant converter. In the CLLC resonant converter, the same-name end of the primary side is connected to the emitter of a switching tube Q1 and the collector of a switching tube Q2, and the different-name end is connected to the emitter of a switching tube Q3 and the collector of a switching tube Q4; the same-name end of the secondary side is connected to the emitter of a switching tube S1 and the collector of a switching tube S2, and the different-name end is connected to the emitter of a switching tube S3 and the collector of a switching tube S4; the method comprises the following steps of O-mode under the PO mode: when being in the positive half cycle, if the output voltage of the secondary side is greater than zero, the switching tube S2 is turned on in advance by a phase difference alpha relative to the end phase of the O-mode; and when being in the negative half cycle, if the output voltage of the secondary side is less than zero, the switching tube S1 is turned on in advance by the phase difference alpha. The method is related to a circuit structure which is simple, can effectively widen the voltage gain range, realizes higher voltage gain at lower loss and cost, is more suitable for wide-range voltage operation, and has higher stability.

A full-bridge series resonant converter includes a full-bridge switch circuit, a transformer, a resonant tank, a sensing circuit, and a processing circuit. The full-bridge switch circuit includes a first switch leg and a second switch leg having a second lower switch. The resonant tank includes a resonant inductor, a magnetizing inductor, and a resonant capacitor. The sensing circuit is coupled between the resonant capacitor and a ground point of a primary side of the transformer for sensing a node voltage between the resonant capacitor and the ground point as a sensing voltage. The processing circuit counts a turned-on time of the second lower switch as a first half-cycle time based on the sensing voltage, and duplicates the first half-cycle time as a second half-cycle time for controlling the full-bridge switch circuit.

A method for controlled switching of a switching device is described. In one example, a rate of decrease of a first dielectric strength (RDDS) value and a second RDDS value is determined. Once determined, the first RDDS value is compared to an absolute peak value of a gap voltage. If the first RDDS value is less than the absolute peak value of any one of a plurality of half cycles of the gap voltage, switching of the switching device at a second time can be performed. To this end, the second time is an offset relative to a first time such that the absolute peak value of the gap voltage does not intersect a range defined by the first RDDS value and the second RDDS value.

Disclosed are a method and apparatus for synchronous switching of multiple-input demodulation comparators. The method includes receiving line signals by a plurality of combined multiple-input comparator demodulation circuits, each combined multiple-input comparator demodulation circuit receiving the line signals according to a corresponding input arrangement related to a corresponding subchannel vector of a plurality of mutually orthogonal subchannel vectors, the line signals including a superposition of a set of baseband symbols and a set of carrier-modulated symbols; generating a set of baseband subchannel outputs by combining the set of line signals according to the corresponding input arrangement; obtaining a phase-adjusted demodulation signal related to the set of carrier-modulated symbols; and generating a set of demodulated subchannel outputs by combining the set of line signals according to the corresponding input arrangement and according to the phase-adjusted demodulation signal, the phase-adjusted demodulation signal configured to constructively combine a first half cycle and a second half cycle of the carrier-modulated signals and destructively cancel the set of baseband symbols.

The present disclosure relates to load control devices with overcurrent protection circuitry. A load control device for controlling power delivered from an alternating current power source to a power load can include a controllably conductive device, a control circuit, and an overcurrent protection circuit configured to be disabled when the controllably conductive device is non-conductive. The control circuit can be configured to control the controllably conductive device to be non-conductive at the beginning of each half cycle of the AC power source and to be conductive during each half cycle at a firing time (e.g., using forward phase control dimming techniques). The overcurrent protection circuit can be configured to render the controllably conductive device non-conductive when an overcurrent condition occurs in the controllably conductive device. The overcurrent protection circuit can be disabled when the controllably conductive device is non-conductive and enabled after the firing time at which the controllably conductive device is rendered conductive during each half cycle.

The application belongs to the technical field of inverter control, and provides an inverter circuit control method, an inverter device and an energy storage equipment. The second lower switch tube is controlled to be kept on in the rising stage of the positive half cycle of the output waveform of the voltage output signal, and is kept off in other stages of the whole cycle. The second upper switch tube is controlled to be kept on in the falling stage of the negative half cycle of the output waveform, and is kept off in other stages of the whole cycle. When it is detected that the output waveform enters the rising stage of the positive half cycle or the negative half cycle, the first upper switch tube is controlled to be on or off, and the first lower switch tube is kept off. When it is detected that the output waveform enters the falling stage of the positive half cycle or the negative half cycle, the first lower switch tube is controlled to be on or off, and the first upper switch tube is kept off. The embodiments of the application improve the switching control logic of the first bridge arm and the second bridge arm, and reduce the loss of the inverter circuit under no load.

The invention specifically relates to a dual three-phase permanent magnet synchronous motor winding fault diagnosis and positioning method, and belongs to the technical field of motor fault diagnosis. Comprising the following steps: firstly, collecting armature current and carrying out clark conversion to obtain current components of planes of two sets of windings, calculating a current difference value of the corresponding component, extracting a half-cycle effective value as a fault diagnosis characteristic, and calculating a phase angle of a current vector as a fault positioning characteristic; the method provided by the invention can diagnose whether the winding has a fault on line and determine the type and position of the fault. The method disclosed by the invention is of great significance for improving the operation reliability and the maintenance convenience of the dual three-phase permanent magnet synchronous motor.

Embodiments of the invention generally relate to a semiconductor device. According to one embodiment, a semiconductor device includes a first element region, a second element region, and an intermediate region between the first element region and the second element region. The silicon carbide layer in the intermediate region includes: a silicon carbide region extending in a first direction and disposed repeatedly at a first period in a second direction perpendicular to the first direction; and other silicon carbide regions that are offset from the silicon carbide region by a half cycle of the first cycle, extend in the first direction, and are disposed repeatedly in the second direction by the first cycle.

The application relates to a non-full-phase power supply line comprehensive protection method, system, device and medium, characterized in that: when it is determined that traction power supply line protection at a transformer substation side has started, current and voltage information of two phases at the transformer substation side is collected; a fault element starting moment is recorded, a plurality of maximum sampling values in the former half cycle and a plurality of maximum sampling values corresponding to the latter half cycle before the moment are extracted; whether the traction power supply line at the transformer substation side appears a ground fault or a phase-to-phase fault is judged according to the current and voltage information, the extracted maximum sampling values and a first criterion, a second criterion and a voltage auxiliary criterion which are constructed in advance, and whether protection export is determined, and the application can be widely applied in the field of power supply lines.

The application belongs to the technical field of converter control, and provides a control method of a multi-phase interleaved inverter circuit, a power conversion device and an energy storage device. When it is detected that an output waveform of a voltage output signal of the multi-phase interleaved inverter circuit enters a positive half cycle, a lower switch tube of a current conversion bridge arm is controlled to be kept conductive in the positive half cycle. When it is detected that the output waveform enters a negative half cycle, an upper switch tube of the current conversion bridge arm is controlled to be kept conductive in the negative half cycle. When it is detected that the output waveform enters a rising stage of the positive half cycle, the upper switch tube of the power conversion bridge arm is controlled to be conductive or non-conductive, and the lower switch tube of the power conversion bridge arm is controlled to be non-conductive. When it is detected that the output waveform enters a falling stage of the negative half cycle, the lower switch tube of the power conversion bridge arm is controlled to be conductive or non-conductive, and the upper switch tube of the power conversion bridge arm is controlled to be non-conductive. The application reduces the loss of the multi-phase interleaved inverter circuit under no load by improving the switching control logic of the alternating current bridge arm and the power conversion bridge arm.

This invention provides a method, system, device, and medium for real-time identification and estimation of motor inductance parameters, belonging to the field of motor control technology. The method includes: determining a high-frequency approximation model of a permanent magnet synchronous motor (PMSM) in a target coordinate system, corresponding to the fundamental frequency and high frequency, using mechanistic analysis; injecting a high-frequency orthogonal square wave voltage signal into the PMSM and using the high-frequency approximation model combined with numerical calculations to obtain the current characteristic information of the PMSM under the high-frequency orthogonal square wave voltage signal; obtaining the inductance solution equation based on the current characteristic information using a half-cycle voltage equation subtraction strategy; and using the inductance solution equation to perform real-time identification and estimation of the motor inductance parameters of the PMSM to obtain the motor inductance estimation result.

The invention discloses a half-cycle time sequence repairing method and system of a circuit delay locked storage device. The method comprises the following steps: detecting whether installation time violation or holding time violation exists in the digital circuit design or not; when the time sequence violation exists and cannot be conventionally repaired, verifying whether the time sequence margin of the violation path meets a calling condition or not; if yes, part of clock cycle time is called through the barrier-free passing characteristic of the circuit delay lock storage device in the high-level stationary circuit period, and half-cycle cycle time calling repair based on the circuit delay lock storage device is carried out on a violation path, specifically, for installation time violation, an end device is replaced; for holding time violation, a reverse trigger device is inserted. Through the half-cycle period time calling and differentiation strategy, the technical bottleneck of a traditional method is broken through, and a final solution is provided for time sequence violation which cannot be repaired by a conventional method in an extreme design environment.

The application discloses a circuit control method and device, a storage medium and an electronic device. The method comprises the following steps: obtaining a phase lag angle and a resonance frequency of equivalent impedance; obtaining a theoretical conduction duration based on the phase lag angle and the resonance frequency; obtaining a load voltage, a power supply voltage, a transformation ratio and an actual conduction duration; when the load voltage is less than a target voltage, reducing the actual conduction duration by a unit duration to obtain a first conduction duration; determining a target conduction duration based on the first conduction duration and the theoretical conduction duration; when the load voltage is greater than a preset voltage, increasing the actual conduction duration by a unit duration to obtain a second conduction duration; determining the target conduction duration based on the second conduction duration and a half-cycle duration; and controlling a working state of a switch tube in a target circuit by using the target conduction duration. By using the application, the charging feedback phenomenon of the target circuit is controlled, so that the target circuit can still work in a high-gain state during charging and discharging, and the working performance of the target circuit is improved.

The invention discloses a junction temperature complementary modulation method suitable for a heterogeneous device hybrid ANPC converter, based on a hybrid device replacement type 3L-ANPC converter, the junction temperature complementary modulation method comprises outer tubes S1 and S4, inner tubes S2 and S3 and clamping tubes S5 and S6, the inner tubes S2 and S3 and the clamping tubes S5 and S6 are all hybrid devices, and the junction temperature complementary modulation method comprises the following steps: S1, when loss is concentrated on the inner tubes, the inner tubes S2 and S3 and the clamping tubes S5 and S6 are mixed devices; if the temperature difference between the Si IGBT and the SiC MOSFET in the hybrid device is greater than the threshold value, the switching sequence of the inner tubes S2 and S3 is adjusted from the first switching-on and then switching-off of the MOSFET to the first switching-on and then switching-off and the middle switching-off of the MOSFET; s2, analyzing the working mode of each current tube, and when the junction temperature of the current time sequence switch is concentrated on the diode of the inner tube, constructing a modulation strategy for canceling the use of a double-clamping branch to conduct the current in a zero state; and S3, implementing the modulation strategy constructed in the S2, and if the temperature of the Si IGBT of the modulated inner tube is still lower than that of the SiC MOSFET, conducting the inner tube S2 and the inner tube S3 in the half cycle only by the Si IGBT, and keeping the SiC MOSFET normally closed.

Embodiments of this disclosure relate to a control method and system for preventing reverse current in the rectifier of a switching converter. A method for controlling synchronous rectifier transistors in a switching converter includes: sensing the drain-to-source voltage across each synchronous rectifier transistor during each switching half-cycle of the switching converter; calculating, for each synchronous rectifier transistor, an average of the sensed drain-to-source voltages over N previous switching half-cycles; and sensing a load current transient in the switching converter based on the sensed drain-to-source voltage for each synchronous rectifier transistor and the calculated average of the sensed drain-to-source voltages for each synchronous rectifier transistor over N previous switching half-cycles.

The invention provides a high-resistance fault detection method based on a waveform harmonic distortion rate, and belongs to the field of power system power distribution network relay protection. Bus zero-sequence voltage is monitored through a mutual inductor, when bus zero-sequence voltage u0 is detected to be larger than Ku times of rated phase voltage UN, zero-sequence current signals of all feeder lines are detected, and the zero-sequence current signals of all the feeder lines are obtained through fast Fourier transform; the zero-sequence current signal of the line is filtered, and finally, the zero-sequence current distortion rate of each feeder line in the first half period and the second period after the small resistor is put is calculated, and the zero-sequence current distortion rate is used as a fault criterion. According to the method, only the zero-sequence current needs to be collected, data collection is convenient, weak fault signals during high-resistance faults can be effectively highlighted, and reliable detection of the high-resistance faults of the flexible grounding system is achieved.

The application discloses a continuous mode bridgeless power factor correction circuit and a control method thereof, which comprises an alternating voltage source AC, a diode D1, a diode D2, a main switch Q1, a main switch Q2, an output capacitor C1, a positive half cycle control circuit and a negative half cycle control circuit. In the application, the freewheeling diode is reversely biased before the main switch is turned on, and the current is transferred to the control circuit auxiliary super-fast diode branch. The body diode of the freewheeling diode has no reverse current when the main switch is turned on, and can work at high frequency. Through proper dead zone setting, the freewheeling diode can realize zero voltage switching. The control circuit only works for a short time, the control method is simple, the average power is small, and the cost is low.

The invention discloses a motor stall detection system and method, and relates to the technical field of motor control, and the system comprises a preset register group which is used for storing a preset number of continuous electrical half cycles; wherein the preset number of continuous electrical half cycles comprise the latest electrical half cycle; the calculation circuit is connected with the preset register block and is used for calculating an electrical cycle detection value according to all electrical half cycles in the preset register block; the stall fault judgment circuit is connected with the calculation circuit and is used for determining that the operation condition of the motor to be detected is a motor stall state when the electrical cycle detection value is greater than or equal to a stall threshold value; according to the method, the counter electromotive force between the rising current quadrant and the falling current quadrant can be compared through electrical cycle detection, so that the stall state of the motor is rapidly and conveniently detected, and the detection cost and the operation complexity are reduced; and the motor stall detection can be realized by adopting a digital circuit, the occupied area is small, and the cost is low.

This invention provides a power factor correction circuit that can suppress the surge voltage generated between the drain and source of a switching element during the first switching of each half-cycle. [Solution] The power factor correction circuit 1 comprises a high-frequency leg 11 connected to the AC voltage Vin via an inductor L, and a commercial leg 12 directly connected to the AC voltage Vin. The power factor correction circuit 1 includes a discharge circuit 13 for discharging the output capacitance Coss of the commercial leg 12. The power factor correction circuit 1 discharges the output capacitance Coss by the discharge circuit 13 during the dead time at the start of the half-cycle, and then turns on the commercial leg 12 before the high-frequency leg 11.

The invention discloses a base resistance temperature compensation band-gap reference source circuit with chopping modulation, which is provided with a starting circuit, a biasing circuit, a chopping operational amplifier circuit and a band-gap core circuit, the chopping operational amplifier circuit performs superposition processing on a first input signal and an offset voltage of the operational amplifier in a first level half cycle of the chopping clock to obtain a first output signal, and performs superposition processing on the chopping operational amplifier circuit and the offset voltage of the operational amplifier in a second level half cycle of the chopping clock to obtain a second output signal; the band-gap core circuit receives a first output signal and a second output signal to output corresponding reference voltage, the operational amplifier with chopping modulation is introduced to improve the stability of the output voltage, the base temperature compensation resistor is introduced to reduce the temperature characteristic of the reference voltage, the resistance value of the base temperature compensation resistor is small, the circuit area increase is small, and the power consumption is low. And the requirement of a high-precision integrated circuit is met.

Provided are a voltage modulation method and a three-level inverter, belonging to the field of inverter control technologies. The voltage modulation method is applied to a three-level inverter circuit including a neutral line relay. The voltage modulation method includes: determining a desired output voltage for each phase of the three-level inverter circuit; obtaining, in response to the neutral line relay being in an on state, a positive half-bus voltage and a negative half-bus voltage in the three-level inverter circuit; determining, based on the positive half-bus voltage and the desired output voltage, a first switching duty cycle during a positive half-cycle; determining, based on the negative half-bus voltage and the desired output voltage, a second switching duty cycle during a negative half-cycle; and driving, based on the first switching duty cycle and the second switching duty cycle, the three-level inverter circuit to output the desired output voltage.

The application discloses a kind of detection methods of alternating side power grid voltage midpoint and related components, it is related to electrical detection field, between the first fire line of inverter and N line, unidirectional conduction first discharge module is set, when the connection of N line and electric load is disconnected, first discharge module positive conduction, since the phase voltage between first fire line and N line is alternating current, only half cycle phase voltage can pass through unidirectional conduction first discharge module, so that the arithmetic mean of first phase voltage between first fire line and N line in preset number of voltage periods will change.Therefore, when detecting that the arithmetic mean of first phase voltage in preset number of voltage periods exceeds preset rated threshold, it can be determined that voltage midpoint is not reliably connected, without higher measurement accuracy, more easily detect the change of phase voltage, can more accurately determine whether voltage midpoint is reliably connected, simple to implement, higher reliability.

The invention relates to a method, a device and a medium for controlling a converter unit of a vehicle. The converter unit includes a power interface, a motor interface, at least one H-bridge, and at least one snubber capacitor. The H-bridge and the at least one snubber capacitor are electrically interposed between the power interface and the motor interface. A switch is disposed on each branch of the H-bridge. The method includes closing a pair of switches for supplying current to the motor interface during a first predetermined time span. The method further includes, during a second predetermined time span and after the predetermined latency, closing the pair of switches to supply an induced current to the motor interface. The first predetermined time span and the second predetermined time span are associated with the same current supply half cycle. In addition, the present disclosure relates to a data processing device, a computer program, and a computer-readable storage medium.