167 results about "Half cycle" patented technology

The invention discloses a quantum phase-locked detection method based on entanglement enhancement, and the method comprises the steps: encoding quantum bits in a ground state and an excited state, and preparing the quantum bits into an initialized quantum state; loading a periodic multi-pulse sequence to act on the quantum bits; and loading a carrier pulse resonating with the ground state and the excited state, detecting the final quantum state of the quantum bit, and comparing curves of each component of the measurement density matrix and the theoretical density matrix changing along with the pulse time interval of the periodic multi-pulse sequence to obtain the half cycle and the amplitude of the sine wave to be measured. According to the method, measurement noise under the condition that the rotation angle and the detuning error exist can be effectively restrained, high measurement precision is kept under the condition that the rotation angle and the detuning error exist, and the robustness enables the method to be more reliable in practical application.

The invention discloses a single-phase differential Boost inverter voltage zero-crossing compensation method based on a DSP (Digital Signal Processor). According to the method provided by the invention, the single-phase differential Boost inverter works under a discontinuous modulation strategy, and two Boost circuit modules alternately output positive and negative half cycles of alternating current sinusoidal voltage, so that the differential total output is the required alternating current sinusoidal voltage; wherein in the last switching period before the positive-negative half-cycle switching, the bridge arm switch actively turns off the interrupted current so as to eliminate zero crossing point oscillation caused by the residual energy of the inductor after the positive-negative half-cycle zero crossing point; in a first switching period after negative-positive half cycle switching, an initial pulse is widened for eliminating zero crossing point oscillation caused by inductive current mutation after negative-positive half cycle zero crossing.

The embodiment of the invention discloses a current sampling calibration method, electronic equipment and a storage medium. The method comprises the steps of obtaining circulating voltage output by a voltage loop, and judging whether a fluctuation value of the circulating voltage is smaller than a preset fluctuation threshold value or not; when the fluctuation value is smaller than a preset fluctuation threshold value, current loop output values in a preset number of power frequency periods are collected and subjected to filtering processing, and filtering values corresponding to the positive and negative half cycles of the input end are obtained; calculating a difference absolute value of the two filtering values, and judging whether the difference absolute value is greater than a preset calibration threshold; when the absolute value of the difference value is greater than a preset calibration threshold value, selecting one as a reference filtering value, and determining a correction coefficient according to the size relation of the two filtering values; and taking the reference filtering value and the adjustment filtering value processed by the correction coefficient as filtering values of corresponding half cycles according to the level of the polarity signal. By means of the mode, sampling gain deviation of the mutual inductor can be eliminated through self-correction, and performance indexes such as total harmonic distortion and power factors can be improved.

Systems and methods are disclosed for reduced-power serial data links. A clock-forwarded serial link carries a clock lane and one or more data lanes. Every active serial data cycle is accompanied by its own serial clock edge: a clock delay allows the same clock edge to drive data at a transmitter and latch data at a receiver. Power is saved by idling the serial clock when data is not being transmitted. A valid signal can be omitted, providing a space saving. At the destination, similar clock-forwarding and delay enables a single parallel clock edge to drive data to the boundary of its clock domain, e.g. from a deserializer to a FIFO. The data link exhibits zero-cycle entry and exit. Variations with half- or single-cycle entry or exit are disclosed.

The invention discloses a self-powered synchronous rectification active bridge, a control method thereof and a power supply system. An active bridge belongs to the technical field of power electronics and comprises a full-bridge rectifying circuit composed of four switching devices, a self-powered circuit taking electricity from an alternating current input end and a control circuit. And the control circuit detects an alternating current input phase, generates a driving signal with dead time, and controls the switching device to be alternately conducted in positive and negative half cycles to realize synchronous rectification. The self-powered circuit is preferably a charge pump, and an external auxiliary power supply is not needed. Through integration of synchronous rectification, self-power supply and intelligent control, the rectification efficiency and the power density are remarkably improved, a traditional rectifier bridge is conveniently and directly replaced through the modular design, and the high-power rectifier bridge can be widely applied to high-power scenes.

A control method and a control circuit for a bidirectional resonant direct-current converter are provided. The control method includes determining a zero-crossing point of a secondary resonant current of the bidirectional resonant direct-current converter, determining, for a switching transistor to be turned off in the secondary circuit within each half cycle of the secondary resonant current, a turn-off start time instant of the switching transistor as an end time instant of a preset delay duration starting from the zero-crossing point; and determining, for a switching transistor to be turned on in the secondary circuit within each half cycle of the secondary resonant current, a turn-on start time instant of the switching transistor as an end time instant of a dead time starting from the turn-off start time instant of the switching transistor complementary to the switching transistor to be turned on.

The application discloses a self-interference cancellation device in a full duplex system, which is an independently deployable hardware module connected between a radio frequency transceiver and an antenna, and comprises a switch matrix and a phase shift network unit, a control signal unit, an interface unit and a power supply unit. The switch matrix and the phase shift network unit comprise a radio frequency switch matrix and an inverter composed of a balun transformer; the control signal unit comprises a microcontroller. The microcontroller is configured to output a periodic control signal to synchronously control the radio frequency switch matrix to alternately switch the connection between the two antennas and the transmitting and receiving ports in the first half cycle and the second half cycle in a control period, and synchronously control the phase shift network to introduce a 180-degree fixed phase shift in the second half cycle. Through the above operation, the self-interference signal spectrum is moved away from the baseband, and then low-pass filtering is performed on the latter stage to realize endogenous elimination. The application does not need channel estimation, has simple hardware architecture, low cost and good compatibility, and is convenient for full duplex upgrading of existing equipment.

The application discloses a kind of permanent magnet synchronous motor position sensorless control demodulation methods based on three-branch external tangent demodulation, belong to permanent magnet synchronous motor control field.This method injects random half-cycle square wave high-frequency voltage signal in the estimation synchronous rotating coordinate system, collects three-phase current and extracts high-frequency current component under stationary αβ coordinate system;According to the estimated electrical angle, construct three sets of three-branch external combined current variables, obtain the demodulation quantity corresponding to the position error sine and cosine components by algebraic combination, then obtain the position error signal by external tangent relationship, and estimate rotor position and speed by phase-locked loop.This method does not depend on the strict synchronization multiplication of random square wave demodulation carrier and sampled current, can weaken or avoid the equivalent delay influence of about 1.5Ts caused by digital sampling, improve the position estimation accuracy and robustness under random half-cycle switching condition.

The invention relates to the technical field of capacitance detection circuits, in particular to a capacitance digital conversion circuit based on phase-sensitive integration. The circuit comprises a phase shift circuit unit, a capacitance detection unit, a phase control unit and a digital processing unit. According to the invention, an excitation signal is converted into an excitation signal which is 90 degrees ahead by using a phase shift circuit through a phase shift circuit unit, a capacitance detection unit controls a single-pole double-throw switch S1 to alternately access the excitation signal and an inversion signal to a to-be-detected capacitor Cx and a reference capacitor C0, and a phase control unit utilizes integration-deintegration double stages in an integration stage. Phase signals are converted into high and low levels through a comparator so as to control overturning of a capacitor CF pole plate, the digital processing unit carries out phase sampling counting at 0 degree and 180 degrees, the capacitance value is calculated according to the ratio of the number of integration cycles to the number of deintegration half cycles, the influence of stray capacitance is reduced, and the measurement precision is improved.

The application provides an extended dual-port RAM communication device based on a PCIE bus and an implementation method, which communicates with a CPU through a PCIE bus, connects with external equipment through an interface, and realizes dual-port RAM communication between the PCIE bus CPU and the external equipment. The application can work independently or in parallel in a far-end mode and a near-end mode. The extended dual-port RAM communication device based on the PCIE bus supports physical connection with a dual-port RAM communication port of the external equipment through a plurality of optional types of interfaces, and matches the electrical characteristics of the dual-port RAM communication physical port of different external equipment. The extended dual-port RAM communication device based on the PCIE bus generates a square wave signal and transmits the square wave signal to the CPU and the external equipment at both ends of the dual-port RAM communication, so that the CPU and the external equipment respectively perform read and write access to the dual-port RAM in the positive half cycle and the negative half cycle of the square wave signal, and the conflict caused by simultaneous read and write of both parties to the same address unit in the dual-port RAM is avoided.

This invention relates to the field of motherboard programming, and in particular to a motherboard programming control method, device, and system. The method includes, during the programming process, controlling the level changes of the cache state machine and the block addressing state machine to determine whether the two state machines will simultaneously be in a metastable state during state updates. If so, a micropulse is generated and inserted into the oscillation half-cycle, so that the time when the two state machines are simultaneously in a metastable state is staggered from the clock edge before data is written. This avoids data rejection due to the continuous metastable state of the two state machines, effectively ensuring the integrity of data writing and thus guaranteeing the quality of motherboard programming.

A switching control system, including: switch units, configured to separately receive one of alternating currents and couple to a load; a detection unit, configured to detect the alternating currents; and a control unit, configured to, after receiving a switching signal, and in response to detecting that a power supply alternating current and a backup alternating current are in a polarity half cycle and a voltage difference is less than a preset voltage, perform: closing a first turn-on direction of a power supply switch unit; opening a second turn-on direction of a backup switch unit; closing a second turn-on direction of the power supply switch unit; and opening a first turn-on direction of the backup switch unit; where the first turn-on direction is opposite to a direction of the polarity half cycle, and the second turn-on direction is the same as the direction of the polarity half cycle.

The invention provides a control method and device of a motor system, a medium, a controller and electric equipment.The control method of the motor system comprises the steps that a first voltage signal and a second voltage signal on an alternating current bus are obtained, the first voltage signal is the positive half cycle of an alternating current voltage signal on the alternating current bus, and the second voltage signal is the negative half cycle of the alternating current voltage signal on the alternating current bus; the second voltage signal is a negative half cycle of the AC voltage signal; determining an AC voltage signal based on the first voltage signal and the second voltage signal; inputting the AC voltage signal to a phase-locked loop to obtain a voltage phase corresponding to the AC voltage signal; correcting the current instruction based on the voltage phase to obtain a corrected current instruction; and controlling the motor system based on the corrected current instruction. In the process of determining the voltage phase, an operational amplifier and a differential circuit do not need to be used, so that the control cost of the motor system can be reduced.

The embodiment of the present disclosure discloses a modular bidirectional current conversion system and a zero-crossing control method. The control method comprises: in response to at least part of the first module in the level conversion module switching from processing the first half cycle of the modulation signal to processing the second half cycle of the modulation signal in the first cycle, and at least part of the second module switching from processing the first half cycle of the modulation signal to processing the second half cycle of the modulation signal in the second cycle, outputting a compensation control pulse to at least one target switch in the plurality of switches of the second module in the second cycle to turn on the target switch in the corresponding time length of the compensation control pulse; wherein the second cycle is a modulation cycle located after the first cycle; the positive and negative polarities of the first half cycle and the second half cycle are different; the compensation control pulse at least partially overlaps with the control pulse of the target switch corresponding to the first module in the second cycle; the processing of the modulation signal by the level conversion module comprises: inverter processing and / or rectifier processing.

The application provides a bootstrap driving control device and a control method. The device comprises a full-bridge circuit and a bootstrap driving circuit. The full-bridge circuit comprises first to fourth MOS transistors and first to fourth diodes. The bootstrap driving circuit comprises a bootstrap driving module, first and second bootstrap capacitors and a fifth diode. The bootstrap driving module is used to load the voltage of the first and second bootstrap capacitors to the gate of the second MOS transistor when the first MOS transistor changes from on to off and the fourth MOS transistor changes from on to off, and is also used to load the first power supply voltage and the voltage of the first bootstrap capacitor to the gate of the first MOS transistor when the second MOS transistor changes from on to off and the third MOS transistor changes from on to off. The bootstrap driving circuit is used to control the third and fourth MOS transistors to be continuously turned on in the respective working half cycles, so as to realize sufficient charging of the bootstrap capacitors, and to realize smooth turning on of the first and second MOS transistors when the full-bridge circuit enters a light load mode.

The application relates to the field of power electronics, and discloses a control method for wide-voltage operation of a CLLC resonant converter. In the CLLC resonant converter, the same-name end of the primary side is connected to the emitter of a switching tube Q1 and the collector of a switching tube Q2, and the different-name end is connected to the emitter of a switching tube Q3 and the collector of a switching tube Q4; the same-name end of the secondary side is connected to the emitter of a switching tube S1 and the collector of a switching tube S2, and the different-name end is connected to the emitter of a switching tube S3 and the collector of a switching tube S4; the method comprises the following steps of O-mode under the PO mode: when being in the positive half cycle, if the output voltage of the secondary side is greater than zero, the switching tube S2 is turned on in advance by a phase difference alpha relative to the end phase of the O-mode; and when being in the negative half cycle, if the output voltage of the secondary side is less than zero, the switching tube S1 is turned on in advance by the phase difference alpha. The method is related to a circuit structure which is simple, can effectively widen the voltage gain range, realizes higher voltage gain at lower loss and cost, is more suitable for wide-range voltage operation, and has higher stability.

A full-bridge series resonant converter includes a full-bridge switch circuit, a transformer, a resonant tank, a sensing circuit, and a processing circuit. The full-bridge switch circuit includes a first switch leg and a second switch leg having a second lower switch. The resonant tank includes a resonant inductor, a magnetizing inductor, and a resonant capacitor. The sensing circuit is coupled between the resonant capacitor and a ground point of a primary side of the transformer for sensing a node voltage between the resonant capacitor and the ground point as a sensing voltage. The processing circuit counts a turned-on time of the second lower switch as a first half-cycle time based on the sensing voltage, and duplicates the first half-cycle time as a second half-cycle time for controlling the full-bridge switch circuit.

A method for controlled switching of a switching device is described. In one example, a rate of decrease of a first dielectric strength (RDDS) value and a second RDDS value is determined. Once determined, the first RDDS value is compared to an absolute peak value of a gap voltage. If the first RDDS value is less than the absolute peak value of any one of a plurality of half cycles of the gap voltage, switching of the switching device at a second time can be performed. To this end, the second time is an offset relative to a first time such that the absolute peak value of the gap voltage does not intersect a range defined by the first RDDS value and the second RDDS value.

Disclosed are a method and apparatus for synchronous switching of multiple-input demodulation comparators. The method includes receiving line signals by a plurality of combined multiple-input comparator demodulation circuits, each combined multiple-input comparator demodulation circuit receiving the line signals according to a corresponding input arrangement related to a corresponding subchannel vector of a plurality of mutually orthogonal subchannel vectors, the line signals including a superposition of a set of baseband symbols and a set of carrier-modulated symbols; generating a set of baseband subchannel outputs by combining the set of line signals according to the corresponding input arrangement; obtaining a phase-adjusted demodulation signal related to the set of carrier-modulated symbols; and generating a set of demodulated subchannel outputs by combining the set of line signals according to the corresponding input arrangement and according to the phase-adjusted demodulation signal, the phase-adjusted demodulation signal configured to constructively combine a first half cycle and a second half cycle of the carrier-modulated signals and destructively cancel the set of baseband symbols.

The present disclosure relates to load control devices with overcurrent protection circuitry. A load control device for controlling power delivered from an alternating current power source to a power load can include a controllably conductive device, a control circuit, and an overcurrent protection circuit configured to be disabled when the controllably conductive device is non-conductive. The control circuit can be configured to control the controllably conductive device to be non-conductive at the beginning of each half cycle of the AC power source and to be conductive during each half cycle at a firing time (e.g., using forward phase control dimming techniques). The overcurrent protection circuit can be configured to render the controllably conductive device non-conductive when an overcurrent condition occurs in the controllably conductive device. The overcurrent protection circuit can be disabled when the controllably conductive device is non-conductive and enabled after the firing time at which the controllably conductive device is rendered conductive during each half cycle.

Provided is a control device for an alternating-current rotary electric machine that can reduce noise and suppress an increase in noise of the alternating-current rotary electric machine by taking into account a mechanical resonance period of the alternating-current rotary electric machine, and an electric power steering device. The control device (10) for the alternating-current rotary electric machine switches n zero-phase candidate voltage values in order every switching period (Tv) to calculate a zero-phase voltage value (Vz), turns on and off a switching element based on a voltage command value corrected based on the zero-phase voltage value (Vz), sets a deviation between the zero-phase voltage value (Vz) and a value that is a j multiple of the zero-phase voltage value (Vz) delayed by the switching period (Tv) as a zero-phase time delay deviation value (Vzdif), j is a natural number that minimizes a difference between a half period of a mechanical resonance period (Tm) of the alternating-current rotary electric machine and a j multiple of the switching period (Tv), the n zero-phase candidate voltage values are set in advance so that a root mean square value (Vzdif_rms) of the zero-phase time delay deviation value is smaller than an alternating-current component root mean square value (VzAC_rms) of the zero-phase voltage value.

The invention relates to a method for controlling a 3-stage, T-type pulse-controlled inverter (1). In a first operating mode of the pulse-controlled inverter (1), a current (I) is conducted alternately through a first bridge branch (B1) and a third bridge branch (B3) of the pulse-controlled inverter (1) during a first half-period of an alternating current to be generated by the pulse-controlled inverter (1), and alternately through a second bridge branch (B2) and the third bridge branch (B3) of the pulse-controlled inverter (1) in the second half-period. In a second operating mode of the pulse-controlled inverter (1), the current (I) is alternately conducted through the first bridge branch (B1) and the second bridge branch (B2), wherein the current (I) is conducted through the third bridge branch (B3) for a delay duration (Δt) each time the current conduction is switched between the first bridge branch (B1) and the second bridge branch (B2). The pulse-controlled inverter (1) is operated in the first operating mode if the current intensity value is less than a current threshold value, and otherwise the pulse-controlled inverter (1) is operated in the second operating mode.

Power Converter This description relates to a power converter (400) comprising: a switch (114) including first (114d) and second (114s) conduction terminals for receiving a first alternating voltage (Vds), a first circuit (402) for detecting a minimum value reached by the first voltage at each half-cycle, and for averaging minimum values ​​over several half-cycles, and a second circuit (404) for controlling the switch configured, based on the average of said values, to open the switch when the first voltage is substantially zero. Figure for the abbreviation: Fig. 4

The application belongs to the technical field of inverter control, and provides an inverter circuit control method, an inverter device and an energy storage equipment. The second lower switch tube is controlled to be kept on in the rising stage of the positive half cycle of the output waveform of the voltage output signal, and is kept off in other stages of the whole cycle. The second upper switch tube is controlled to be kept on in the falling stage of the negative half cycle of the output waveform, and is kept off in other stages of the whole cycle. When it is detected that the output waveform enters the rising stage of the positive half cycle or the negative half cycle, the first upper switch tube is controlled to be on or off, and the first lower switch tube is kept off. When it is detected that the output waveform enters the falling stage of the positive half cycle or the negative half cycle, the first lower switch tube is controlled to be on or off, and the first upper switch tube is kept off. The embodiments of the application improve the switching control logic of the first bridge arm and the second bridge arm, and reduce the loss of the inverter circuit under no load.

The invention specifically relates to a dual three-phase permanent magnet synchronous motor winding fault diagnosis and positioning method, and belongs to the technical field of motor fault diagnosis. Comprising the following steps: firstly, collecting armature current and carrying out clark conversion to obtain current components of planes of two sets of windings, calculating a current difference value of the corresponding component, extracting a half-cycle effective value as a fault diagnosis characteristic, and calculating a phase angle of a current vector as a fault positioning characteristic; the method provided by the invention can diagnose whether the winding has a fault on line and determine the type and position of the fault. The method disclosed by the invention is of great significance for improving the operation reliability and the maintenance convenience of the dual three-phase permanent magnet synchronous motor.

Embodiments of the invention generally relate to a semiconductor device. According to one embodiment, a semiconductor device includes a first element region, a second element region, and an intermediate region between the first element region and the second element region. The silicon carbide layer in the intermediate region includes: a silicon carbide region extending in a first direction and disposed repeatedly at a first period in a second direction perpendicular to the first direction; and other silicon carbide regions that are offset from the silicon carbide region by a half cycle of the first cycle, extend in the first direction, and are disposed repeatedly in the second direction by the first cycle.

The application relates to a non-full-phase power supply line comprehensive protection method, system, device and medium, characterized in that: when it is determined that traction power supply line protection at a transformer substation side has started, current and voltage information of two phases at the transformer substation side is collected; a fault element starting moment is recorded, a plurality of maximum sampling values in the former half cycle and a plurality of maximum sampling values corresponding to the latter half cycle before the moment are extracted; whether the traction power supply line at the transformer substation side appears a ground fault or a phase-to-phase fault is judged according to the current and voltage information, the extracted maximum sampling values and a first criterion, a second criterion and a voltage auxiliary criterion which are constructed in advance, and whether protection export is determined, and the application can be widely applied in the field of power supply lines.

The application belongs to the technical field of converter control, and provides a control method of a multi-phase interleaved inverter circuit, a power conversion device and an energy storage device. When it is detected that an output waveform of a voltage output signal of the multi-phase interleaved inverter circuit enters a positive half cycle, a lower switch tube of a current conversion bridge arm is controlled to be kept conductive in the positive half cycle. When it is detected that the output waveform enters a negative half cycle, an upper switch tube of the current conversion bridge arm is controlled to be kept conductive in the negative half cycle. When it is detected that the output waveform enters a rising stage of the positive half cycle, the upper switch tube of the power conversion bridge arm is controlled to be conductive or non-conductive, and the lower switch tube of the power conversion bridge arm is controlled to be non-conductive. When it is detected that the output waveform enters a falling stage of the negative half cycle, the lower switch tube of the power conversion bridge arm is controlled to be conductive or non-conductive, and the upper switch tube of the power conversion bridge arm is controlled to be non-conductive. The application reduces the loss of the multi-phase interleaved inverter circuit under no load by improving the switching control logic of the alternating current bridge arm and the power conversion bridge arm.

This invention provides a method, system, device, and medium for real-time identification and estimation of motor inductance parameters, belonging to the field of motor control technology. The method includes: determining a high-frequency approximation model of a permanent magnet synchronous motor (PMSM) in a target coordinate system, corresponding to the fundamental frequency and high frequency, using mechanistic analysis; injecting a high-frequency orthogonal square wave voltage signal into the PMSM and using the high-frequency approximation model combined with numerical calculations to obtain the current characteristic information of the PMSM under the high-frequency orthogonal square wave voltage signal; obtaining the inductance solution equation based on the current characteristic information using a half-cycle voltage equation subtraction strategy; and using the inductance solution equation to perform real-time identification and estimation of the motor inductance parameters of the PMSM to obtain the motor inductance estimation result.

The invention discloses a half-cycle time sequence repairing method and system of a circuit delay locked storage device. The method comprises the following steps: detecting whether installation time violation or holding time violation exists in the digital circuit design or not; when the time sequence violation exists and cannot be conventionally repaired, verifying whether the time sequence margin of the violation path meets a calling condition or not; if yes, part of clock cycle time is called through the barrier-free passing characteristic of the circuit delay lock storage device in the high-level stationary circuit period, and half-cycle cycle time calling repair based on the circuit delay lock storage device is carried out on a violation path, specifically, for installation time violation, an end device is replaced; for holding time violation, a reverse trigger device is inserted. Through the half-cycle period time calling and differentiation strategy, the technical bottleneck of a traditional method is broken through, and a final solution is provided for time sequence violation which cannot be repaired by a conventional method in an extreme design environment.