240 results about "Gate current" patented technology

The invention discloses an E-mode device nonlinear current model parameter extraction method considering a gate current effect, and relates to the technical field of enhanced device modeling. Comprising the following steps: establishing a nonlinear current model of an E-mode device; extracting parasitic resistance of the transistor; removing the influence of parasitic resistance of the transistor, and calculating gate-source and gate-drain node voltages of an intrinsic region in the nonlinear current model to obtain an intrinsic gate-source voltage and an intrinsic drain-source voltage; extracting intrinsic gate current model parameters; obtaining the drain-source current component of the intrinsic part from the influence of the fused gate current component in the actually measured drain-source current of the transistor; extracting intrinsic nonlinear drain-source current model parameters; and substituting the intrinsic nonlinear drain-source current model parameter value into an intrinsic nonlinear drain-source current model equation for verification. According to the method, gate current component calculation is introduced into a traditional nonlinear current model parameter extraction method, and accurate extraction of intrinsic nonlinear current source parameters is achieved.

The invention relates to a load matching optimization method of a multi-channel gate driver and related equipment thereof. The method comprises the following steps of: acquiring grid current, grid voltage and switching frequency of the multi-channel parallel grid driver to obtain driver load operation data; performing region division processing on the operation space to obtain a safe operation region and a transition region; inputting a first adaptive prediction model for feature extraction to obtain a load balancing prediction result; parallel optimization calculation is carried out on the control strategy to obtain each driving channel control parameter, and each driving channel control parameter comprises a grid driving voltage regulating variable and a driving time sequence regulating variable; performing real-time adjustment on each driving channel control parameter to obtain a load balance adjustment instruction; and performing performance index evaluation calculation to obtain a performance optimization parameter, and updating the first adaptive prediction model to obtain a second adaptive prediction model. According to the invention, through cooperative control of voltage regulation and time sequence compensation, dynamic balance of each channel load is realized.

The invention discloses a cascode cascade type switching device with a cascode current limiting structure. The cascode cascade type switching device comprises a grid end, a source end, a drain end, a low-voltage enhancement type field effect transistor, a high-voltage depletion type field effect transistor and the current limiting structure. The current limiting structure comprises a plurality of common-gate current limiting depletion type field effect transistors and a current limiting resistor. According to the current-limiting depletion type field-effect transistor, when a switching device is turned on, the grid current of the high-voltage depletion type field-effect transistor can be limited through the current-limiting resistor and the series internal resistors of the plurality of current-limiting depletion type field-effect transistors, so that the working reliability of the current-limiting depletion type field-effect transistor and the whole switching device is improved.

The present disclosure concerns a method for measuring a degradation of thermal characteristics of a power module comprising sequences of: - injecting current pulses (Pinj), having a voltage-clamped constant amplitude (IInj), between an emitter and a gate of a power semiconductor of such power module, a duration of said voltage-clamped constant amplitude (Iinj) current pulses (Pinj) being modulated periodically with a modulation frequency (Fmod), said current pulses causing losses modulated with said modulation frequency (Fmod), - measuring a parameter (k.Tj) dependent of a junction temperature (Tj) of such power semiconductor at the beginning of said current pulses, - measuring a phase shift (Δφ) between said modulation frequency (Fmod) and said parameter (k.Tj), said phase shift (Δφ) providing a health indicator for the power module.　

The invention discloses a differential closed-loop negative feedback amplification circuit based on JFET geminate transistors, a low-noise amplifier is used for measuring weak voltage signals, discrete JFET field-effect transistors are used for forming an input stage of the low-noise amplifier, noise interference is reduced, meanwhile, extremely high input impedance can be provided by using the characteristic that the grid current of the JFET field-effect transistors is basically zero, and the differential closed-loop negative feedback amplification circuit based on the JFET geminate transistors is obtained. Mirror current is provided for a pair of JFET field effect transistors in the low-noise amplifier module through a current mirror of the low-noise amplifier, a closed-loop feedback structure of the low-noise amplifier can save one path of input for the JFET field effect transistors, so that the amplifying circuit can realize dual-channel input, and a dual-channel input structure can enable an accessed signal to be a differential signal, so that common-mode interference is effectively inhibited, and the reliability of the amplifying circuit is improved. Overall closed-loop negative feedback can achieve high gain stability, reduce nonlinear distortion, increase input impedance, reduce output impedance and improve the performance of the amplifier, and solves the problem of precise amplification and measurement of weak voltage signals in the aviation electromagnetic field.

The invention belongs to the technical field of vehicle-mounted power supplies, and particularly relates to a driving circuit of a safety switch of a low-voltage battery, a low-voltage battery power supply system and a vehicle power system, and the driving circuit comprises a driving module, a reference end of which is used for being connected with a source electrode of the safety switch and is grounded; one end of the driving resistor is connected with the output end of the driving module, and the other end is connected with the grid of the safety switch; one end of the limiting capacitor is connected with the other end of the driving resistor, and the other end of the limiting capacitor is connected with the drain electrode of the safety switch or grounded; wherein the capacitance value of the limiting capacitor at least exceeds the capacitance value of a parasitic Miller capacitor of the safety switch with the preset first multiplying power, so that the grid current of the safety switch is limited, and the Miller plateau area of the safety switch is prolonged. The Miller platform area of the safety switch is prolonged, so that the drain current iD of the safety switch can charge the inner side capacitor in an approximate constant current mode, triggering of a reverse over-current fault is prevented, and charging of the inner side capacitor cannot be interrupted.

Disclosed is a device that decouples switching speed and gate delay time using an improved voltage-source gate driver. A shunt capacitor and a shunt resistor are connected in series to parallel across gate resistors of a voltage-source gate driver. The shunt capacitor and shunt resistor allow the gate delay and switching speed effect of the gate resistors to be decoupled. The shunt capacitor provides an initial high charge voltage and discharge gate current to reduce gate delay time. The shunt resistor modifies the effective gate resistance, which affects the gate current and the resulting switching speed. Shunt capacitor and shunt resistor values are determined to achieve the desired switching speed control with minimum gate delay time. When multiple power devices are paralleled, a common gate resistor, a shunt resistor and a capacitor combination is used. Each power device is also provided a respective split-gate resistor.

The invention discloses a thyristor type device leakage current monitoring method and circuit and a power electronic device.The method comprises the steps that in response to a system turn-off instruction, a first control signal is sent to a device turn-off module; the device turn-off module is used for conducting a turn-off branch of the thyristor device according to the first control signal; acquiring a leakage current sampling signal from a leakage current monitoring module; the leakage current monitoring module is used for converting the gate current of the thyristor device into a leakage current sampling signal; and generating a leakage current monitoring result based on the leakage current sampling signal. According to the invention, real-time and accurate measurement of the leakage current can be realized on the premise of not influencing system operation.

An array substrate is disclosed. The array substrate includes a semiconductor layer integrated with a PIN photoelectric diode and an active area. The PIN photoelectric diode includes a P-type semiconductor area, an N-type semiconductor area, and an I-type semiconductor area defined between the P-type semiconductor area and the N-type semiconductor area. A gate electric current is introduced at a location corresponding to the I-type semiconductor area, so as to enhance light sensitivity.

In an example, a system includes an amplifier having an output stage configured to provide an output voltage, where the output stage includes a p-channel transistor and an n-channel transistor. The system includes a sense transistor having a gate coupled to a gate of the p-channel transistor, where the sense transistor is configured to sense a current of the p-channel transistor and produce a sense current. The system includes a current mirror coupled to the sense transistor and configured to provide the sense current to a gate of a control transistor, the control transistor having a source coupled to the gate of the p-channel transistor. The system includes a reference current source coupled to the control transistor and configured to provide a reference current. The control transistor is configured to adjust a gate current provided to the p-channel transistor based on comparing the sense current to the reference current.

The invention discloses a superconducting rectifier, a superconducting diode and a manufacturing and control method thereof, and belongs to the technical field of superconducting electronics, the superconducting rectifier comprises more than one superconducting diode, the superconducting diode comprises an insulating substrate and a superconducting nanowire, the superconducting nanowire is provided with a narrowing section, and the narrowing section is provided with a narrow section. The narrowing section is connected with a first gate line and a second gate line, the first gate line and the second gate line are symmetrically arranged, and the first gate line and the second gate line are both perpendicular to the superconducting nanowire. According to the invention, in-situ reconfigurable reversal symmetry destruction can be realized through a nanoscale hot spot controlled by a grid electrode; electrically controlled opening or closing and polarity reversal are realized by adjusting a small grid current without changing a magnetic field; the superconductive rectifier realizes electrically reconfigurable full-wave and half-wave rectification, and paves a way for development of extensible and electrically programmable superconductive electronic devices.

The invention provides a method and a device for identifying a second-class short circuit state of an insulated gate bipolar transistor (IGBT), and relates to the technical field of IGBT devices. The invention aims to timely and accurately judge whether the insulated gate bipolar transistor is in the second-class short circuit state or not. The method comprises the following steps: acquiring an emitter structure of an insulated gate bipolar transistor in a test circuit; if the emitter structure does not have the auxiliary emitter, acquiring a chip gate voltage, a gate side line parasitic inductance, a gate parasitic inductance, an emitter side line parasitic inductance, a common emitter parasitic inductance, a gate current, a collector current and a current from a gate to a collector in a gate driving loop; on the basis of the Kirchhoff's voltage law, grid voltage is determined through the collected parameter data; and if the grid voltage is within the preset short-circuit voltage range, determining that the insulated gate bipolar transistor has a second-class short circuit.

Control circuit for a current source converter having a current generator comprising an inductance (2) and having two or more half bridges each half bridge having an upper leg provided with an upper switching device (11, 13) and a lower leg provided with a lower switching device (12, 14), said upper legs switching devices and said lower legs switching devices being controlled by a controller (40) to provide an overlap between an upper leg turning off and an upper leg turning on switching device and to provide an overlap between a lower leg turning on switching device and a lower leg turning off switching device through gate pull up and gate pull down pulse signals to gate drivers buffers (6) of said switching devices, where said gate driver circuit comprises: - for each switching device (11, 12, 13, 14) a gate current mirroring circuit (5) on a sink branch of the gate driver buffer (6) of such switching device (11, 12, 13, 14) to provide a gate pull down detection signal (Im) from a turning OFF switching device, - for each switching device (11, 12, 13, 14) a gate command connection path to provide a gate command signal (G), at least one logic circuit combining a gate command signal (G) of a first upper or lower leg switching device and a gate pull down signal of a respectively second upper or lower leg switching device to provide a first protection trigger signal (Pr), when said gate command signal of said first upper or lower leg switching device and said gate pull down detection signal of said respective second upper or lower leg switching device correspond to both said first and second upper leg switching devices or both said first and second lower leg switching devices being OFF; converter having such a control circuit.

Provided is a buffer circuit that can realize a wide dynamic range, a reduced area, and a reduced power consumption amount while maintaining low output impedance. The buffer circuit includes a first transistor, a current source, a second transistor, an output terminal, and first and second capacitors. The first transistor has a gate to which an input signal is input. The current source is connected to one terminal of the first transistor. The second transistor is connected to the other terminal of the first transistor. The output terminal is connected to the one terminal or the other terminal of the first transistor. The first and second capacitors are between the current source and the gate of the second transistor. The first transistor, the second transistor, and the first capacitor form a first feedback circuit. The first transistor, the current source, and the second capacitor form a second feedback circuit.

A method and a circuit arrangement for ascertaining a junction temperature of a semiconductor component including an insulated gate. The method includes: recharging an input capacitance of the semiconductor component using a current-controlled gate driver at a predefined first time, and ascertaining a junction temperature of the semiconductor component based on information about a voltage-dependent behavior of the input capacitance of the semiconductor component and based on a level of an internal gate resistor of the semiconductor component at a second time which follows the first time, at which a current build-up phase of a gate current generated by the gate driver for recharging the input capacitance has ended and at which a substantially constant gate current is present.

Control circuit for a current source converter having a current generator comprising an inductance (2) and having two or more half bridges each half bridge having an upper leg provided with an upper switching device (11, 13) and a lower leg provided with a lower switching device (12, 14), said upper legs switching devices and said lower legs switching devices being controlled by a controller (40) to provide an overlap between an upper leg turning off switching device (11, 13) and an upper leg turning on switching device (13, 11) and to provide an overlap between a lower leg turning on switching device (12, 14) and a lower leg turning off switching device (14, 12) through gate pull up and gate pull down pulse signals to gate drivers buffers (6) of said switching devices, said gate driver circuit comprising: - for each upper leg switching device and each lower leg switching device (11, 12, 13, 14) a gate current mirroring circuit (51) on a source branch of the gate driver buffer (6) of said switching device (11, 12, 13, 14) to provide a gate pull down signal (Gpx, Gpy) upon turning OFF of said switching device, said gate pull down signal (Gpx, Gpy) being connected to a control line (Cl) of a gate buffer (6) of a respective further upper leg switching device or further lower leg switching device (11, 12, 13, 14), - for each upper leg switching device and each lower leg switching device (11, 12, 13, 14) a positive gate command connection path (G+) from a positive gate command output of a pre-driver (7) to provide a reset signal (RSTx, RSTy) for a respective further upper leg switching device and lower leg switching device (11, 12, 13, 14) gate pull down signal.

A voltage regulator for outputting a regulated output voltage to an integrated circuit, the voltage regulator comprising: a voltage supply terminal for receiving a supply voltage; an output terminal for outputting the regulated output voltage; a reference terminal; a feedforward Wilson current mirror comprising: a Wilson current mirror with an input current terminal and an output current terminal; an input current source coupled between the supply voltage terminal and the input current terminal of the Wilson current mirror; a feedforward capacitor arranged in parallel with the input current source; and an output current transistor with a conduction channel coupled between the supply voltage terminal and the output current terminal of the Wilson current mirror; and a flipped voltage follower, FVF, comprising: a pass transistor comprising a conduction channel coupled between the supply voltage terminal and the output terminal; a first FVF transistor with a conduction channel coupled between the output voltage and a FVF node; a second FVF transistor with a conduction channel coupled between a gate of the pass transistor and the FVF node; a third FVF transistor with a conduction channel coupled between the supply voltage terminal and the gate of the pass transistor, wherein a gate of the third FVF transistor is coupled to a gate of the output current transistor; and a FVF current source coupled between the FVF node and the reference terminal.

A load control device for controlling power delivered from an AC power source to an electrical load may comprise a thyristor, a gate current path, and a control circuit. The control circuit may be configured to control the gate current path to conduct a pulse of gate current through a gate terminal of the thyristor to render the thyristor conductive at a firing time during a half-cycle of the AC power source. The control circuit may operate in a first gate drive mode in which the control circuit renders the gate current path non-conductive after a pulse time period from the firing time. The control circuit may operate in a second gate drive mode in which the control circuit maintains the gate current path conductive after the pulse time period during the half-cycle.

A method for driving a transistor is described herein. In accordance with one embodiment, method includes modulating an output voltage by cyclically switching a transistor on and off, wherein, in each switching cycle, a gate current having a first current level is supplied to the transistor to switch the transistor on. The method further includes determining a characteristic time parameter of the output voltage (e.g. a rise or a delay time) and determining an error representing the difference between the determined time parameter and a target time in each switching cycle; adjusting the first current level based on the error; and detecting an oscillation of the error. When an oscillation is detected, the adjustment of the first current level is paused until the magnitude of the error exceeds a threshold value in a second number of consecutive switching cycles.

The invention discloses a shield gate field effect transistor for eliminating voltage clamping and a preparation method thereof, the shield gate field effect transistor comprises a shield gate, a control gate and source electrode metal, the shield gate and the control gate are located in a groove, the shield gate comprises a gate body part and an extension part, the gate body part is located below the control gate, the extension part extends upwards from the gate body part, and the source electrode metal is located in the groove. The extension part is led out from two sides of the control gate to the top of the groove, or the extension part is led out from one side of the control gate to the top of the groove; the top of the extension portion is in direct contact with the source metal by configuring a contact hole structure. Compared with an up-and-down structure of a shield grid and a control grid in a traditional SGT, a whole contact hole can be formed in the top of the extending part of the extended shield grid to be in direct contact with source electrode metal, shield grid resistance is eliminated, shield grid current and voltage are avoided, the voltage clamping problem introduced by shielding is eliminated, and the stability of the SGT is improved. Meanwhile, the charge balance effect and electric field distribution of the whole chip are improved, and current concentration is reduced.

To suppress an increase in gate current when a high gate voltage is applied.SOLUTION: A nitride semiconductor device 10 includes: a substrate 12; a nitride semiconductor layer 40 formed on the substrate 12; a gate electrode 24 formed on and in contact with the nitride semiconductor layer 40; and a source electrode 28 and a drain electrode 30 formed on the nitride semiconductor layer 40 and sandwiching the gate electrode 24. At least a part of the gate electrode 24, including a lower surface 24B in contact with the nitride semiconductor layer 40, is composed of a specific metal oxide. The specific metal oxide includes at least one first metal selected from Pd and Pt, at least one second metal selected from Co, Rh, and Cr, and oxygen atoms.SELECTED DRAWING: Figure 2

The invention discloses a rapidly-switched-on insulated gate bipolar transistor and a preparation method thereof, and relates to the technical field of semiconductors, the rapidly-switched-on insulated gate bipolar transistor comprises a gate bonding pad, a gate current amplification unit, a gate bus and a cell, the input end of the gate bonding pad is connected with an external gate driving circuit, and the output end of the gate bonding pad is connected with an external gate driving circuit; the output end of the grid electrode bonding pad is connected with the input end of the grid electrode current amplification unit, the output end of the grid electrode current amplification unit is connected with the input end of the grid electrode bus, the output end of the grid electrode bus is connected with the grid electrode of the cell, and the grid electrode current amplification unit is used for amplifying the grid electrode current output by the grid electrode bonding pad and outputting the amplified grid electrode current. According to the invention, by adding the grid current amplification unit, the grid current can be amplified, and the amplified grid current is used for driving the cell, so that the grid voltage rise rate of the cell is improved, and the purpose of improving the opening speed of the cell in the insulated gate bipolar transistor is achieved.

An electric circuit in which a first switching element and a first diode element are connected in antiparallel to form an upper arm and a second semiconductor element and a second diode element are connected in antiparallel to form a lower arm, and the upper arm and the lower arm are connected in series. A gate current path in one of the upper and lower arms and a reverse recovery path in the other one of the upper and lower arms are disposed close enough and extend at least partially in parallel to each other, so as to generate mutual inductance by the reverse recovery current flowing through the reverse recovery path and the gate current flowing through the gate current path.

The invention discloses a continuous time current comparator capable of outputting maximum current and minimum current. The continuous time current comparator comprises eight groups of cascode current mirrors consisting of NMOS (N-channel Metal Oxide Semiconductor) transistors N1-N20 and PMOS (P-channel Metal Oxide Semiconductor) transistors P1-P8, the drain electrode of the PMOS tube P2 is connected with the drain electrode of the NMOS tube N5 and the drain electrode of the NMOS tube N7 at the same time, the drain electrode of the PMOS tube P6 is connected with the drain electrode of the NMOS tube N11 and the drain electrode of the NMOS tube N13 at the same time, and the drain electrode of the PMOS tube P8 is connected with the drain electrode of the NMOS tube N17; a to-be-compared current Ia is input from the drain electrode of the NMOS transistor N1, and a to-be-compared current Ib is input and then is divided into two paths which respectively flow to the drain electrode of the NMOS transistor N3 and the drain electrode of the NMOS transistor N9; the drain electrode of the NMOS tube N19 outputs the maximum current Imax, and the drain electrode of the NMOS tube N15 outputs the minimum current Imin. After currents Ia and Ib to be compared are input, the maximum current Imax and the minimum current Imin corresponding to the currents Ia and Ib are output through current copying, summation and difference operation of the cascode current mirror, and the maximum current Imax and the minimum current Imin are both continuous analog current signals.

The invention discloses a semiconductor device and an electronic device comprising the same. The semiconductor device comprises a drain electrode, an active layer, a source electrode, a grid electrode and an internal grid electrode current collector, the active layer comprises a substrate, a drift region, a well region and a doped region which are stacked in the direction away from the drain electrode, and the surface, away from the drain electrode, of the active layer extends towards the drift region to form a first groove and a second groove; the source electrode partially extends into the first groove, and the part, extending into the first groove, of the source electrode is insulated from the active layer; the grid electrode at least partially extends into the second groove, and the grid electrode and the active layer are insulated and spaced; the internal gate current collector is arranged on the side, away from the drain electrode, of the active layer, the source electrode and the gate electrode are coupled through the internal gate current collector, and the internal gate current collector has an internal driving potential; wherein the equivalent resistance temperature change coefficient of the source electrode is smaller than the equivalent resistance temperature change coefficient of the grid electrode.

The invention discloses a regulation and control gate current determination method based on a one-way cut-off current gate regulation and control light-emitting device, and the method comprises the steps: applying a first driving signal corresponding to a first gray-scale value between an anode and a cathode, and applying a first gate regulation and control current to a first regulation and control electrode of a one-way cut-off current gate structure; continuously changing the first grid regulation and control current, and collecting first luminous efficiency corresponding to different first grid regulation and control current in real time; in response to matching of the first luminous efficiency and the standard luminous efficiency, determining the corresponding first grid regulation and control current as the standard grid regulation and control current of the first gray-scale value; obtaining standard grid regulation and control current corresponding to a plurality of different gray-scale values; obtaining a first function relation according to the linear relation between different gray-scale values and the corresponding standard grid regulation and control current; and according to the first function relationship, obtaining standard grid regulation and control current corresponding to each gray-scale value of the light-emitting device. According to the invention, standard grid regulation and control signals corresponding to different gray-scale values can be rapidly determined.

A control circuit for a current source converter having a current generator comprising an inductance and having two or more half bridges, each half bridge having an upper leg provided with upper switching devices and a lower leg provided with lower switching devices, the upper leg switching devices and the lower leg switching devices being controlled by a controller to provide overlap between upper leg off switching devices and upper leg on switching devices and to provide overlap between lower leg on switching devices and lower leg off switching devices by gate pull-up and pull-down pulse signals input to gate driver buffers of the switching devices, characterized in that the gate driver circuit comprises: - a gate current mirror circuit for each upper leg switching device and each lower leg switching device, the gate current mirror circuit providing a gate pull-down signal on a source branch of the gate driver buffer of the switching device when the switching device is off, the gate pull-down signal being connected to a control line of a gate buffer of a respective other upper leg switching device or other lower leg switching device, - a positive gate command connection path from a positive gate command output of a pre-driver for each upper leg switching device and each lower leg switching device, the positive gate command connection path providing a reset signal for the gate pull-down signal of the respective other upper leg switching device or respective other lower leg switching device.

The present invention discloses an IGCT gate drive device, electrical equipment, and IGCT gate drive method. The device includes: a detection unit that detects the IGCT gate current and generates an IGCT turn-on signal when the detected IGCT gate current reaches the IGCT's set turn-on current; a control unit that controls the IGCT to turn on based on the IGCT turn-on signal; the detection unit that generates an IGCT turn-on maintenance signal when the detected IGCT gate current continues to be less than the IGCT's set turn-on maintenance current; and the control unit that adjusts the IGCT gate current based on the IGCT turn-on maintenance signal to maintain the IGCT on. This solution can solve the problem of erroneous shutdown caused by the gate current being less than the maintenance current after the IGCT is turned on, thereby preventing the IGCT from erroneously shutting down due to the gate current being less than the maintenance current after the IGCT is turned on.

The present invention discloses a method for determining a control gate current of a light-emitting device based on a unidirectional current-cutoff gate, comprising: applying a first drive signal corresponding to a first grayscale value between an anode and a cathode, and applying a first gate control current to a first control electrode of the unidirectional current-cutoff gate structure; continuously changing the first gate control current, and collecting first luminous efficiencies corresponding to different first gate control currents in real time; in response to the first luminous efficiency matching a standard luminous efficiency, determining the corresponding first gate control current as a standard gate control current of a first grayscale value; obtaining standard gate control currents corresponding to multiple different grayscale values; obtaining a first functional relationship based on a linear relationship between different grayscale values ​​and their corresponding standard gate control currents; and obtaining the standard gate control current corresponding to each grayscale value of the light-emitting device based on the first functional relationship. The present invention can quickly determine the standard gate control signal corresponding to different grayscale values.

Embodiments of the present invention related to a neuromimetic circuit including a transmitter circuit to receive the threshold signal from a superconducting optoelectronic neuron and convert the small current pulse to a voltage pulse sufficient to produce light from a semiconductor diode. This light is the signal used to communicate between neurons in the network. The transmitter circuit in accordance with the present invention includes an amplifier chain that comprises two Josephson junctions, a superconducting thin-film current-gated current amplifier, and a superconducting thin-film current-gated voltage amplifier. The transmitter circuit in accordance with the present invention enable an amplification sequence that allows neuronal firing of about 20 MHz with power density sufficiently low to be cooled with standard 4He cryogenic systems operating at 4.2 K.