157 results about "Gate current" patented technology

The invention discloses an E-mode device nonlinear current model parameter extraction method considering a gate current effect, and relates to the technical field of enhanced device modeling. Comprising the following steps: establishing a nonlinear current model of an E-mode device; extracting parasitic resistance of the transistor; removing the influence of parasitic resistance of the transistor, and calculating gate-source and gate-drain node voltages of an intrinsic region in the nonlinear current model to obtain an intrinsic gate-source voltage and an intrinsic drain-source voltage; extracting intrinsic gate current model parameters; obtaining the drain-source current component of the intrinsic part from the influence of the fused gate current component in the actually measured drain-source current of the transistor; extracting intrinsic nonlinear drain-source current model parameters; and substituting the intrinsic nonlinear drain-source current model parameter value into an intrinsic nonlinear drain-source current model equation for verification. According to the method, gate current component calculation is introduced into a traditional nonlinear current model parameter extraction method, and accurate extraction of intrinsic nonlinear current source parameters is achieved.

The invention belongs to the technical field of vehicle-mounted power supplies, and particularly relates to a driving circuit of a safety switch of a low-voltage battery, a low-voltage battery power supply system and a vehicle power system, and the driving circuit comprises a driving module, a reference end of which is used for being connected with a source electrode of the safety switch and is grounded; one end of the driving resistor is connected with the output end of the driving module, and the other end is connected with the grid of the safety switch; one end of the limiting capacitor is connected with the other end of the driving resistor, and the other end of the limiting capacitor is connected with the drain electrode of the safety switch or grounded; wherein the capacitance value of the limiting capacitor at least exceeds the capacitance value of a parasitic Miller capacitor of the safety switch with the preset first multiplying power, so that the grid current of the safety switch is limited, and the Miller plateau area of the safety switch is prolonged. The Miller platform area of the safety switch is prolonged, so that the drain current iD of the safety switch can charge the inner side capacitor in an approximate constant current mode, triggering of a reverse over-current fault is prevented, and charging of the inner side capacitor cannot be interrupted.

The invention discloses a thyristor type device leakage current monitoring method and circuit and a power electronic device.The method comprises the steps that in response to a system turn-off instruction, a first control signal is sent to a device turn-off module; the device turn-off module is used for conducting a turn-off branch of the thyristor device according to the first control signal; acquiring a leakage current sampling signal from a leakage current monitoring module; the leakage current monitoring module is used for converting the gate current of the thyristor device into a leakage current sampling signal; and generating a leakage current monitoring result based on the leakage current sampling signal. According to the invention, real-time and accurate measurement of the leakage current can be realized on the premise of not influencing system operation.

The invention discloses a superconducting rectifier, a superconducting diode and a manufacturing and control method thereof, and belongs to the technical field of superconducting electronics, the superconducting rectifier comprises more than one superconducting diode, the superconducting diode comprises an insulating substrate and a superconducting nanowire, the superconducting nanowire is provided with a narrowing section, and the narrowing section is provided with a narrow section. The narrowing section is connected with a first gate line and a second gate line, the first gate line and the second gate line are symmetrically arranged, and the first gate line and the second gate line are both perpendicular to the superconducting nanowire. According to the invention, in-situ reconfigurable reversal symmetry destruction can be realized through a nanoscale hot spot controlled by a grid electrode; electrically controlled opening or closing and polarity reversal are realized by adjusting a small grid current without changing a magnetic field; the superconductive rectifier realizes electrically reconfigurable full-wave and half-wave rectification, and paves a way for development of extensible and electrically programmable superconductive electronic devices.

The invention provides a method and a device for identifying a second-class short circuit state of an insulated gate bipolar transistor (IGBT), and relates to the technical field of IGBT devices. The invention aims to timely and accurately judge whether the insulated gate bipolar transistor is in the second-class short circuit state or not. The method comprises the following steps: acquiring an emitter structure of an insulated gate bipolar transistor in a test circuit; if the emitter structure does not have the auxiliary emitter, acquiring a chip gate voltage, a gate side line parasitic inductance, a gate parasitic inductance, an emitter side line parasitic inductance, a common emitter parasitic inductance, a gate current, a collector current and a current from a gate to a collector in a gate driving loop; on the basis of the Kirchhoff's voltage law, grid voltage is determined through the collected parameter data; and if the grid voltage is within the preset short-circuit voltage range, determining that the insulated gate bipolar transistor has a second-class short circuit.

Provided is a buffer circuit that can realize a wide dynamic range, a reduced area, and a reduced power consumption amount while maintaining low output impedance. The buffer circuit includes a first transistor, a current source, a second transistor, an output terminal, and first and second capacitors. The first transistor has a gate to which an input signal is input. The current source is connected to one terminal of the first transistor. The second transistor is connected to the other terminal of the first transistor. The output terminal is connected to the one terminal or the other terminal of the first transistor. The first and second capacitors are between the current source and the gate of the second transistor. The first transistor, the second transistor, and the first capacitor form a first feedback circuit. The first transistor, the current source, and the second capacitor form a second feedback circuit.

A method for driving a transistor is described herein. In accordance with one embodiment, method includes modulating an output voltage by cyclically switching a transistor on and off, wherein, in each switching cycle, a gate current having a first current level is supplied to the transistor to switch the transistor on. The method further includes determining a characteristic time parameter of the output voltage (e.g. a rise or a delay time) and determining an error representing the difference between the determined time parameter and a target time in each switching cycle; adjusting the first current level based on the error; and detecting an oscillation of the error. When an oscillation is detected, the adjustment of the first current level is paused until the magnitude of the error exceeds a threshold value in a second number of consecutive switching cycles.

An electric circuit in which a first switching element and a first diode element are connected in antiparallel to form an upper arm and a second semiconductor element and a second diode element are connected in antiparallel to form a lower arm, and the upper arm and the lower arm are connected in series. A gate current path in one of the upper and lower arms and a reverse recovery path in the other one of the upper and lower arms are disposed close enough and extend at least partially in parallel to each other, so as to generate mutual inductance by the reverse recovery current flowing through the reverse recovery path and the gate current flowing through the gate current path.

The invention discloses a continuous time current comparator capable of outputting maximum current and minimum current. The continuous time current comparator comprises eight groups of cascode current mirrors consisting of NMOS (N-channel Metal Oxide Semiconductor) transistors N1-N20 and PMOS (P-channel Metal Oxide Semiconductor) transistors P1-P8, the drain electrode of the PMOS tube P2 is connected with the drain electrode of the NMOS tube N5 and the drain electrode of the NMOS tube N7 at the same time, the drain electrode of the PMOS tube P6 is connected with the drain electrode of the NMOS tube N11 and the drain electrode of the NMOS tube N13 at the same time, and the drain electrode of the PMOS tube P8 is connected with the drain electrode of the NMOS tube N17; a to-be-compared current Ia is input from the drain electrode of the NMOS transistor N1, and a to-be-compared current Ib is input and then is divided into two paths which respectively flow to the drain electrode of the NMOS transistor N3 and the drain electrode of the NMOS transistor N9; the drain electrode of the NMOS tube N19 outputs the maximum current Imax, and the drain electrode of the NMOS tube N15 outputs the minimum current Imin. After currents Ia and Ib to be compared are input, the maximum current Imax and the minimum current Imin corresponding to the currents Ia and Ib are output through current copying, summation and difference operation of the cascode current mirror, and the maximum current Imax and the minimum current Imin are both continuous analog current signals.

The invention discloses a semiconductor device and an electronic device comprising the same. The semiconductor device comprises a drain electrode, an active layer, a source electrode, a grid electrode and an internal grid electrode current collector, the active layer comprises a substrate, a drift region, a well region and a doped region which are stacked in the direction away from the drain electrode, and the surface, away from the drain electrode, of the active layer extends towards the drift region to form a first groove and a second groove; the source electrode partially extends into the first groove, and the part, extending into the first groove, of the source electrode is insulated from the active layer; the grid electrode at least partially extends into the second groove, and the grid electrode and the active layer are insulated and spaced; the internal gate current collector is arranged on the side, away from the drain electrode, of the active layer, the source electrode and the gate electrode are coupled through the internal gate current collector, and the internal gate current collector has an internal driving potential; wherein the equivalent resistance temperature change coefficient of the source electrode is smaller than the equivalent resistance temperature change coefficient of the grid electrode.

A control circuit for a current source converter having a current generator comprising an inductance and having two or more half bridges, each half bridge having an upper leg provided with upper switching devices and a lower leg provided with lower switching devices, the upper leg switching devices and the lower leg switching devices being controlled by a controller to provide overlap between upper leg off switching devices and upper leg on switching devices and to provide overlap between lower leg on switching devices and lower leg off switching devices by gate pull-up and pull-down pulse signals input to gate driver buffers of the switching devices, characterized in that the gate driver circuit comprises: - a gate current mirror circuit for each upper leg switching device and each lower leg switching device, the gate current mirror circuit providing a gate pull-down signal on a source branch of the gate driver buffer of the switching device when the switching device is off, the gate pull-down signal being connected to a control line of a gate buffer of a respective other upper leg switching device or other lower leg switching device, - a positive gate command connection path from a positive gate command output of a pre-driver for each upper leg switching device and each lower leg switching device, the positive gate command connection path providing a reset signal for the gate pull-down signal of the respective other upper leg switching device or respective other lower leg switching device.

The present invention discloses an IGCT gate drive device, electrical equipment, and IGCT gate drive method. The device includes: a detection unit that detects the IGCT gate current and generates an IGCT turn-on signal when the detected IGCT gate current reaches the IGCT's set turn-on current; a control unit that controls the IGCT to turn on based on the IGCT turn-on signal; the detection unit that generates an IGCT turn-on maintenance signal when the detected IGCT gate current continues to be less than the IGCT's set turn-on maintenance current; and the control unit that adjusts the IGCT gate current based on the IGCT turn-on maintenance signal to maintain the IGCT on. This solution can solve the problem of erroneous shutdown caused by the gate current being less than the maintenance current after the IGCT is turned on, thereby preventing the IGCT from erroneously shutting down due to the gate current being less than the maintenance current after the IGCT is turned on.

The present invention discloses a method for determining a control gate current of a light-emitting device based on a unidirectional current-cutoff gate, comprising: applying a first drive signal corresponding to a first grayscale value between an anode and a cathode, and applying a first gate control current to a first control electrode of the unidirectional current-cutoff gate structure; continuously changing the first gate control current, and collecting first luminous efficiencies corresponding to different first gate control currents in real time; in response to the first luminous efficiency matching a standard luminous efficiency, determining the corresponding first gate control current as a standard gate control current of a first grayscale value; obtaining standard gate control currents corresponding to multiple different grayscale values; obtaining a first functional relationship based on a linear relationship between different grayscale values ​​and their corresponding standard gate control currents; and obtaining the standard gate control current corresponding to each grayscale value of the light-emitting device based on the first functional relationship. The present invention can quickly determine the standard gate control signal corresponding to different grayscale values.

Embodiments of the present invention related to a neuromimetic circuit including a transmitter circuit to receive the threshold signal from a superconducting optoelectronic neuron and convert the small current pulse to a voltage pulse sufficient to produce light from a semiconductor diode. This light is the signal used to communicate between neurons in the network. The transmitter circuit in accordance with the present invention includes an amplifier chain that comprises two Josephson junctions, a superconducting thin-film current-gated current amplifier, and a superconducting thin-film current-gated voltage amplifier. The transmitter circuit in accordance with the present invention enable an amplification sequence that allows neuronal firing of about 20 MHz with power density sufficiently low to be cooled with standard 4He cryogenic systems operating at 4.2 K.

The invention discloses a test structure for positioning a plasma damage source. A test substructure corresponding to a selected metal layer comprises a first MOS transistor, a first gate lead, a first antenna and a monitoring gate liner. The first gate lead is composed of metal wires of a selected metal layer. The first antenna is connected with the first gate lead. The first gate lead is connected with the first gate conductive material layer of the first MOS transistor. The first antenna, the first gate lead and the first gate conductive material layer form a first path for accumulating plasma charges to the surface of the first gate dielectric layer, and the first antenna is used for increasing absorption of the plasma charges and amplifying damage. The monitoring gate pad is connected with the first gate lead and is used for testing the gate current of the first MOS transistor, and the gate current is used for monitoring the damage amount of the first gate dielectric layer caused by the graphical etching plasma charge of the selected metal layer. The invention also discloses a test method for positioning the plasma damage source. The plasma damage source can be positioned.

The invention discloses an aviation high-power SSPC active current sharing circuit, which improves the current sharing stability of a power device in a non-switching state in an SSPC and reduces the complexity of the circuit. The circuit comprises a first main circuit and a plurality of parallel branches. The current of a first main circuit is used as a reference quantity, and the current of other parallel branches is used as a following quantity, so that the dynamic current sharing of multiple tubes connected in parallel is realized; the first main circuit and the plurality of branch circuits use MOSFETs to control the on and off of the circuit, and use a mirror current source and a resistor to provide drive current required by the SSPC to respectively control the on and off of the SSPC; each branch circuit adjusts the driving current of each parallel branch circuit in the SSPC in real time through a grid current injection circuit and a grid current extraction circuit, the dynamic current sharing condition of the parallel branch circuits in the switching process of the SSPC is improved, the current sharing of a power device in a non-switching state is realized, the reliability and stability of the SSPC are improved, and the service life of the SSPC is prolonged.

This solves the problem that arises when turning off high-side or low-side transistors. [Solution] The first output sensor 280 controls the output voltage V of the output stage 110. OUT The first threshold voltage V TH1 When the value drops to a certain level, the first output detection signal VOUTDET1 is asserted. When the output stage 110 is in current source mode, the control circuit 210 responds to the instruction to turn off the high-side transistor MH by causing the high-side driver 220 to sink the high-side gate current I from the gate of the high-side transistor MH. HG_OFF The first current I1 is set. The control circuit 210 responds to the assertion of the first output detection signal VOUTDET1 by setting the high-side gate current I HG_OFF Set the current to a second current I2, which is less than the first current I1.

The invention discloses a method for establishing a GaN HEMT device gate model based on electric leakage matching, and the method comprises the steps: analyzing a gate structure of a GaN HEMT device, and establishing a corresponding gate equivalent circuit model which is formed by the sequential series connection of a first voltage dividing structure D1, a voltage dividing resistor R1 and a second voltage dividing structure D2 in the device gate structure; obtaining a voltage division relation in the gate equivalent circuit model based on electric leakage matching, constructing an iterative algorithm for calculating channel charges Qch, and solving the channel charges Qch through iterative calculation; and acquiring data of gate current of the GaN HEMT device under different gate voltage conditions, and performing parameter extraction on the gate equivalent circuit model. Model construction is carried out on the GaN HEMT device, calling of designers is facilitated, and the cost and time of integrated circuit design are greatly saved.

Switching device (10), comprising: a power transistor (50, 52) with a gate terminal (G1, G2), a collector or drain terminal (K1, K2) and an emitter or source terminal (E1, E2); a voltage source (34, 36) which is configured to supply a supply voltage to a transition between the gate terminal (G1, G2) and the emitter or source terminal (E1, E2); a device (22, 26) for measuring a voltage that is established between the gate terminal (G1, G2) and the emitter or source terminal (E1, E2) depending on a state of the power transistor (50, 52), or for measuring a gate current through the gate terminal (G1, G2) that depends on the state of the power transistor (50, 52); wherein the device (22, 26) for measuring a voltage or for measuring a gate current outputs a corresponding measurement signal (70, 71) to a control unit (12); the control unit (12) which is configured to compare the measurement signal (70, 71) with a reference (72) and, depending on the comparison result, to output at least one status signal (75); characterized by the fact that the status signal (75) indicates that there is a short circuit on a path between the collector or drain terminal (K1, K2) and the emitter or source terminal (E1, E2); and the device (22, 26) is configured to perform the measurement of the voltage or gate current and / or to generate the measurement signal (70, 71) corresponding to the measured voltage or gate current without applying a high-voltage voltage between the collector or drain terminal (K1, K2) and the emitter or source terminal (E1, E2).

This invention provides a method for obtaining breakdown voltage, a computer-readable storage medium, and a terminal. The method includes: providing a flash memory device, the flash memory device including word lines, control gates located on both sides of the word lines, and a dielectric layer between the two; applying a first voltage to the control gates, and applying a second voltage to the word lines within a preset voltage range with a preset step size; measuring and obtaining the word line current and control gate current under each of the second voltages, wherein the word line current is the current flowing into the word line, and the control gate current is the current flowing out of the control gate; and obtaining the breakdown voltage of the dielectric layer based on the word line current and the control gate current; wherein the first voltage is less than 0V, and the second voltage is greater than or equal to 0V. This invention solves the problem of inaccurate breakdown voltage of the dielectric layer between the word lines and the control gates obtained by existing methods.

Semiconductor devices, systems and methods are described. A semiconductor device can include a driver configured to output a gate current to drive a power module. The semiconductor device can further include a buffer configured to buffer a reference voltage that is less than a supply voltage being provided to the driver. The semiconductor device can further include a controller configured to determine a gate voltage of the power module is equivalent to the reference voltage. The controller can, in response to determination that the gate voltage is equivalent to the reference voltage, disable the driver to cause the driver to stop providing the gate current to the power module and enable the buffer to supply the reference voltage to the power module.

The present application relates to the technical field of LED chip, and particularly relates to an epitaxial wafer of Mini LED with low GTO effect and a growth method thereof. The epitaxial wafer of Mini LED with low GTO effect comprises a buffer layer, a U-shaped GaN layer, an N-type GaN layer, a multi-quantum well active region layer and a P-type GaN layer which are sequentially grown on a substrate. The multi-quantum well active region layer comprises a defect inducing layer, a Si-doped AlGaN layer and a multi-quantum well light emitting layer which are sequentially grown on the N-type GaN layer. The epitaxial wafer of Mini LED avoids strong GTO effect and improves the brightness consistency of Mini LED by setting the defect inducing layer after the N-type GaN layer and setting the Si-doped AlGaN layer after the defect inducing layer.

The application relates to the technical field of amorphous soft magnetic material preparation, and discloses a cobalt-based amorphous soft magnetic alloy material, a preparation method thereof and application. a Fe b Mo c Si d B e C f M g In the formula, a, b, c, d, e, f and g respectively represent the atomic percentage content of corresponding components; wherein 50<=a<=70, 2<=b<=8, 0.5<=c<=5, 10<=d<=20, 10<=e<=20, 0.01<=f<=0.5, 0.1<=g<=5, and a+b+c+d+e+f+g=100; and M represents at least one of elements V, Cr, Mn and Nb. The cobalt-based amorphous soft magnetic alloy material provided by the application has low saturation magnetic induction intensity, low coercive force, high rectangular ratio and other superior soft magnetic properties, is good in corrosion resistance and easy to prepare; and a magnetic probe prepared from the alloy material has high precision in sensor testing, and has important significance for promoting the development of small high-precision magnetic flux gate current sensors.

The present invention discloses a power supply protection circuit for a depletion-type negative voltage device, used for power-on and power-off protection of negative voltage devices such as GaN HEMTs and GaAs PHEMTs. The protection circuit includes: a negative voltage device gate switch timing circuit, used to control the timing of powering on and off the negative voltage device's gate; a negative voltage device drain switch timing circuit, used to control the timing of powering on and off the negative voltage device's drain; and a negative voltage device gate bias temperature compensation constant current circuit, used to temperature-compensate the negative voltage device's gate bias voltage to maintain a constant gate current at different operating temperatures. The present invention can achieve power supply timing protection for negative voltage devices, preventing device damage caused by power-on and power-off timing issues, and provides a dynamic gate voltage to ensure a constant current state at different operating temperatures, such as high, normal, and low temperatures. The present invention has a simple structure, low cost, and wide applicability, making it suitable for commercialization.

The invention discloses a low-side switch short circuit detection circuit, a protection circuit and a switching power supply applying the same, the low-side switch short circuit detection circuit comprises an operational amplifier, the positive input end of the operational amplifier is connected with a short circuit threshold voltage, the reverse input end of the operational amplifier is connected between a first resistor and the drain electrode of an NMOS, and the output end of the operational amplifier is connected with the grid electrode of the NMOS; the current mirror is connected between the operational amplifier and the comparator and is used for converting the voltage of the short-circuit threshold voltage relative to the ground into the voltage relative to the source electrode of the NMOS; and the positive end of the comparator is connected with the NMOS drain voltage, the negative end of the comparator is connected with the voltage of the short-circuit threshold voltage relative to the NMOS source, and a voltage comparison result is output. The method is flexible in application, simple and effective, and design resources and cost are reduced while detection accuracy and reliability are guaranteed.

The invention discloses an IGCT (integrated gate commutated thyristor) driving circuit. The circuit comprises an MOSFET driving circuit which comprises a pair of N-channel MOSFET and P-channel MOSFET which work complementarily and is used for providing forward gate current and reverse gate current for the IGCT device; the two gate resistors are used for adjusting the gate current of the IGCT device; the two acceleration capacitors are used for providing transient current at the conduction moment of the MOSFET driving circuit and adjusting the gate voltage rising speed of the IGCT device; the signal isolation module is used for transmitting an external control signal to a grid electrode of the MOSFET; and the power supply module is used for providing positive direct-current voltage for the N-channel MOSFET and providing negative direct-current voltage for the P-channel MOSFET. The technical problems that the switching frequency of the IGCT is limited and the power conversion efficiency is not high due to the fact that the gate current change rate is low and the switching speed is low in the high-frequency switching operation of the IGCT in the related technology are solved.

The utility model discloses a band-gap reference voltage circuit without an operational amplifier, which solves the problems that the structure and operation of the band-gap reference voltage circuit without the operational amplifier in the prior art are complicated, and the PSRR performance of output voltage in a high-frequency band is poor, and comprises a band-gap reference core circuit and a cascode current mirror circuit which are connected with each other, the band-gap reference core circuit and the cascode current mirror circuit are jointly connected with a starting circuit, and the band-gap reference core circuit is further connected with a driving circuit. According to the utility model, the circuit structure and the operation complexity are simplified, the parameters of each component do not need to be repeatedly adjusted, and the excellent PSRR performance of the output voltage in a high frequency band is realized.

The invention provides a fluxgate current sensor, and belongs to the technical field of current detection sensors. Comprising a front shell provided with a through first through hole; the rear shell is provided with a second through hole coaxial with the first through hole, and a hollow cavity is defined by the rear shell and the front shell; a connector male end is also arranged on one side, far away from the front shell, of the rear shell; the magnetic core unit is embedded in the cavity, surrounds the second through hole and is used for acquiring an excitation current signal of the current wire to be detected; the control circuit board is embedded in the cavity, is electrically connected with the magnetic core unit and is used for acquiring and outputting an excitation current signal of the magnetic core unit; wherein the first through hole or the second through hole is used for a to-be-detected current lead to radially pass through; the magnetic core unit only comprises one coil; the control circuit board further drives the magnetic core unit to generate an excitation magnetic field.

The invention provides a test circuit, a test method and a test system for gate leakage current of an MOS (Metal Oxide Semiconductor) tube. The test circuit comprises a band-gap reference voltage module, a high-resistance module, a leakage current detection module and a test voltage excitation module, and the output end of the band-gap reference voltage module is coupled with the first end of the high-resistance module. The second end of the high-resistance module, the output end of the test voltage excitation module and the leakage current detection module are coupled to a grid current test node used for being connected with the MOS tube to be tested. The band-gap reference voltage module provides a bias voltage with a first preset threshold value; the test voltage excitation module provides continuous scanning voltage; the leakage current detection module detects the test current of the current test node and obtains a leakage current detection result according to the bias voltage, the scanning voltage and the test current. According to the invention, the detection of the gate leakage current of the to-be-tested MOS transistor at the fA magnitude can be realized, and the charge stability of the gate node of the to-be-tested MOS transistor can be ensured, so that the consistency of batch testing can be ensured, and the reliability is high.

The application discloses a kind of shipborne localization IGBT module drive monitoring systems, specifically related to power electronic drive monitoring and smart grid control field, including: drive monitoring acquisition module is used to access the IGBT module drive board in shipborne smart grid, gate loop, power loop and auxiliary power supply loop, gathers drive control signal, gate voltage, gate current, collector voltage, emitter potential, desaturation detection signal and auxiliary power supply state, and output corresponding moment monitoring record;Diagnosis disturbance injection module is used to read the drive switching time in monitoring record, and under the condition that current power conversion task is not changed, diagnostic disturbance action is injected to gate loop. By injecting diagnostic disturbance action in the process of drive switching and generating drive response fingerprint, external working condition disturbance in on-load operation and drive chain intrinsic anomaly are separated and judged, so that the problem of coexistence of false protection shutdown and missed detection is relatively improved.