72 results about "Double heterostructure" patented technology

Low-bandgap, monolithic, multi-bandgap, optoelectronic devices (10), including PV converters, photodetectors, and LED's, have lattice-matched (LM), double-heterostructure (DH), low-bandgap GaInAs(P) subcells (22, 24) including those that are lattice-mismatched (LMM) to InP, grown on an InP substrate (26) by use of at least one graded lattice constant transition layer (20) of InAsP positioned somewhere between the InP substrate (26) and the LMM subcell(s) (22, 24). These devices are monofacial (10) or bifacial (80) and include monolithic, integrated, modules (MIMs) (190) with a plurality of voltage-matched subcell circuits (262, 264, 266, 270, 272) as well as other variations and embodiments.

Aspects of the present invention provide an enhancement mode (E-mode) insulated gate (IG) double heterostructure field-effect transistor (DHFET) having low power consumption at zero gate bias, low gate currents, and/or high reliability. An E-mode HFET in accordance with an embodiment of the invention includes: top and bottom barrier layers; and a channel layer sandwiched between the bottom and the top barrier layers, wherein the bottom and top barrier layers have a larger bandgap than the channel layer, and wherein polarization charges of the bottom barrier layer deplete the channel layer and polarization charges of the top barrier layer induce carriers in the channel layer; and wherein a total polarization charge in the bottom barrier layer is larger than a total polarization charge in the top barrier layer such that the channel layer is substantially depleted at zero gate bias.

A heterostructure device layer is epitaxially grown on a virtual substrate, such as an InP/InGaAs/InP double heterostructure. A device substrate and a handle substrate form the virtual substrate. The device substrate is bonded to the handle substrate and is composed of a material suitable for fabrication of optoelectronic devices. The handle substrate is composed of a material suitable for providing mechanical support. The mechanical strength of the device and handle substrates is improved and the device substrate is thinned to leave a single-crystal film on the virtual substrate such as by exfoliation of a device film from the device substrate. An upper portion of the device film exfoliated from the device substrate is removed to provide a smoother and less defect prone surface for an optoelectronic device. A heterostructure is epitaxially grown on the smoothed surface in which an optoelectronic device may be fabricated.

Layered and film structures for improving the performance of semiconductor devices include single and multiple quantum wells and double heterostructures and superlattice structures.

A double hetero structure light-emitting diode device includes an active layer (6), a positive-electrode-side cladding layer, a negative-electrode-side cladding layer (4), a window layer (9) and an undoped AlInP layer. The positive-electrode-side cladding layer includes an undoped AlInP layer (7) grown to have a thickness of 0.5 μm and an intermediate layer (8) doped to assume p-type conductivity and having an intermediate energy band gap value between that of the undoped AlInP layer and that of the window layer. The window layer on the intermediate layer is a GaP layer grown at 730° C. or higher and at a growth rate of 7.8 μm/hour or more in the presence of Ze serving as a dopant. The negative-electrode-side cladding layer is provided with an undoped AlInP layer (5) having a thickness of 0.1 μm or more. With this configuration, there is provided a light-emitting diode device that enhances the crystallinity of a window layer, prevents generation of faults caused by a high-temperature process and attains high luminance at a wavelength falling within a yellow-green band.

Methods and systems for germanium-on-silicon photodetectors without germanium layer contacts are disclosed and may include, in a semiconductor die having a photodetector, where the photodetector includes an n-type silicon layer, a germanium layer, a p-type silicon layer, and a metal contact on each of the n-type silicon layer and the p-type silicon layer: receiving an optical signal, absorbing the optical signal in the germanium layer, generating an electrical signal from the absorbed optical signal, and communicating the electrical signal out of the photodetector via the n-type silicon layer and the p-type silicon layer. The photodetector may include a horizontal or vertical junction double heterostructure where the germanium layer is above the n-type and p-type silicon layers. An intrinsically-doped silicon layer may be below the germanium layer between the n-type silicon layer and the p-type silicon layer. A top portion of the germanium layer may be p-doped.

A light emitting device having an oxide transparent electrode layer as an emission drive electrode, and designed so that damage possibly occurs during bonding of electrode wires to the bonding pads is less influential to a light emitting layer portion is disclosed. The light emitting device has the light emitting layer portion composed of a compound semiconductor and has a double heterostructure in which a first-conductivity-type cladding layer, an active layer and a second-conductivity-type cladding layer are stacked in this order; and the light emitting layer portion is applied with emission drive voltage through an oxide transparent electrode layer formed so as to cover the main surface of the second-conductivity-type cladding layer. A bonding pad composed of a metal is disposed on the oxide transparent electrode layer, and to the bonding pad an electrode wire for current supply is bonded. Between the second-conductivity cladding layer and the oxide transparent electrode layer, a cushion layer composed of a compound semiconductor having a dopant concentration lower than that of the second-conductivity-type cladding layer is disposed.

A field-effect transistor has a so-called double heterostructure which is formed such that a channel layer through which electrons travel is provided between an electron supply layer and a liner layer, wherein a forbidden band width of the liner layer and a forbidden band width of the electron supply layer are broader than a forbidden bandwidth of the channel layer.

The invention discloses a double-channel transistor. The double-channel transistor is made of GaN (gallium nitride), and includes two channels, i.e. a first channel and a second channel, wherein the first channel serves as an interface of a barrier layer and a GaN channel layer, the second channel serves as an interface of a back barrier layer and the GaN channel layer, and the barrier layer and the back barrier layer are both made of AlGaN (aluminum gallium nitride); the thickness of the AlGaN back barrier layer is 20 nm, and the aluminum content is 30 percent; the thickness of the AlGaN barrier layer is 20 nm, and the aluminum content is 30 percent; a substrate of the transistor is a silicon carbide substrate. The double-channel transistor and a preparation method for the double-channel transistor have the advantages that AlGaN with a certain aluminum content and a certain thickness serves as the back barrier layer, so as to form an AlGaN/GaN/AlGaN double heterostructure; a two-dimensional electron gas (2DEG) in the channels is confined in two extremely high barriers through a strong polarization electric field to form the two channels, which improves the 2DEG carrier confinement in the channels and the device reliability.

Provided is a nitride semiconductor light emitting element that has improved light extraction efficiency and a wide irradiation angle of outgoing light irrespective of the reflectance of a metal used for an electrode. An n side anti-reflection layer 2 and a p side Bragg reflection layer 4 are formed so as to sandwich an MQW active layer 3 that serves as a light emitting region, and the nitride semiconductor light emitting element has a double hetero structure. On top of the n side anti-reflection layer 2, an n electrode 1 is formed. Meanwhile, at the lower side of the p side Bragg reflection layer 4, a p electrode 5, a reflection film 7, and a pad electrode 8 are formed, and the pad electrode is bonded to a support substrate 10 with a conductive bonding layer 9 interposed in between. Both the n side anti-reflection layer 2 and the p side Bragg reflection layer 4 also serve as contact layers. The n side anti-reflection layer 2 is disposed on the light-extracting-direction side while the p side Bragg reflection layer 4 is disposed on the opposite side to the light-extracting-direction side. Consequently, the light extraction efficiency is improved.

A laser device includes a double hetero-structure element constructed by depositing a p-type cladding layer, a quantum well active layer, an n-type thin first cladding layer and an n-type thick second cladding layer sequentially. A ridge-waveguide is shaped between two trenches formed in the second cladding layer. The first cladding layer serves as an etching stopper while etching the second cladding layer to form the two trenches. The trenches reach to or reach in vicinity to the surface of the first cladding layer. High-resistance regions may be formed in portions of the first cladding layer directly underneath the trenches. The thin first cladding layer, suppresses leakage current and improves the temperature characteristics and the operating speed characteristics of the laser device.

A process for fabricating an integrated group III nitride structure comprising high electron mobility transistors (HEMTs) and Schottky diodes, and the resulting structure, are disclosed. Integration of vertical junction Schottky diodes is enabled, and the parasitic capacitance and resistance as well as the physical size of the diode are minimized. A process for fabricating an integrated group III nitride structure comprising double-heterostructure field effect transistors (DHFETs) and Schottky diodes and the resulting structure are also disclosed.

A double heterojunction field effect transistor (DHFET) includes a substrate, a buffer layer consisting of GaN back-barrier buffer layer formed on the substrate, a channel layer consisting of an In_xGa_1-xN ternary alloy in one embodiment, and in another embodiment, InGaN/GaN superlattice (SL) formed on the GaN back-barrier buffer layer opposite to the substrate. A GaN spacer layer is formed on the In_xGa_1-xN or InGaN/GaN superlattice channel layer opposite to the GaN buffer layer and a carrier-supplying layer consisting of an Al_1-yIn_yN ternary alloy is formed on the GaN spacer layer opposite to the channel layer. A preferred thickness of the GaN spacer layer is less than about 1.5 nm. The InGaN/GaN SL preferably includes 1 to 5 InGaN—GaN pairs and a preferred thickness of the InGaN layer in the InGaN/GaN SL is equal to or less than about 0.5 nm. A two-dimensional electron gas is formed at the interface between the In_xGa_1-xN or InGaN/GaN SL channel and GaN spacer layers.

Provided is an element structure whereby it is possible to produce a silicon-germanium light-emitting element enclosing an injected carrier within a light-emitting region. Also provided is a method of manufacturing the structure. Between the light-emitting region and an electrode there is produced a narrow passage for the carrier, specifically, a one-dimensional or two-dimensional quantum confinement region. A band gap opens up in this section due to the quantum confinement, thereby forming an energy barrier for both electrons and positive holes, and affording an effect analogous to a double hetero structure in an ordinary Group III-V semiconductor laser. Because no chemical elements other than those used in ordinary silicon processes are employed, the element can be manufactured inexpensively, simply by controlling the shape of the element.

A double hetero structure light-emitting diode device includes an active layer ( 6 ), a positive-electrode-side cladding layer, a negative-electrode-side cladding layer ( 4 ), a window layer ( 9 ) and an undoped AlInP layer. The positive-electrode-side cladding layer includes an undoped AlInP layer ( 7 ) grown to have a thickness of 0.5 mum and an intermediate layer ( 8 ) doped to assume p-type conductivity and having an intermediate energy band gap value between that of the undoped AlInP layer and that of the window layer. The window layer on the intermediate layer is a GaP layer grown at 730 DEG C. or higher and at a growth rate of 7.8 mum/hour or more in the presence of Ze serving as a dopant. The negative-electrode-side cladding layer is provided with an undoped AlInP layer ( 5 ) having a thickness of 0.1 mum or more. With this configuration, there is provided a light-emitting diode device that enhances the crystallinity of a window layer, prevents generation of faults caused by a high-temperature process and attains high luminance at a wavelength falling within a yellow-green band.

A double-heterostructure GaN-based high-electron mobility transistor structure comprises: a substrate; a nucleating layer prepared on the substrate; an unpurposed doped high resistance layer prepared on the nucleating layer; an unpurposed doped inserting layer prepared on the unpurposed doped high resistance layer; an unpurposed doped high mobility layer prepared on the unpurposed doped inserting layer; an unpurposed doped aluminum nitride inserting layer prepared on the high mobility layer; an unpurposed doped ALGaN barrier layer prepared on the unpurposed doped aluminum nitride inserting layer; and an unpurposed doped GaN capping layer prepared on the unpurposed doped ALGaN barrier layer.