52 results about "Heterostructure field effect transistors" patented technology

Aspects of the present invention provide an enhancement mode (E-mode) insulated gate (IG) double heterostructure field-effect transistor (DHFET) having low power consumption at zero gate bias, low gate currents, and/or high reliability. An E-mode HFET in accordance with an embodiment of the invention includes: top and bottom barrier layers; and a channel layer sandwiched between the bottom and the top barrier layers, wherein the bottom and top barrier layers have a larger bandgap than the channel layer, and wherein polarization charges of the bottom barrier layer deplete the channel layer and polarization charges of the top barrier layer induce carriers in the channel layer; and wherein a total polarization charge in the bottom barrier layer is larger than a total polarization charge in the top barrier layer such that the channel layer is substantially depleted at zero gate bias.

The present invention is directed to high frequency, high power or low noise devices such as low noise amplifiers, amplifiers operating at frequencies in the range of 1 GHz up to 400 GHz, radars, portable phones, satellite broadcasting or communication systems, or other devices and systems that use high electron mobility transistors, also called hetero-structure field-effect transistors. A high electron mobility transistor (HEMT) includes a substrate, a quantum well structure and electrodes. The high electron mobility transistor has a polarization-induced charge of high density. Preferably, the quantum well structure includes an AlN buffer layer, an un-doped GaN layer, and an un-doped InAlN layer.

A GaN-based heterostructure field effect transistor capable of accomplishing higher output, higher breakdown voltage, higher speed, higher frequency, and the like. A heterostructure field effect transistor including a channel layer (4) of GaN and a barrier layer (6) of AlGaN, wherein the surface of a transistor element has an insulating film (10).

A vertical heterostructure field effect transistor including a first layer having a first material, and the first material having a hexagonal crystal lattice structure defining a first bandgap and one or more non-polar planes is provided. The transistor further includes a second layer that is adjacent to the first layer having a second material. Further, the second layer has a first surface and a second surface, and a portion of the second layer first surface is coupled to the surface of the first layer to form a two dimensional charge gas and to define a first region. The second material may have a second bandgap that is different than the first bandgap. Furthermore, the transistor may include a conductive layer that is disposed in the trench and is interposed between the first region and a second region that is not in electrical communication with the first region if no electrical potential is applied to the conductive layer, and an electrical potential applied to the conductive layer allows electrical communication from the first region to the second region.

A heterostructure field effect transistor (HFET) gallium nitride (GaN) semiconductor power device comprises a hetero-junction structure comprises a first semiconductor layer interfacing a second semiconductor layer of two different band gaps thus generating an interface layer as a two-dimensional electron gas (2DEG) layer. The power device further comprises a source electrode and a drain electrode disposed on two opposite sides of a gate electrode disposed on top of the hetero-junction structure for controlling a current flow between the source and drain electrodes in the 2DEG layer. The power device further includes a floating gate located between the gate electrode and hetero-junction structure, wherein the gate electrode is insulated from the floating gate with an insulation layer and wherein the floating gate is disposed above and padded with a thin insulation layer from the hetero-junction structure and wherein the floating gate is charged for continuously applying a voltage to the 2DEG layer to pinch off the current flowing in the 2DEG layer between the source and drain electrodes whereby the HFET semiconductor power device is a normally off device.

The invention discloses a high-threshold voltage gallium nitride (GaN) enhancement metal oxide semiconductor heterostructure field effect transistor (MOSHFET) device and a manufacturing method. The device comprises a substrate (1) and an epitaxial layer grown on the substrate (1), and is characterized in that: the epitaxial layer comprises a stress buffer layer (2), a GaN layer (3) and a heterostructure barrier layer (4) sequentially upwards from the bottom; the heterostructure barrier layer (4) is etched to the GaN layer (4) to form a groove in a gate region; a p-type GaN layer (6) is selectively grown on the groove; an insulated dielectric layer (7) is deposited on the surfaces of the p-type GaN layer (6) and the heterostructure barrier layer (4) and etched in source and drain regions on the surface of the heterostructure barrier layer (4); a gate metal (9) is evaporated in the gate region; and an ohmic contact metal (8) is evaporated on the source and drain regions. The device provided by the invention has a simple structure, is simple in manufacturing process and high in stability, and can effectively increase a forward threshold voltage and simultaneously repair crystal lattices damaged by plasma treatment.

Gallium nitride (GaN) based semiconductor devices and methods of manufacturing the same. The GaN-based semiconductor device may include a heat dissipation substrate (that is, a thermal conductive substrate); a GaN-based multi-layer arranged on the heat dissipation substrate and having N-face polarity; and a heterostructure field effect transistor (HFET) or a Schottky electrode arranged on the GaN-based multi-layer. The HFET device may include a gate having a double recess structure. While such a GaN-based semiconductor device is being manufactured, a wafer bonding process and a laser lift-off process may be used.

Disclosed in this invention is a new four-terminal type and multiple delta-doped transistors with multiple functions grown by low-pressure metalorganic chemical vapor deposition (LP-MOCVD). All the epilayers are grown on n+-GaAs substrates. The real-space transfer transistors (RST), the collector is located under the substrate, reveal very strong negative differential resistance phenomena. The RST structure using an InGaAs channel manifests superior characteristics of a very high peak-to-valley current ratio up to 430,000 at room temperature, a peak current as high as 100 mA, very sharp charge injection, and a valley current as broad as 5.5V. Meanwhile, high performance heterostructure field effect transistors can be implemented on the same wafer by further evaporating a gate between source and drain electrodes. In order to significantly reduce leakage current, an ohmic recession is made at the source and drain. These new multiple-functions device may be used in high-speed, low-noise, and/or high power microwave oscillators and amplifiers.

A hetero-structure field effect transistor (HFET). The HFET may include a first contact and a second contact and a hetero-junction structure. The hetero-junction structure may include a first layer made from a first semiconductor material and a second layer made from a second semiconductor material. An interface at which the first layer and the second layer are in contact with each other may be provided, along which a two dimensional electron gas (2DEG) is formed in a part of the first layer directly adjacent to the interface, for propagating of electrical signals from the first contact to the second contact or vice versa. The transistor may further include a gate structure for controlling a conductance of the channel; a substrate layer made from a substrate semiconductor material, and a dielectric layer separating the first layer from the substrate layer. The second contact may include an electrical connection between the substrate layer and the first layer. The electrical connection may include a passage through the dielectric layer filled with an electrically conducting material which is electrically connected to the first layer.

Heterostructure field-effect transistor (HFET) having a channel layer, a barrier layer disposed on the channel layer, and a gate, source and drain electrodes disposed on the barrier layer, respectively, and corresponding fabrication methods are disclosed. The drain electrode includes a p-type semiconductor patterned structure and a raised drain section, the drain electrode includes a Schottky contact and an ohmic contact, the Schottky contact is formed between a top surface together with a side surface of p-type semiconductor patterned structure and a bottom surface together with a side surface of raised drain section, the ohmic contact is formed between another surface of raised drain section and barrier layer, the raised drain section partially surrounding the p-type semiconductor patterned structure, and a bandgap of the channel layer is less than a bandgap of the barrier layer.

A heterostructure field effect transistor (HFET) gallium nitride (GaN) semiconductor power device comprises a hetero-junction structure comprises a first semiconductor layer interfacing it second semiconductor layer of two different band gaps thus generating an interface layer as a two-dimensional electron gas (2DEG) layer. The power device further comprises a source electrode and a drain electrode disposed on two opposite sides of a gate electrode disposed on top of the hetero-junction structure for controlling a current flow between the source and drain electrodes in the 2DEG layer. The power device further includes a floating gate located between the gate electrode an hetero-junction structure, wherein the gate electrode is insulated from the floating gate with an insulation layer and wherein the floating gate is disposed above and padded with a thin insulation layer from the hetero-junction structure and wherein the floating gate is charged for continuously applying a voltage to the 2DEG layer to pinch off the current flowing in the 2DEG layer between the source and drain electrodes whereby the HFET semiconductor power device is a normally off device.

The invention discloses a vertical channel heterostructure field-effect transistor (VC-HFET) and a preparation method thereof. The heterostructure field-effect transistor comprises a source electrode, a drain electrode, a grid electrode and at least one heterostructure channel, wherein the axis of the heterostructure channel is fundamentally vertical to a selected plane; the heterostructure channel is positioned in a heterostructure; the heterostructure comprises a second semiconductor and a first semiconductor arranged around the second semiconductor, the energy gap of the first semiconductor is greater than that of the second semiconductor, and two-dimensional electron gas or two-dimensional hole gas is formed in the heterostructure channel; the source electrode is electrically connected with the drain electrode through the two-dimensional electron gas or the two-dimensional hole gas; and the grid electrode is distributed between the source electrode and the drain electrode. The heterostructure field-effect transistor disclosed by the invention has the advantages of being good in grid-control capacity, high in work efficiency, low in process difficulty, easy to manufacture, high in rate of finished products and the like.

A device including a first layer having a first material, and the first material having a hexagonal crystal lattice structure defining a first bandgap and one or more non-polar planes is provided. The device further includes a second layer that is adjacent to the first layer having a second material. The second material may have a second bandgap that is different than the first bandgap. The second layer may have a first surface and a second surface, and a portion of the second layer first surface may be coupled to a surface of the first layer to form a two dimensional charge gas and to define a first region. Further, the device includes a conductive layer that is interposed between the first region and a second region that is spaced from the first region, where the device is normally-off if no electrical potential is applied to the conductive layer, and an electrical potential applied to the conductive layer allows electrical communication from the first region to the second region.

A heterostructure device or article includes a carrier transport layer, a back channel layer and a barrier layer. The carrier transport layer has a first surface and a second surface opposing to the first surface. The back channel layer is secured to the first surface of the carrier transport layer and the barrier layer is secured to the second surface of the carrier transport layer. Each of the carrier transport layer, the back channel layer and the barrier layer comprises an aluminum gallium nitride alloy. The article further includes a 2D electron gas at an interface of the second surface of the carrier transport layer and a surface of the barrier layer. The 2D electron gas is defined by a bandgap differential at an interface, which allows for electron mobility. A system includes a heterostructure field effect transistor that includes the article.

A method for fabricating a non-planar heterostructure field effect transistor using group III-nitride materials with consistent repeatable results is disclosed. The method provides a substrate on which at least one layer of semiconductor material is deposited. An AlN layer is deposited on the at least one layer of semiconductor material. A portion of the AlN layer is removed using a solvent to create a non-planar region with consistent and repeatable results. The at least one layer beneath the AlN layer is insoluble in the solvent and therefore acts as an etch stop, preventing any damage to the at least one layer beneath the AlN layer. Furthermore, should the AlN layer incur any surface damage as a result of the reactive ion etching, the damage will be removed when exposed to the solvent to create the non-planar region.