32 results about "Semiconductor heterostructures" patented technology

Disclosed is a simple and scalable method for preparing a netted heterostructure of a thermoelectric material at a nanoscale. The preparation method involves shaking the nanomaterial of component B and component A in molten form in an inert environment, followed by controlled consolidation. A cellular network of component B with voids filled with component A forms a heterostructure B / A at nanoscale, where component A and component B may be a metal, a semiconductor or an insulator. Also disclosed are methods of improving the thermoelectric figure of merit (ZT) through the quantum confinement effect and methods of inverting its polarity by injecting carriers from a barrier layer in a nano-sized heterostructure. It is shown that ZTgt; ZTgt, ZTgt, ZTgt, ZTgt, ZTgt, ZTgt ', ZTgt', ZTgt ', ZTgt', ZTgt ', ZTgt' 2. The method of ZT enhancement is also applicable to semiconductor-semiconductor heterostructures as well as superlattice structures. The high ZT materials may be used for power generation, Peltier cooling and refrigeration, thermal infrared sensing and imaging, and thermal infrared display.

Semiconductor-superconductor hybrid devices with a horizontally-confined channel and methods of forming the same are described. An example semiconductor-superconductor hybrid device includes a semiconductor heterostructure formed over a substrate. The semiconductor-superconductor hybrid device may further include a superconducting layer formed over the semiconductor heterostructure. The semiconductor-superconductor hybrid device may further include a first gate, having a first top surface, formed adjacent to a first side of the semiconductor heterostructure. The semiconductor-superconductor hybrid device may further include a second gate, having a second top surface, formed adjacent to a second side, opposite to the first side, of the semiconductor heterostructure, where each of the first top surface of the first gate and the second top surface of the second gate is offset vertically from a selected surface of the semiconductor heterostructure by a predetermined offset amount.

The present disclosure provides for methods for designing and constructing metal / semiconductor heterostructures as catalysts for a wide range of applications such as oxygen activation. In a particular aspect, the present disclosure provides for the manipulation of atomic structures at M / TiO2 interface (e.g., Au / TiO2 interface) that significantly alters the interfacial electron distribution and prompts O2 activation. In an aspect, the present disclosure provides for a M / TiO2 composites (e.g., heterostructures) having a defect-free M / TiO2 interface and method of making the M / TiO2 composites having a defect-free M / TiO2 interface. The M can be Au, Ag, Cu, Al, Pt, Ni, or Pd, for example.

FIELD: microwave electronic devices.SUBSTANCE: in a low-noise microwave field-effect transistor on a semiconductor heterostructure, at least three quantum barrier layers of i-AlAs are additionally made, each with a thickness of 2-6 atomic monolayers, wherein each of said quantum barrier layers is located between the actual channel layer of InyGa1-yAs or a group of layers of the latter and the gate, wherein at least one quantum barrier layer is located between the doped layer and, or δ n-layer and the actual channel layer of InyGa1-yAs or a group of layers of the latter and at least one quantum barrier layer is located between the doped layer and, orδ n-layer and a gate, wherein the quantum barrier layers are separated from each other by at least one layer of narrow-band material AlxGa1-xAs, with a molar fraction of the chemical element Al x less than 0.4, with a thickness equal to or greater than 2 atomic monolayers, or a layer of GaAs, with a thickness equal to or greater than 2 atomic monolayers, between the actual channel layer InyGa1-yAs or a group of layers of the latter and the buffer layer, layers of GaAs, transition layers, quantum barrier layers i-AlAs, barrier layers, and layers doped with an acceptor impurity are made, on the last layer of the group of barrier layers, quantum barrier layers i-AlAs, barrier, transition and contact layers are made in a given sequence.EFFECT: increase in the gain factor and a reduction in the noise figure.1 cl, 1 dwg, 1 tbl

A method of operating a quantum processor (10) comprising a plurality of gate electrodes arranged on a semiconductor heterostructure, where the plurality of gate electrodes comprise transfer gate electrodes, the transfer gate electrode is configured to be provided with at least one voltage V to move at least one qubit arranged in the semiconductor heterostructure along at least one path to a manipulation region for manipulating the at least one qubit. The method comprises the steps of: calibrating at least one voltage V provided to the gate electrode; determining at least one fidelity FM or error symptom S associated with manipulating the at least one qubit in the manipulation zone; and adjusting the at least one voltage V.

The application relates to a band gap testing method and device of a semiconductor heterostructure, computer equipment, a storage medium and a computer program product. The method comprises the following steps: scanning a first semiconductor material sample by using a visible spectrophotometer with a preset wavelength range to obtain a corresponding diffuse reflection spectrum of the first semiconductor material sample; scanning the semiconductor heterostructure by using the visible spectrophotometer with the preset wavelength range to obtain a corresponding diffuse reflection spectrum of the semiconductor heterostructure; determining band gap information of the first semiconductor material sample according to the corresponding diffuse reflection spectrum of the first semiconductor material sample, and determining band gap information of the semiconductor heterostructure according to the corresponding diffuse reflection spectrum of the semiconductor heterostructure; and obtaining a band gap testing result of the semiconductor heterostructure according to the band gap information of the first semiconductor material sample and the band gap information of the semiconductor heterostructure. The method can improve the band gap testing accuracy of a two-dimensional material heterojunction.

A shuttle element for a quantum computer includes a plurality of gate electrodes arranged on a semiconductor heterostructure. The plurality of gate electrodes includes a shield gate for defining at least one path in the semiconductor heterostructure. The plurality of gate electrodes includes a transfer gate disposed at the at least one path. The transfer gate includes a subset of electrodes electrically disconnected from each other. The transfer gates of any one of the electrode subsets are electrically connected to each other. The finger gate is configured to be provided with at least one voltage V to move at least one qubit along at least one path.

A method for determining atomic structure uses a reverse machine-learning model (MLM) that is trained to transform images of spectral functions into atomic descriptors that describe a semiconductor heterostructure, superlattice, or bulk material. The method includes feeding, into a trained machine-learning model, an image of a spectral function of a semiconductor heterostructure. The trained machine-learning model, in response to being fed the image, outputs a set of atomic descriptors for one atom of a plurality of atoms forming a supercell of the semiconductor heterostructure. The set of atomic descriptors include an elemental descriptor that identifies an element type of the one atom. The set of atomic descriptors also include structural descriptors, each of which quantifies a structural relationship between (i) the one atom and (ii) one or more other atoms of the plurality of atoms forming the supercell. The reverse MLM may be implemented as a convolutional neural network.

A method of operating a quantum chip (10) using a microprocessor wherein the quantum chip comprises a semiconductor heterostructure (12) and a plurality of gate electrodes (50) arranged on the semiconductor heterostructure (12) for providing a plurality of shuttle channels (16) for moving a plurality of qubits along a plurality of paths (45); the plurality of gate electrodes (50) are further arranged to form a plurality of manipulation regions (20) and a plurality of T-junctions (18), any of the plurality of manipulation regions (20) comprising an interface (25) at which two of the plurality of shuttle channels (16) meet each other, and any of the plurality of T-junctions (18) comprising a junction (28) at which two of the plurality of shuttle channels (16) meet each other. One of the plurality of shuttle channels (16) is linked to another of the plurality of shuttle channels (16): the method comprising the steps of: calibrating voltage parameters relating to a voltage to be applied to the plurality of gate electrodes (50), one of the parameters relating to one of the plurality of gate electrodes (50); selecting a path (45s) along a selected shuttle channel (16-1, 16-2, 16-n) of the plurality of shuttle channels (16) between the position (S) of the qubit and the selected manipulation zone (20); determining, for any one of a selected shuttle channel (16-1, 16-2, 16-n) of the plurality of shuttle channels (16), at least one shuttle voltage time process to be applied to an associated subset (50i) of the plurality of gate electrodes (50) for moving the qubit from the current position to the selected manipulation zone (20) based on the voltage parameter; moving the qubit along a selected one of the plurality of shuttle channels (16-1, 16-2, 16-n) of the plurality of shuttle channels (16) from the current position (S) to the selected manipulation zone (20) by applying a shuttle voltage time process to a subset (50-1, 50-2, 50-n) of the plurality of gate electrodes (50) associated with the selected one of the plurality of shuttle channels (16-1, 16-2, 16-n); determining, for the selected manipulation region (20), a manipulation voltage-time process for manipulating qubits to be applied to an associated subset (50-n, 50-s) of the plurality of gate electrodes (50), based on the voltage parameter; and manipulating the qubits in the selected manipulation region (20) by applying at least one manipulation voltage time process to a subset (50-n, 50-s) of the plurality of gate electrodes (50) associated with the selected manipulation region (20).

The invention relates to an ultrafast laser welding method for a transparent hard and brittle material and a semiconductor heterogeneous material. The transparent hard and brittle material and the semiconductor heterogeneous material are assembled in a clamp according to an optical contact state; and ultrafast laser welding parameters are set, an ultrafast laser is adopted to emit laser beams, the laser beams penetrate through the transparent hard and brittle material to act on the interface between the transparent hard and brittle material and the semiconductor material, and scanning welding is completed. Compared with the prior art, the ultrafast laser interlayer-free direct connection technology of the heterogeneous transparent hard and brittle material and the semiconductor material is provided for the first time, thermal stress concentration is avoided by optimizing the scanning path, effective connection of the transparent hard and brittle material and the semiconductor material is successfully achieved, and a high-strength and high-precision connection joint is formed. Compared with a traditional connection technology, the method does not need high temperature, an intermediate layer or an external load, is simple and convenient to operate, has a narrow heat affected zone, and is suitable for the precise manufacturing field of MEMS packaging and the like.

A quantum device including superconducting-semiconducting qubits and coupler designs based on high-quality, compact through-silicon vias (TSVs). An interposer probe wafer containing TSVs is used to contact a sample wafer with, for example, a superconductor-proximitized, epitaxially-grown, germanium quantum well. By utilizing the capacitance of the probe wafer TSVs, the majority of the electric field in the qubits is pulled away from lossy regions that are present in the semiconducting wafer. The probe wafer can reduce the qubit's electric field participation in the sample wafer by an order of magnitude for thin substrates and remains small even when the epitaxial layer thickness approaches 100 μμm. This scheme is extensible to multi-qubit systems that have tunable qubit-qubit couplings without magnetic fields. This approach shrinks the on-chip footprint of voltage-tunable superconducting qubits and is applicable to super-semi heterostructures in a variety of systems.

The application discloses a method for improving intrinsic thermal conductivity of a semiconductor, and belongs to the technical field of the semiconductor, and discloses a semiconductor heterostructure which comprises a semiconductor material and a modified layer which are arranged in a laminated mode; an interface between the semiconductor material and the modified layer is a coherent hetero-interface; the semiconductor material and the modified layer are matched in acoustic phonons and are not matched in optical phonons; and the semiconductor material and the modified layer each independently comprises a III-V semiconductor material. The semiconductor heterostructure with the coherent hetero-interface is constructed, the phonon transport near the interface is in a non-equilibrium state, the phonon-phonon scattering process is regulated and controlled, the thermal resistance caused by high-order phonon scattering is reduced, the phonon relaxation time is prolonged, and the intrinsic thermal conductivity of the material is improved. The application only needs to utilize the interface engineering, does not need to introduce a new material, the preparation process of the semiconductor heterostructure is compatible with an existing chip preparation process, and the engineering has strong realizability.

An electrical device is provided, the device comprising: an n-channel metal–oxide– semiconductor, NMOS, transistor comprising a source, a body and a drain, wherein the body is an elongated semiconductor heterostructure configured for conduction of negative charge carriers, wherein the source and the drain are arranged on opposite distal regions of the body; and a p-channel metal–oxide–semiconductor, PMOS, transistor comprising a source, a body and a drain, wherein the body is an elongated semiconductor heterostructure configured for conduction of positive charge carriers, wherein the source and the drain are arranged on opposite distal regions of the body; wherein the bodies are arranged separated, in parallel and superimposed relative to each other. The NMOS transistor and the PMOS transistor of the electrical device are connected to form a circuit for a complementary metal–oxide– semiconductor, CMOS. A method of providing an electrical device and a CMOS are also provided.

The utility model relates to a device. A device includes: a semiconductor heterostructure including an active region and a non-active region, and having a channel layer of a high electron mobility transistor (HEMT); the GaN gate layer is located on the channel layer and comprises a first gate finger, a second gate finger and a gate arc connected with the first gate finger and the second gate finger; and a source region between the first and second gate fingers and in contact with the channel layer therebetween, where the channel layer has a higher concentration of isolation dopant species in the non-active region than in the active region, where the entire gate arc is located directly above the active region.

The application discloses a kind of color image sensor based on two-dimensional semiconductor heterostructure and its application in image convolution processing.The device contains deposited on substrate bipolar two-dimensional semiconductor and N-type two-dimensional semiconductor, which form horizontal heterojunction structure.By adjusting back gate voltage, the energy band arrangement of heterojunction is controlled, and a continuously variable spectral response function is realized, so that multi-band image information can be obtained without color filter.Meanwhile, by source-drain voltage, the photocurrent response of heterojunction is controlled, and then the output signal is given different weights.Several heterojunctions with the same size as the convolution kernel are connected in parallel, and the sum of the currents read is mapped to the gray value, and the convolved image under this waveband can be obtained.By applying convolution operation under different wavebands respectively, image convolution processing can be completed.The device performs well in integrated image acquisition and convolution calculation, effectively reduces the computing resource overhead, and significantly improves the image processing efficiency.

The present application relates to a kind of graphene nanobelt / copper selenide semiconductor heterostructure and its preparation method, belong to nanometer material technical field.The present application utilizes the strategy that intermolecular carbon hydrogen activation and intramolecular cyclization dehydrogenation will occur under the catalysis of four anthracene precursor in copper substrate, four anthracene precursor molecule is deposited on copper surface, and is kept at 100 ℃-400 ℃ temperature for 30 minutes to obtain one-dimensional graphene nanobelt.Then, the strategy that single-layer copper selenide semiconductor is generated by the chemical reaction of selenium powder and copper substrate is used, by depositing selenium powder on the above graphene nanobelt and copper substrate, and keeping at 100 ℃-400 ℃ temperature for 30 minutes, to obtain graphene nanobelt / copper selenide semiconductor heterostructure.

The invention relates to a method for improving catalytic hydrogen production performance by introducing anion vacancies into an Au / semiconductor heterostructure through electrochemical treatment, and belongs to the technical field of catalytic energy. According to the method, gold nanoparticles are used and loaded on semiconductor particles through sputtering, finally, electrochemical treatment is carried out on the composite material, anion vacancies are introduced, and a sample (called a Vc-Au / semiconductor) heterostructure obtained after electrochemical treatment is formed. In the electro-catalysis process, local electron enrichment of anion vacancies can promote high catalytic activity of the catalyst in electro-catalysis hydrogen evolution (HER). When different semiconductors are replaced for loading gold nanoparticles and anion vacancies are introduced through electrochemical treatment, obvious HER activity enhancement is shown. The smooth implementation of the invention provides a universal, simple, convenient and efficient strategy for regulating and controlling the efficiency of the electro-catalytic hydrogen production reaction, solves the problems of high temperature and high energy consumption caused by introducing vacancies in a traditional heat treatment mode, and provides greater possibility for industrialization in the field of electro-catalytic hydrogen production.

A HEMT transistor includes a semiconductor body having a semiconductor heterostructure. A gate region of conductive material is disposed on and in contact with the semiconductor body. A first insulating layer laterally extends over the semiconductor body to the conductive gate region. A second insulating layer extends over the first insulating layer and the gate region. A first field plate region of conductive material extends between the first and second insulating layers, laterally separated from the conductive gate region along a first direction. A second field plate region of conductive material extends over the second insulating layer, and the second field plate region covers and is vertically aligned with the first field plate region.

A method of operating a quantum chip (10) using a microprocessor wherein the quantum chip comprises a semiconductor heterostructure (12) and a plurality of gate electrodes (50) arranged on the semiconductor heterostructure (12) for providing a plurality of shuttle channels (16) for moving a plurality of qubits along a plurality of paths (45); the plurality of gate electrodes (50) are further arranged to form a plurality of manipulation regions (20) and a plurality of T-junctions (18), any of the plurality of manipulation regions (20) comprising an interface (25) at which two of the plurality of shuttle channels (16) meet each other, and any of the plurality of T-junctions (18) comprising a junction (28) at which two of the plurality of shuttle channels (16) meet each other. One of the plurality of shuttle channels (16) is linked to another of the plurality of shuttle channels (16): the method comprising the steps of: calibrating voltage parameters relating to a voltage to be applied to the plurality of gate electrodes (50), one of the parameters relating to one of the plurality of gate electrodes (50); selecting a path (45s) along a selected shuttle channel (16-1, 16-2, 16-n) of the plurality of shuttle channels (16) between the position (S) of the qubit and the selected manipulation zone (20); determining, for any one of a selected shuttle channel (16-1, 16-2, 16-n) of the plurality of shuttle channels (16), at least one shuttle voltage time process to be applied to an associated subset (50i) of the plurality of gate electrodes (50) for moving the qubit from the current position to the selected manipulation zone (20) based on the voltage parameter; moving the qubit along a selected one of the plurality of shuttle channels (16-1, 16-2, 16-n) of the plurality of shuttle channels (16) from the current position (S) to the selected manipulation zone (20) by applying a shuttle voltage time process to a subset (50-1, 50-2, 50-n) of the plurality of gate electrodes (50) associated with the selected one of the plurality of shuttle channels (16-1, 16-2, 16-n); based on the voltage parameter, determining, for the selected manipulation region (20), a manipulation voltage-time process for manipulating qubits to be applied to an associated subset (50-n, 50-s) of the plurality of gate electrodes (50); and manipulating the qubits in the selected manipulation region (20) by applying at least one manipulation voltage time process to a subset (50-n, 50-s) of the plurality of gate electrodes (50) associated with the selected manipulation region (20).

Semiconductor-superconductor hybrid devices with a horizontally-confined channel and methods of forming the same are described. An example semiconductor-superconductor hybrid device includes a semiconductor heterostructure formed over a substrate. The semiconductor-superconductor hybrid device may further include a superconducting layer formed over the semiconductor heterostructure. The semiconductor-superconductor hybrid device may further include a first gate, having a first top surface, formed adjacent to a first side of the semiconductor heterostructure. The semiconductor-superconductor hybrid device may further include a second gate, having a second top surface, formed adjacent to a second side, opposite to the first side, of the semiconductor heterostructure, where each of the first top surface of the first gate and the second top surface of the second gate is offset vertically from a selected surface of the semiconductor heterostructure by a predetermined offset amount.

A method of operating a quantum processor comprising a plurality of gate electrodes arranged on a semiconductor heterostructure is disclosed, wherein the plurality of gate electrodes are to be provided with at least one voltage to perform at least one action on at least one qubit arranged in the semiconductor heterostructure. The method comprises the steps of: calibrating the at least one voltage V; determining at least one fidelity F of the quantum processor; analyzing at least one measurement relating to determining the fidelity F; identifying at least one fidelity reduction site; and adjusting the at least one voltage V.

Per-and polyfluoroalkyl substances (PFAS) are persistent contaminants that pose significant environmental and health risks. This invention introduces a semiconductor heterostructure material under visible light for PFAS degradation in aqueous matrices. Utilizing hexagonal boron nitride (h-BN) and zirconium dioxide (ZrO2), the heterostructure enhances charge separation and light absorption, enabling efficient PFAS mineralization under visible light. The invention offers a cost-effective and sustainable solution for PFAS remediation in wastewater treatment, stormwater management, and industrial effluents. By destroying rather than removing PFAS, the heterostructure provides a transformative advancement in environmental cleanup.

This invention belongs to the field of chip thermal management technology and discloses a method for simulating thermal transport at semiconductor heterostructure interfaces using micro / nanostructures. The method includes: defining the basic conditions such as the heterostructure system and interface type, setting optimization objectives and evaluation indicators; then, parameterizing the interface micro / nanostructure based on a morphology parameter database and establishing a three-dimensional geometric model; constructing a phonon parameter library using first-principles calculations; solving the phonon Boltzmann transport equation using the Monte Carlo method; simulating phonon transport and calculating thermal indicators; generating a simulation dataset under manufacturing constraints; training a neural network surrogate model based on the dataset to establish a fast mapping between morphology parameters and thermal indicators; using a genetic algorithm for global search to output a candidate solution set; finally, verifying prediction errors through high-fidelity solving, selecting high-confidence candidate solutions, and verifying the heat transfer performance of the candidate solutions. This invention provides a precise solution for enhancing heat transfer at semiconductor heterostructure interfaces, improving device thermal performance and reliability.

Gate-controlled quantum dots based on silicon-germanium (SiGe) alloy heterostructures are provided. Also provided are quantum computing systems incorporating the gate-controlled quantum dots. The quantum dots are formed in a semiconductor heterostructure in which a SiGe alloy quantum well is sandwiched between SiGe alloy barriers or between Ge barriers. The presence of germanium in the quantum dots increases the average valley splitting for quantum dots confined in the SiGe. As a result, the yield of quantum dots having a sufficiently high valley splitting for device applications is increased by the use of a SiGe alloy in the quantum well.

A semiconductor heterostructure for an optoelectronic device with improved light emission is disclosed. The heterostructure can include a first semiconductor layer having a first index of refraction n1. A second semiconductor layer can be located over the first semiconductor layer. The second semiconductor layer can include a laminate of semiconductor sublayers having an effective index of refraction n2. A third semiconductor layer having a third index of refraction n3 can be located over the second semiconductor layer. The first index of refraction n1 is greater than the second index of refraction n2, which is greater than the third index of refraction n3.

A method of operating a quantum chip using a microprocessor is disclosed. The quantum chip includes a semiconductor heterostructure and a plurality of gate electrodes arranged on the semiconductor heterostructure for providing a plurality of shuttle channels for moving a plurality of qubits along a plurality of paths. The plurality of gate electrodes are further arranged to form a plurality of manipulation regions and a plurality of T-junctions, any one of the plurality of manipulation regions comprising an interface at which two of the plurality of shuttle channels meet each other, and any one of the plurality of T-junctions comprising a junction at which two of the shuttle channels meet each other. One of the plurality of shuttle channels is coupled to another of the plurality of shuttle channels. The method includes: selecting a path along a selected shuttle lane of the plurality of shuttle lanes between a start position and an end position; a fidelity associated with shuttling the qubit along the path is estimated based on a predetermined shuttling fidelity associated with at least one of selected shuttling channels of the plurality of shuttling channels.

The invention discloses a longitudinal spatial analysis method for a multi-quantum well semiconductor element, and the method comprises the steps: carrying out the ion sputtering etching of the surface of the semiconductor element in an inclined direction through TOF-SIMS till a template layer of the semiconductor element is etched; determining an area where the etching pit is located based on a super-resolution microscope, and carrying out Raman spectrum and photoluminescence spectrum measurement; and determining corresponding areas of the cover plate layer, the quantum well layer and the template layer on the spectrogram to obtain a longitudinal space spectrum analysis diagram. According to the invention, the optical performance characterization analysis of the longitudinal space of the semiconductor element is realized, the fine spatial resolution capability of an ultrahigh vacuum optical system and the sensitive detection capability of a time-of-flight secondary ion mass spectrometer can be brought into full play, and the characterization effect of associating the material structure with the luminescence performance is realized; the method has universality and can be applied to characterization of optical characteristics of quantum wells, quantum dots and other types of epitaxial growth semiconductor heterostructures.

A T-junction for a quantum processor includes a plurality of gate electrodes arranged on a semiconductor heterostructure. The plurality of gate electrodes includes a first transfer gate disposed at the at least one path and a second transfer gate disposed at the branch. The branch and the at least one path are arranged substantially perpendicular to each other and meet at a junction. The first transfer gate and the second transfer gate are configured to be supplied with at least one voltage V. The first and second transfer gates are configured to move at least one qubit disposed in the semiconductor heterostructure along the at least one path and / or along the branch, and to divert the at least one qubit from the at least one path into the branch or from the branch into the at least one path.

The present disclosure provides for methods for designing and constructing metal / semiconductor heterostructures as catalysts for a wide range of applications such as oxygen activation. In a particular aspect, the present disclosure provides for the manipulation of atomic structures at MJ / TiO2 interface (e.g., Au / TiO2 interface) that significantly alters the interfacial electron distribution and prompts O2 activation. In an aspect, the present disclosure provides for a M / TiO2 composites (e.g., heterostructures) having a N defect-free M / TiO2 interface and method of making the M / TiO2 composites having a defect-free M / TiO2 interface. The M can be Au, Ag, Cu, Al, Pt, Ni, or Pd, for example.

Semiconductor heterostructures having an engineered polarization. Semiconductor materials having specified crystallographic directions and specified polarizations are directly bonded to one another by means of atomic layer bonding without the use of any interfacial bonding materials, where spontaneous polarization of the two layers produced by joining the two materials by direct wafer bonding produces a strong 2DEG or 2DHG at the interface. Embodiments include GaN / AlN and AlN / GaN heterostructures having an N- or Ga-polar GaN layer directly bonded to an N- or Al-polar Al layer. Other embodiments can incorporate an InN epitaxial layer or an alloy incorporating an N-polar, Al-polar, or Ga-polar material having In, Al, or Ga in the crystal lattice, e.g., (InxAl1-xN), InxGa1-xN, AlxGa1-xN, InxAlyGa1-x-yN, where (0<x≤1, 0<y≤1, 0<x+y≤1).