64 results about "Semiconductor heterostructures" patented technology

The present invention belongs to the technical field of insulating materials, and specifically relates to an insulating material and a preparation method and application thereof. The insulating material provided by the present invention comprises the following components by mass: 100 parts of polyethylene, 0.01 to 1 parts of core-shell quantum dots, 0.5 to 2 parts of peroxide crosslinking agents and 0.5 to 2 parts of antioxidants. In the present invention, the contact interface formed by the core layer and the shell layer of the core-shell quantum dots belongs to the n-n type semiconductor heterostructure contact; the core-shell interface of the core-shell quantum dots themselves provides a confinement effect on electron carriers, and the interface between the shell layer and the insulating matrix provides a confinement effect on hole carriers; and the confinement effect gradually increases with the increase in the difference in band gap between the core layer and the shell layer of the quantum dots, thereby limiting the migration of carriers under high temperature and strong field, inhibiting the accumulation of space charges, and thus improving the insulation performance of the insulating material under high temperature and strong electric field conditions.

A method includes of fabricating a heterostructure includes growing epitaxially, in a growth chamber, a first semiconductor layer of the heterostructure, the first semiconductor layer comprising a III-nitride semiconductor material, the first semiconductor layer being supported by a substrate, and, after growing the first semiconductor layer, growing epitaxially, in the growth chamber, a second semiconductor layer of the heterostructure such that the second semiconductor layer is supported by the first semiconductor layer, the second semiconductor layer comprising a quaternary or higher order III-nitride alloy. The quaternary or higher order III-nitride alloy comprises a group IIIB element

A semiconductor heterostructure for an optoelectronic device with improved light emission is disclosed. The heterostructure can include a first semiconductor layer having a first index of refraction n1. A second semiconductor layer can be located over the first semiconductor layer. The second semiconductor layer can include a laminate of semiconductor sublayers having an effective index of refraction n2. A third semiconductor layer having a third index of refraction n3 can be located over the second semiconductor layer. The first index of refraction n1 is greater than the second index of refraction n2, which is greater than the third index of refraction n3.

The invention discloses a color image sensor based on a two-dimensional semiconductor heterostructure and application of the color image sensor in image convolution processing. The device comprises a bipolar two-dimensional semiconductor and an N-type two-dimensional semiconductor which are deposited on a substrate, and the bipolar two-dimensional semiconductor and the N-type two-dimensional semiconductor form a horizontal heterojunction structure. By adjusting the voltage of the back gate, the energy band arrangement of the heterojunction is controlled, a spectral response function capable of continuously changing is realized, and image information under multiple wavebands can be obtained without a color filter. Meanwhile, the photocurrent response of heterojunctions is regulated and controlled through source and drain voltages, then different weights are given to output signals, a plurality of heterojunctions with the same size as a convolution kernel are connected in parallel, and the sum of read currents is mapped into a gray value, so that a convoluted image under the wave band can be obtained. And image convolution processing can be completed by respectively applying convolution operation under different wavebands. The device has excellent performance in the aspects of integrated image acquisition and convolution calculation, effectively reduces the cost of calculation resources, and remarkably improves the image processing efficiency.

Disclosed is a simple and scalable method for preparing a netted heterostructure of a thermoelectric material at a nanoscale. The preparation method involves shaking the nanomaterial of component B and component A in molten form in an inert environment, followed by controlled consolidation. A cellular network of component B with voids filled with component A forms a heterostructure B / A at nanoscale, where component A and component B may be a metal, a semiconductor or an insulator. Also disclosed are methods of improving the thermoelectric figure of merit (ZT) through the quantum confinement effect and methods of inverting its polarity by injecting carriers from a barrier layer in a nano-sized heterostructure. It is shown that ZTgt; ZTgt, ZTgt, ZTgt, ZTgt, ZTgt, ZTgt ', ZTgt', ZTgt ', ZTgt', ZTgt ', ZTgt' 2. The method of ZT enhancement is also applicable to semiconductor-semiconductor heterostructures as well as superlattice structures. The high ZT materials may be used for power generation, Peltier cooling and refrigeration, thermal infrared sensing and imaging, and thermal infrared display.

Semiconductor-superconductor hybrid devices with a horizontally-confined channel and methods of forming the same are described. An example semiconductor-superconductor hybrid device includes a semiconductor heterostructure formed over a substrate. The semiconductor-superconductor hybrid device may further include a superconducting layer formed over the semiconductor heterostructure. The semiconductor-superconductor hybrid device may further include a first gate, having a first top surface, formed adjacent to a first side of the semiconductor heterostructure. The semiconductor-superconductor hybrid device may further include a second gate, having a second top surface, formed adjacent to a second side, opposite to the first side, of the semiconductor heterostructure, where each of the first top surface of the first gate and the second top surface of the second gate is offset vertically from a selected surface of the semiconductor heterostructure by a predetermined offset amount.

A semiconductor device and a method for manufacturing the same are provided in this disclosure. The semiconductor device includes a semiconductor heterostructure layer. The semiconductor heterostructure layer includes alternating first semiconductor material layers and second semiconductor material layers. Two-dimensional hole gas (2DHG) may be generated between each first semiconductor material layer and adjacent second semiconductor material layer. A conductive structure, including a plurality of conductive fingers extends from a surface of the semiconductor heterostructure layer into the semiconductor heterostructure layer. The plurality of conductive fingers are arranged in a direction substantially parallel to the surface. The lengths of the plurality of conductive fingers progressively increase in that direction so that an end portion of each conductive finger is respectively positioned in a different first semiconductor material layer and is in contact with the 2DHG.

A process for forming a high electron mobility transistor (HEMT) includes forming a semiconductor heterostructure including a channel layer of the HEMT, forming a gate (150) layer of GaN on the channel layer, and patterning the gate layer to form a first gate finger, a second gate finger, and a gate arc connecting the first gate finger and the second gate finger. The process includes forming an isolation mask covering an active region of the semiconductor heterostructure and the gate arc and performing an ion bombardment process on an inactive region (142) of the semiconductor heterostructure exposed by the isolation mask.

The present disclosure provides for methods for designing and constructing metal / semiconductor heterostructures as catalysts for a wide range of applications such as oxygen activation. In a particular aspect, the present disclosure provides for the manipulation of atomic structures at M / TiO2 interface (e.g., Au / TiO2 interface) that significantly alters the interfacial electron distribution and prompts O2 activation. In an aspect, the present disclosure provides for a M / TiO2 composites (e.g., heterostructures) having a defect-free M / TiO2 interface and method of making the M / TiO2 composites having a defect-free M / TiO2 interface. The M can be Au, Ag, Cu, Al, Pt, Ni, or Pd, for example.

An HEMT transistor includes a semiconductor body having a semiconductive heterostructure. A gate region, of conductive material, is arranged above and in contact with the semiconductor body. A first insulating layer extends over the semiconductor body, laterally to the conductive gate region. A second insulating layer extends over the first insulating layer and the gate region. A first field plate region, of conductive material, extends between the first and the second insulating layers, laterally spaced from the conductive gate region along a first direction. A second field plate region, of conductive material, extends over the second insulating layer, and the second field plate region overlies and is vertically aligned with the first field plate region.

FIELD: microwave electronic devices.SUBSTANCE: in a low-noise microwave field-effect transistor on a semiconductor heterostructure, at least three quantum barrier layers of i-AlAs are additionally made, each with a thickness of 2-6 atomic monolayers, wherein each of said quantum barrier layers is located between the actual channel layer of InyGa1-yAs or a group of layers of the latter and the gate, wherein at least one quantum barrier layer is located between the doped layer and, or δ n-layer and the actual channel layer of InyGa1-yAs or a group of layers of the latter and at least one quantum barrier layer is located between the doped layer and, orδ n-layer and a gate, wherein the quantum barrier layers are separated from each other by at least one layer of narrow-band material AlxGa1-xAs, with a molar fraction of the chemical element Al x less than 0.4, with a thickness equal to or greater than 2 atomic monolayers, or a layer of GaAs, with a thickness equal to or greater than 2 atomic monolayers, between the actual channel layer InyGa1-yAs or a group of layers of the latter and the buffer layer, layers of GaAs, transition layers, quantum barrier layers i-AlAs, barrier layers, and layers doped with an acceptor impurity are made, on the last layer of the group of barrier layers, quantum barrier layers i-AlAs, barrier, transition and contact layers are made in a given sequence.EFFECT: increase in the gain factor and a reduction in the noise figure.1 cl, 1 dwg, 1 tbl

A method is provided for preparing a semiconductor wafer for fabricating a semiconductor heterostructure device, or for fabricating the semiconductor heterostructure device on the semiconductor wafer. The method comprises dry etching at least one epitaxial layer to produce a dry-etched semiconductor wafer defining a mesa structure. Then, an etchant gas is flowed through a reaction chamber to remove material from sidewalls of the mesa structure and thereby produce a cleaned semiconductor wafer in which the sidewalls of the mesa structure undercut a mask layer and have reduced surface defects in comparison to the sidewalls of the mesa structure of the dry-etched semiconductor wafer. Then, an overgrowth layer is grown on the sidewalls of the mesa structure of the cleaned semiconductor wafer.

A method of operating a quantum processor (10) comprising a plurality of gate electrodes arranged on a semiconductor heterostructure, where the plurality of gate electrodes comprise transfer gate electrodes, the transfer gate electrode is configured to be provided with at least one voltage V to move at least one qubit arranged in the semiconductor heterostructure along at least one path to a manipulation region for manipulating the at least one qubit. The method comprises the steps of: calibrating at least one voltage V provided to the gate electrode; determining at least one fidelity FM or error symptom S associated with manipulating the at least one qubit in the manipulation zone; and adjusting the at least one voltage V.

The application relates to a band gap testing method and device of a semiconductor heterostructure, computer equipment, a storage medium and a computer program product. The method comprises the following steps: scanning a first semiconductor material sample by using a visible spectrophotometer with a preset wavelength range to obtain a corresponding diffuse reflection spectrum of the first semiconductor material sample; scanning the semiconductor heterostructure by using the visible spectrophotometer with the preset wavelength range to obtain a corresponding diffuse reflection spectrum of the semiconductor heterostructure; determining band gap information of the first semiconductor material sample according to the corresponding diffuse reflection spectrum of the first semiconductor material sample, and determining band gap information of the semiconductor heterostructure according to the corresponding diffuse reflection spectrum of the semiconductor heterostructure; and obtaining a band gap testing result of the semiconductor heterostructure according to the band gap information of the first semiconductor material sample and the band gap information of the semiconductor heterostructure. The method can improve the band gap testing accuracy of a two-dimensional material heterojunction.

A shuttle element for a quantum computer includes a plurality of gate electrodes arranged on a semiconductor heterostructure. The plurality of gate electrodes includes a shield gate for defining at least one path in the semiconductor heterostructure. The plurality of gate electrodes includes a transfer gate disposed at the at least one path. The transfer gate includes a subset of electrodes electrically disconnected from each other. The transfer gates of any one of the electrode subsets are electrically connected to each other. The finger gate is configured to be provided with at least one voltage V to move at least one qubit along at least one path.

A method for determining atomic structure uses a reverse machine-learning model (MLM) that is trained to transform images of spectral functions into atomic descriptors that describe a semiconductor heterostructure, superlattice, or bulk material. The method includes feeding, into a trained machine-learning model, an image of a spectral function of a semiconductor heterostructure. The trained machine-learning model, in response to being fed the image, outputs a set of atomic descriptors for one atom of a plurality of atoms forming a supercell of the semiconductor heterostructure. The set of atomic descriptors include an elemental descriptor that identifies an element type of the one atom. The set of atomic descriptors also include structural descriptors, each of which quantifies a structural relationship between (i) the one atom and (ii) one or more other atoms of the plurality of atoms forming the supercell. The reverse MLM may be implemented as a convolutional neural network.

A method of operating a quantum chip (10) using a microprocessor wherein the quantum chip comprises a semiconductor heterostructure (12) and a plurality of gate electrodes (50) arranged on the semiconductor heterostructure (12) for providing a plurality of shuttle channels (16) for moving a plurality of qubits along a plurality of paths (45); the plurality of gate electrodes (50) are further arranged to form a plurality of manipulation regions (20) and a plurality of T-junctions (18), any of the plurality of manipulation regions (20) comprising an interface (25) at which two of the plurality of shuttle channels (16) meet each other, and any of the plurality of T-junctions (18) comprising a junction (28) at which two of the plurality of shuttle channels (16) meet each other. One of the plurality of shuttle channels (16) is linked to another of the plurality of shuttle channels (16): the method comprising the steps of: calibrating voltage parameters relating to a voltage to be applied to the plurality of gate electrodes (50), one of the parameters relating to one of the plurality of gate electrodes (50); selecting a path (45s) along a selected shuttle channel (16-1, 16-2, 16-n) of the plurality of shuttle channels (16) between the position (S) of the qubit and the selected manipulation zone (20); determining, for any one of a selected shuttle channel (16-1, 16-2, 16-n) of the plurality of shuttle channels (16), at least one shuttle voltage time process to be applied to an associated subset (50i) of the plurality of gate electrodes (50) for moving the qubit from the current position to the selected manipulation zone (20) based on the voltage parameter; moving the qubit along a selected one of the plurality of shuttle channels (16-1, 16-2, 16-n) of the plurality of shuttle channels (16) from the current position (S) to the selected manipulation zone (20) by applying a shuttle voltage time process to a subset (50-1, 50-2, 50-n) of the plurality of gate electrodes (50) associated with the selected one of the plurality of shuttle channels (16-1, 16-2, 16-n); determining, for the selected manipulation region (20), a manipulation voltage-time process for manipulating qubits to be applied to an associated subset (50-n, 50-s) of the plurality of gate electrodes (50), based on the voltage parameter; and manipulating the qubits in the selected manipulation region (20) by applying at least one manipulation voltage time process to a subset (50-n, 50-s) of the plurality of gate electrodes (50) associated with the selected manipulation region (20).

The aim of the present beam source is to develop a positron µbeam, which permits it to be the first attempt to describe e+ as beam / current as Pump / Injection semiconductor devices. The concept of type I: positron beam source is to be an alternative source to electron beam and to harness the generation of γ-ray radiations inside the semiconductor heterostructures. Also, type II: Weyl fermions for its high mobility are described how they used a beam of antimatter particles to not only examine for defects in a semiconductor as well as for semiconductor devices injection. Type I: the positron beam's high energies (up to several hundred keV or even tens of MeV), but the limit should follow the same electron range because it is possible to convert an electron into a positron and use either one as a source for pumping materials. This will prevent defects from forming in positron-pumped materials, which would cause a rapid degradation of the materials properties. Type II: the transformation to Weyl fermions, which are considered to carry electric charge via a device far more quickly than ordinary electrons. Weyl electrons are considered to transfer electric current at least twice as quickly as graphene electrons and at least 1,000 times faster than electrons in ordinary semiconductors, according to the most recent studies. In an effort to further this field of study, this patent is harnessing the Weyl electrons as beam / current in Pump / Injection semiconductor devices.

The invention relates to an ultrafast laser welding method for a transparent hard and brittle material and a semiconductor heterogeneous material. The transparent hard and brittle material and the semiconductor heterogeneous material are assembled in a clamp according to an optical contact state; and ultrafast laser welding parameters are set, an ultrafast laser is adopted to emit laser beams, the laser beams penetrate through the transparent hard and brittle material to act on the interface between the transparent hard and brittle material and the semiconductor material, and scanning welding is completed. Compared with the prior art, the ultrafast laser interlayer-free direct connection technology of the heterogeneous transparent hard and brittle material and the semiconductor material is provided for the first time, thermal stress concentration is avoided by optimizing the scanning path, effective connection of the transparent hard and brittle material and the semiconductor material is successfully achieved, and a high-strength and high-precision connection joint is formed. Compared with a traditional connection technology, the method does not need high temperature, an intermediate layer or an external load, is simple and convenient to operate, has a narrow heat affected zone, and is suitable for the precise manufacturing field of MEMS packaging and the like.

Structures that maximize the utilization of a substrate are disclosed. A device of these teachings includes a substrate having two opposing surfaces, at least one semiconductor heterostructure epitaxially grown on one surface of the two opposing surfaces of the substrate, and at least another semiconductor heterostructure epitaxially grown on a surface of the substrate opposite to the one surface. Methods for fabricating the device are also disclosed.

A quantum device including superconducting-semiconducting qubits and coupler designs based on high-quality, compact through-silicon vias (TSVs). An interposer probe wafer containing TSVs is used to contact a sample wafer with, for example, a superconductor-proximitized, epitaxially-grown, germanium quantum well. By utilizing the capacitance of the probe wafer TSVs, the majority of the electric field in the qubits is pulled away from lossy regions that are present in the semiconducting wafer. The probe wafer can reduce the qubit's electric field participation in the sample wafer by an order of magnitude for thin substrates and remains small even when the epitaxial layer thickness approaches 100 μμm. This scheme is extensible to multi-qubit systems that have tunable qubit-qubit couplings without magnetic fields. This approach shrinks the on-chip footprint of voltage-tunable superconducting qubits and is applicable to super-semi heterostructures in a variety of systems.

The application discloses a method for improving intrinsic thermal conductivity of a semiconductor, and belongs to the technical field of the semiconductor, and discloses a semiconductor heterostructure which comprises a semiconductor material and a modified layer which are arranged in a laminated mode; an interface between the semiconductor material and the modified layer is a coherent hetero-interface; the semiconductor material and the modified layer are matched in acoustic phonons and are not matched in optical phonons; and the semiconductor material and the modified layer each independently comprises a III-V semiconductor material. The semiconductor heterostructure with the coherent hetero-interface is constructed, the phonon transport near the interface is in a non-equilibrium state, the phonon-phonon scattering process is regulated and controlled, the thermal resistance caused by high-order phonon scattering is reduced, the phonon relaxation time is prolonged, and the intrinsic thermal conductivity of the material is improved. The application only needs to utilize the interface engineering, does not need to introduce a new material, the preparation process of the semiconductor heterostructure is compatible with an existing chip preparation process, and the engineering has strong realizability.

An electrical device is provided, the device comprising: an n-channel metal–oxide– semiconductor, NMOS, transistor comprising a source, a body and a drain, wherein the body is an elongated semiconductor heterostructure configured for conduction of negative charge carriers, wherein the source and the drain are arranged on opposite distal regions of the body; and a p-channel metal–oxide–semiconductor, PMOS, transistor comprising a source, a body and a drain, wherein the body is an elongated semiconductor heterostructure configured for conduction of positive charge carriers, wherein the source and the drain are arranged on opposite distal regions of the body; wherein the bodies are arranged separated, in parallel and superimposed relative to each other. The NMOS transistor and the PMOS transistor of the electrical device are connected to form a circuit for a complementary metal–oxide– semiconductor, CMOS. A method of providing an electrical device and a CMOS are also provided.

HEMT transistor of the normally off type, having: - a semiconductor heterostructure (4, 6, 200) comprising at least a first layer (4) and a second layer (6), the second layer being arranged on top of the first layer, the first layer (4) being different from the second layer (6), and the first layer (4) being in direct contact with the second layer (6); - a trench (15) extending through the second layer and a region of the first layer; - a gate region (10) of conductive material extending into the trench; and - a dielectric region (18) extending into the trench and in contact with the semiconductor heterostructure; wherein the dielectric region (18) is arranged between the gate region and the semiconductor heterostructure; wherein a part of the trench is laterally bounded by a lateral structure (LS) comprising at least one first step (P b1 , P 11 , P b2 ), wherein the lateral structure (LS) has a stair-step shape; and wherein the semiconductor heterostructure has a first edge (E 1 ) and a second edge (E 2 ) of the first stage, wherein the first edge and the second edge are formed by the first layer; wherein the lateral structure (LS) further forms more than two steps, wherein a second step has a third edge (E 3 ) and a fourth edge (E 4 ; E x1 ), wherein the third edge is formed by the first layer (4) and the fourth edge is formed by the second layer (6) and is arranged above the third edge.

A method for synthesizing noble metal-semiconductor heterostructures includes the following steps S1 to S6. Step S1: noble metal seeds are formed. Step S2: at least one metal precursors including a first metal and a first solvent are mixed in a first reactor chamber, so as to obtain a first solution comprising a first mixture. Step S3: the first solution is heated with a first heating process, so as to obtain a transparent solution. Step S4: the noble metal seeds, the transparent solution, and a second solvent are mixed, so as to obtain a second solution. Step S5: the second solution is heated with a second heating process to grow a semiconductor structure containing the first metal on the noble metal seeds, thereby forming the noble metal-semiconductor heterostructures therein. Also, a photocatalytic system including the aforesaid noble metal-semiconductor heterostructures is provided.

The utility model relates to a device. A device includes: a semiconductor heterostructure including an active region and a non-active region, and having a channel layer of a high electron mobility transistor (HEMT); the GaN gate layer is located on the channel layer and comprises a first gate finger, a second gate finger and a gate arc connected with the first gate finger and the second gate finger; and a source region between the first and second gate fingers and in contact with the channel layer therebetween, where the channel layer has a higher concentration of isolation dopant species in the non-active region than in the active region, where the entire gate arc is located directly above the active region.

The application discloses a kind of color image sensor based on two-dimensional semiconductor heterostructure and its application in image convolution processing.The device contains deposited on substrate bipolar two-dimensional semiconductor and N-type two-dimensional semiconductor, which form horizontal heterojunction structure.By adjusting back gate voltage, the energy band arrangement of heterojunction is controlled, and a continuously variable spectral response function is realized, so that multi-band image information can be obtained without color filter.Meanwhile, by source-drain voltage, the photocurrent response of heterojunction is controlled, and then the output signal is given different weights.Several heterojunctions with the same size as the convolution kernel are connected in parallel, and the sum of the currents read is mapped to the gray value, and the convolved image under this waveband can be obtained.By applying convolution operation under different wavebands respectively, image convolution processing can be completed.The device performs well in integrated image acquisition and convolution calculation, effectively reduces the computing resource overhead, and significantly improves the image processing efficiency.

The present application relates to a kind of graphene nanobelt / copper selenide semiconductor heterostructure and its preparation method, belong to nanometer material technical field.The present application utilizes the strategy that intermolecular carbon hydrogen activation and intramolecular cyclization dehydrogenation will occur under the catalysis of four anthracene precursor in copper substrate, four anthracene precursor molecule is deposited on copper surface, and is kept at 100 ℃-400 ℃ temperature for 30 minutes to obtain one-dimensional graphene nanobelt.Then, the strategy that single-layer copper selenide semiconductor is generated by the chemical reaction of selenium powder and copper substrate is used, by depositing selenium powder on the above graphene nanobelt and copper substrate, and keeping at 100 ℃-400 ℃ temperature for 30 minutes, to obtain graphene nanobelt / copper selenide semiconductor heterostructure.

The invention relates to a method for improving catalytic hydrogen production performance by introducing anion vacancies into an Au / semiconductor heterostructure through electrochemical treatment, and belongs to the technical field of catalytic energy. According to the method, gold nanoparticles are used and loaded on semiconductor particles through sputtering, finally, electrochemical treatment is carried out on the composite material, anion vacancies are introduced, and a sample (called a Vc-Au / semiconductor) heterostructure obtained after electrochemical treatment is formed. In the electro-catalysis process, local electron enrichment of anion vacancies can promote high catalytic activity of the catalyst in electro-catalysis hydrogen evolution (HER). When different semiconductors are replaced for loading gold nanoparticles and anion vacancies are introduced through electrochemical treatment, obvious HER activity enhancement is shown. The smooth implementation of the invention provides a universal, simple, convenient and efficient strategy for regulating and controlling the efficiency of the electro-catalytic hydrogen production reaction, solves the problems of high temperature and high energy consumption caused by introducing vacancies in a traditional heat treatment mode, and provides greater possibility for industrialization in the field of electro-catalytic hydrogen production.

A HEMT transistor includes a semiconductor body having a semiconductor heterostructure. A gate region of conductive material is disposed on and in contact with the semiconductor body. A first insulating layer laterally extends over the semiconductor body to the conductive gate region. A second insulating layer extends over the first insulating layer and the gate region. A first field plate region of conductive material extends between the first and second insulating layers, laterally separated from the conductive gate region along a first direction. A second field plate region of conductive material extends over the second insulating layer, and the second field plate region covers and is vertically aligned with the first field plate region.