15 results about "Semiconductor heterostructures" patented technology

The present disclosure provides for methods for designing and constructing metal / semiconductor heterostructures as catalysts for a wide range of applications such as oxygen activation. In a particular aspect, the present disclosure provides for the manipulation of atomic structures at M / TiO2 interface (e.g., Au / TiO2 interface) that significantly alters the interfacial electron distribution and prompts O2 activation. In an aspect, the present disclosure provides for a M / TiO2 composites (e.g., heterostructures) having a defect-free M / TiO2 interface and method of making the M / TiO2 composites having a defect-free M / TiO2 interface. The M can be Au, Ag, Cu, Al, Pt, Ni, or Pd, for example.

FIELD: microwave electronic devices.SUBSTANCE: in a low-noise microwave field-effect transistor on a semiconductor heterostructure, at least three quantum barrier layers of i-AlAs are additionally made, each with a thickness of 2-6 atomic monolayers, wherein each of said quantum barrier layers is located between the actual channel layer of InyGa1-yAs or a group of layers of the latter and the gate, wherein at least one quantum barrier layer is located between the doped layer and, or δ n-layer and the actual channel layer of InyGa1-yAs or a group of layers of the latter and at least one quantum barrier layer is located between the doped layer and, orδ n-layer and a gate, wherein the quantum barrier layers are separated from each other by at least one layer of narrow-band material AlxGa1-xAs, with a molar fraction of the chemical element Al x less than 0.4, with a thickness equal to or greater than 2 atomic monolayers, or a layer of GaAs, with a thickness equal to or greater than 2 atomic monolayers, between the actual channel layer InyGa1-yAs or a group of layers of the latter and the buffer layer, layers of GaAs, transition layers, quantum barrier layers i-AlAs, barrier layers, and layers doped with an acceptor impurity are made, on the last layer of the group of barrier layers, quantum barrier layers i-AlAs, barrier, transition and contact layers are made in a given sequence.EFFECT: increase in the gain factor and a reduction in the noise figure.1 cl, 1 dwg, 1 tbl

The application relates to a band gap testing method and device of a semiconductor heterostructure, computer equipment, a storage medium and a computer program product. The method comprises the following steps: scanning a first semiconductor material sample by using a visible spectrophotometer with a preset wavelength range to obtain a corresponding diffuse reflection spectrum of the first semiconductor material sample; scanning the semiconductor heterostructure by using the visible spectrophotometer with the preset wavelength range to obtain a corresponding diffuse reflection spectrum of the semiconductor heterostructure; determining band gap information of the first semiconductor material sample according to the corresponding diffuse reflection spectrum of the first semiconductor material sample, and determining band gap information of the semiconductor heterostructure according to the corresponding diffuse reflection spectrum of the semiconductor heterostructure; and obtaining a band gap testing result of the semiconductor heterostructure according to the band gap information of the first semiconductor material sample and the band gap information of the semiconductor heterostructure. The method can improve the band gap testing accuracy of a two-dimensional material heterojunction.

The invention relates to an ultrafast laser welding method for a transparent hard and brittle material and a semiconductor heterogeneous material. The transparent hard and brittle material and the semiconductor heterogeneous material are assembled in a clamp according to an optical contact state; and ultrafast laser welding parameters are set, an ultrafast laser is adopted to emit laser beams, the laser beams penetrate through the transparent hard and brittle material to act on the interface between the transparent hard and brittle material and the semiconductor material, and scanning welding is completed. Compared with the prior art, the ultrafast laser interlayer-free direct connection technology of the heterogeneous transparent hard and brittle material and the semiconductor material is provided for the first time, thermal stress concentration is avoided by optimizing the scanning path, effective connection of the transparent hard and brittle material and the semiconductor material is successfully achieved, and a high-strength and high-precision connection joint is formed. Compared with a traditional connection technology, the method does not need high temperature, an intermediate layer or an external load, is simple and convenient to operate, has a narrow heat affected zone, and is suitable for the precise manufacturing field of MEMS packaging and the like.

A quantum device including superconducting-semiconducting qubits and coupler designs based on high-quality, compact through-silicon vias (TSVs). An interposer probe wafer containing TSVs is used to contact a sample wafer with, for example, a superconductor-proximitized, epitaxially-grown, germanium quantum well. By utilizing the capacitance of the probe wafer TSVs, the majority of the electric field in the qubits is pulled away from lossy regions that are present in the semiconducting wafer. The probe wafer can reduce the qubit's electric field participation in the sample wafer by an order of magnitude for thin substrates and remains small even when the epitaxial layer thickness approaches 100 μμm. This scheme is extensible to multi-qubit systems that have tunable qubit-qubit couplings without magnetic fields. This approach shrinks the on-chip footprint of voltage-tunable superconducting qubits and is applicable to super-semi heterostructures in a variety of systems.

The application discloses a method for improving intrinsic thermal conductivity of a semiconductor, and belongs to the technical field of the semiconductor, and discloses a semiconductor heterostructure which comprises a semiconductor material and a modified layer which are arranged in a laminated mode; an interface between the semiconductor material and the modified layer is a coherent hetero-interface; the semiconductor material and the modified layer are matched in acoustic phonons and are not matched in optical phonons; and the semiconductor material and the modified layer each independently comprises a III-V semiconductor material. The semiconductor heterostructure with the coherent hetero-interface is constructed, the phonon transport near the interface is in a non-equilibrium state, the phonon-phonon scattering process is regulated and controlled, the thermal resistance caused by high-order phonon scattering is reduced, the phonon relaxation time is prolonged, and the intrinsic thermal conductivity of the material is improved. The application only needs to utilize the interface engineering, does not need to introduce a new material, the preparation process of the semiconductor heterostructure is compatible with an existing chip preparation process, and the engineering has strong realizability.

An electrical device is provided, the device comprising: an n-channel metal–oxide– semiconductor, NMOS, transistor comprising a source, a body and a drain, wherein the body is an elongated semiconductor heterostructure configured for conduction of negative charge carriers, wherein the source and the drain are arranged on opposite distal regions of the body; and a p-channel metal–oxide–semiconductor, PMOS, transistor comprising a source, a body and a drain, wherein the body is an elongated semiconductor heterostructure configured for conduction of positive charge carriers, wherein the source and the drain are arranged on opposite distal regions of the body; wherein the bodies are arranged separated, in parallel and superimposed relative to each other. The NMOS transistor and the PMOS transistor of the electrical device are connected to form a circuit for a complementary metal–oxide– semiconductor, CMOS. A method of providing an electrical device and a CMOS are also provided.

The application discloses a kind of color image sensor based on two-dimensional semiconductor heterostructure and its application in image convolution processing.The device contains deposited on substrate bipolar two-dimensional semiconductor and N-type two-dimensional semiconductor, which form horizontal heterojunction structure.By adjusting back gate voltage, the energy band arrangement of heterojunction is controlled, and a continuously variable spectral response function is realized, so that multi-band image information can be obtained without color filter.Meanwhile, by source-drain voltage, the photocurrent response of heterojunction is controlled, and then the output signal is given different weights.Several heterojunctions with the same size as the convolution kernel are connected in parallel, and the sum of the currents read is mapped to the gray value, and the convolved image under this waveband can be obtained.By applying convolution operation under different wavebands respectively, image convolution processing can be completed.The device performs well in integrated image acquisition and convolution calculation, effectively reduces the computing resource overhead, and significantly improves the image processing efficiency.

The present application relates to a kind of graphene nanobelt / copper selenide semiconductor heterostructure and its preparation method, belong to nanometer material technical field.The present application utilizes the strategy that intermolecular carbon hydrogen activation and intramolecular cyclization dehydrogenation will occur under the catalysis of four anthracene precursor in copper substrate, four anthracene precursor molecule is deposited on copper surface, and is kept at 100 ℃-400 ℃ temperature for 30 minutes to obtain one-dimensional graphene nanobelt.Then, the strategy that single-layer copper selenide semiconductor is generated by the chemical reaction of selenium powder and copper substrate is used, by depositing selenium powder on the above graphene nanobelt and copper substrate, and keeping at 100 ℃-400 ℃ temperature for 30 minutes, to obtain graphene nanobelt / copper selenide semiconductor heterostructure.

A HEMT transistor includes a semiconductor body having a semiconductor heterostructure. A gate region of conductive material is disposed on and in contact with the semiconductor body. A first insulating layer laterally extends over the semiconductor body to the conductive gate region. A second insulating layer extends over the first insulating layer and the gate region. A first field plate region of conductive material extends between the first and second insulating layers, laterally separated from the conductive gate region along a first direction. A second field plate region of conductive material extends over the second insulating layer, and the second field plate region covers and is vertically aligned with the first field plate region.

Semiconductor-superconductor hybrid devices with a horizontally-confined channel and methods of forming the same are described. An example semiconductor-superconductor hybrid device includes a semiconductor heterostructure formed over a substrate. The semiconductor-superconductor hybrid device may further include a superconducting layer formed over the semiconductor heterostructure. The semiconductor-superconductor hybrid device may further include a first gate, having a first top surface, formed adjacent to a first side of the semiconductor heterostructure. The semiconductor-superconductor hybrid device may further include a second gate, having a second top surface, formed adjacent to a second side, opposite to the first side, of the semiconductor heterostructure, where each of the first top surface of the first gate and the second top surface of the second gate is offset vertically from a selected surface of the semiconductor heterostructure by a predetermined offset amount.

Per-and polyfluoroalkyl substances (PFAS) are persistent contaminants that pose significant environmental and health risks. This invention introduces a semiconductor heterostructure material under visible light for PFAS degradation in aqueous matrices. Utilizing hexagonal boron nitride (h-BN) and zirconium dioxide (ZrO2), the heterostructure enhances charge separation and light absorption, enabling efficient PFAS mineralization under visible light. The invention offers a cost-effective and sustainable solution for PFAS remediation in wastewater treatment, stormwater management, and industrial effluents. By destroying rather than removing PFAS, the heterostructure provides a transformative advancement in environmental cleanup.

This invention belongs to the field of chip thermal management technology and discloses a method for simulating thermal transport at semiconductor heterostructure interfaces using micro / nanostructures. The method includes: defining the basic conditions such as the heterostructure system and interface type, setting optimization objectives and evaluation indicators; then, parameterizing the interface micro / nanostructure based on a morphology parameter database and establishing a three-dimensional geometric model; constructing a phonon parameter library using first-principles calculations; solving the phonon Boltzmann transport equation using the Monte Carlo method; simulating phonon transport and calculating thermal indicators; generating a simulation dataset under manufacturing constraints; training a neural network surrogate model based on the dataset to establish a fast mapping between morphology parameters and thermal indicators; using a genetic algorithm for global search to output a candidate solution set; finally, verifying prediction errors through high-fidelity solving, selecting high-confidence candidate solutions, and verifying the heat transfer performance of the candidate solutions. This invention provides a precise solution for enhancing heat transfer at semiconductor heterostructure interfaces, improving device thermal performance and reliability.

A semiconductor heterostructure for an optoelectronic device with improved light emission is disclosed. The heterostructure can include a first semiconductor layer having a first index of refraction n1. A second semiconductor layer can be located over the first semiconductor layer. The second semiconductor layer can include a laminate of semiconductor sublayers having an effective index of refraction n2. A third semiconductor layer having a third index of refraction n3 can be located over the second semiconductor layer. The first index of refraction n1 is greater than the second index of refraction n2, which is greater than the third index of refraction n3.

The invention discloses a preparation method and application of an axially ordered metal / semiconductor heterojunction, and belongs to the field of preparation of nano materials. The method comprises the following steps: firstly, providing an axially ordered semiconductor / semiconductor heterojunction as a template, and then carrying out cation exchange to obtain a target axially ordered semiconductor / semiconductor heterojunction; the preparation method comprises the following steps: mixing a target axial ordered semiconductor / semiconductor heterojunction dispersion liquid and a saturated aliphatic amine ligand to form a water-free and oxygen-free condition, then introducing inert gas, adding mercaptan and an organic phosphine ligand, heating to 200-240 DEG C, and reacting for 1-5 minutes to obtain the metal / semiconductor heterojunction which completely retains the axial ordered configuration. The method described by the invention is simple, mild and controllable, the preparation of the axially ordered metal / semiconductor heterostructure is realized for the first time, and the prepared axially ordered metal / semiconductor heterostructure with different segment numbers shows obviously different optical absorption properties and electron transmission properties.