357results about "Frequency-independant attenuators" patented technology

A semiconductor device is disclosed having vertically stacked (also referred to as vertically offset) transistors in a semiconductor fin. The semiconductor fin may include lower transistors separated by a first trench and having a source and drain in a first doped region of the fin. The semiconductor fin also includes upper transistors vertically offset from the first transistors and separated by a second trench and having a source and drain in a second doped region of the fin. Upper and lower stacked gates may be disposed on the sidewalls of the fin, such that the lower transistors are activated by biasing the lower gates and upper transistors are activated by biasing the upper gates. Methods of manufacturing and operating the device are also disclosed.

A cascode circuit with improved withstand voltage is provided. The cascode circuit includes three or more transistors, such as MOSFET transistors. Each transistor has a control terminal, such as a gate, and two conduction terminals, such as a drain and a source. The conduction terminals are coupled in series between two output terminals, such as where the drain of each transistor is coupled to the source of another transistor. A signal input is provided to the gate for the first transistor. Two or more control voltage sources, such as DC bias voltages, are provided to the gate of the remaining transistors. The DC bias voltages are selected so as to maintain the voltage across each transistor to a level below a breakdown voltage level.

A quantum interference transistor may include a source; a drain; N channels (N≧2), between the source and the drain, and having N−1 path differences between the source and the drain; and at least one gate disposed at one or more of the N channels. One or more of the N channels may be formed in a graphene sheet. A method of manufacturing the quantum interference transistor may include forming one or more of the N channels using a graphene sheet. A method of operating the quantum interference transistor may include applying a voltage to the at least one gate. The voltage may shift a phase of a wave of electrons passing through a channel at which the at least one gate is disposed.

A switching power converter with a controlled startup mechanism includes a switching stage which provides a voltage V_out at an output node in response to a switching control signal, with the output node adapted for connection to a non-linear load. A feedback network compares a signal which varies with the current conducted by the load (I_load) with a reference signal, and provides the switching control signal so as to maintain I_load at a desired value. A capacitor connected to the output node provides a current I_c to the feedback network which varies with dV_out/dt. The feedback network is arranged to limit dV_out/dt in response to current I_c when I_load is substantially zero. In this way, large inrush currents or damage that might otherwise occur during startup are avoided.

Apparatus and methods for distributing spurious tones through the frequency domain are disclosed. One such apparatus can include a dithering circuit configured to generate a sequence of numbers that exhibit statistical randomness and a variable frequency circuit configured to adjust a frequency of an output based on the sequence of numbers so as to spread energy of spurious tones in a frequency response of the output to lower a noise floor. In one example, spurious tones can be reduced in a negative voltage generator of a radio frequency (RF) attenuator.

A semiconductor device is provided that includes a fin having a first gate and a second gate formed on a first sidewall of the fin in a first trench, wherein the first gate is formed above the second gate. The device includes a third gate and a fourth gate formed on a second sidewall of the fin in a second trench, wherein the third gate is formed above the fourth gate. Methods of manufacturing and operating the device are also included. A method of operation may include biasing the first gate and the fourth gate to create a current path across the fin.

An electronic microwave circuit (1) with field effect transistors which are integrated on at least one semiconductor chip (2), has a light source (3), which radiates the field effect transistors with light and possesses a housing (6) which encloses in a microwave excluding manner the semiconductor chip (2) and the light source (3) or a light conducting means (8) connected with the light source (3).

An apparatus includes first and second electronically tunable transmission lines configured to transmit or receive a signal pair and provide a selected phase delay difference to the signal pair corresponding to a selected polarization, a first attenuation element connected to the first electronically tunable transmission line and a second attenuation element connected to the second electronically tunable transmission line. The first and second attenuation elements may each be configured to selectively attenuate signals carried on the electronically tunable transmission line to which they are connected according to a selected attenuation setting of a plurality of selectable attenuation settings provided by one or more attenuation control signals and thereby provide a selected attenuation to the signal pair that corresponds to the selected polarization. A corresponding method is also disclosed herein.

A semiconductor device is provided that includes a fin having a first upper gate on a sidewall of the fin in a first trench and a second upper gate formed on the opposite sidewall of the fin. The device also includes a first lower gate on the sidewall and a second lower gate on the opposite sidewall, wherein the first upper gate is formed above the first lower gate and the second upper gate is formed above the second lower gate. Methods of manufacturing and operating the device are also included. A method of operation may include biasing the first upper gate and second upper gate to preselect the transistors of a fin and then biasing the first lower gate and second lower gate to operate the transistors of the fin.