4963 results about "Circuit design" patented technology

The invention relates to an anti-electromagnetic interference intelligent cooling fan system based on dynamic filter circuit design. The system comprises a dual analysis module used for performing time domain and frequency domain dual analysis on a rotating speed feedback signal of a double-ball fan to obtain a multi-dimensional electromagnetic interference characteristic model, and configuring filter network parameters to obtain a target three-stage cascade dynamic filter network; the signal purification module is used for collecting first fan operation parameters and inputting the first fan operation parameters into a target three-stage cascade dynamic filter network for signal purification to obtain filtered Hall sensor signals and filtered power supply signals; the closed-loop control calculation module is used for performing closed-loop control calculation to obtain a non-linear PWM duty ratio control quantity and a phase distribution parameter; and the phase difference control module is used for carrying out phase difference control to obtain a multi-fan cooperative control strategy. According to the invention, high-precision control and anti-interference capability in a wide rotating speed range are realized, and the problem of mutual influence of electromagnetic interference when multiple fans are connected in parallel is solved.

The invention discloses a multichannel high-precision PAF signal synchronous acquisition system and a multichannel high-precision PAF signal synchronous acquisition method, and relates to the technical field of phased array signal acquisition and processing, the multichannel high-precision PAF signal synchronous acquisition system is characterized in that a hydrogen atomic clock time-frequency distribution module is in signal connection with a plurality of signal acquisition processing boards, and each signal acquisition processing board comprises a double-loop phase determination clock circuit and an RFSoC circuit; and the double-loop phase determination clock circuit is in signal connection with the RFSoC circuit. The time-frequency distribution module adopts a time-frequency signal output by a hydrogen atomic clock as a reference, so that the synchronization precision is ensured; the clock architecture of the acquisition processing board card adopts a phase determination mode, so that a Tile clock and a PL logic clock in the board are strictly in phase with an external input reference clock, and ADC acquisition synchronization of all channels is ensured; a phase clock circuit design is determined by adopting double loops, and all output clocks and an input reference clock keep a strict phase relationship; the system adopts a three-step synchronization process, so that the synchronous acquisition of hundreds of paths of PAF signals reaches the ps-level precision.

The invention discloses a circuit EMI suppression-oriented multi-knowledge collaborative distillation and optimization method and system, and the method comprises the steps: constructing a basic large language model based on the circuit design of the electronic industry as a student model, and carrying out the adaptive optimization of the circuit design field. Thirdly, integrating the formalized EMI rule base, the simulation data / model base and the expert experience case base, constructing a multi-source heterogeneous teacher knowledge system, and generating a comprehensive guidance signal G; then, candidate circuit design generated by a student model is evaluated through the system, and a multi-objective loss function including basic distillation, rule conformity, performance fitting and expert experience consistency is constructed; according to the method, the universality is reserved by quantifying differences, compliance is ensured through punishment, the performance difference is reduced, dynamic weight adjustment is introduced, and the model performance reaches a preset target through iterative distillation. The model can understand and process terminologies and design rules in the field of circuit design, and the defect that a general AI model lacks domain knowledge is overcome.

The invention relates to the technical field of power electronics, in particular to a filter equivalent circuit design simulation system suitable for an energy storage converter, which comprises a main circuit topology unit, a control strategy unit, a parameter optimization and design unit, a simulation engine unit and a performance evaluation unit, wherein the main circuit topology unit is used for building a filter equivalent circuit topology of the energy storage converter and configuring passive element parameters of an inductor, a capacitor and a resistor. According to the method, automatic high-robustness optimization of filter parameters is realized through genetic algorithm-particle swarm hybrid optimization, multi-objective collaborative optimization and digital twinning auxiliary optimization, and a'design-optimization-verification-iteration 'closed loop is formed by combining dynamic working condition evaluation, reliability modeling and artificial intelligence auxiliary analysis, so that the method has the advantages of high robustness and high robustness. The harmonic suppression capability, efficiency and long-term operation reliability of the filter are remarkably improved, the design period is shortened, and the development cost is reduced.

The invention belongs to the technical field of integrated circuit design verification, and particularly discloses an SoC performance verification method and device based on dynamic QoS regulation and control, a medium and equipment, and the method comprises the steps: analyzing a chip architecture, and obtaining a chip resource mapping table; constructing an automatic verification environment based on the chip resource mapping table and performing testing; scene parameter configuration is carried out according to a target application scene and based on the chip resource mapping table; and performing dynamic QoS regulation and control based on the configured scene parameters in a tested automatic verification environment so as to verify the performance of the SoC. According to the invention, the accuracy and efficiency of SoC performance verification and the consistency of the result and the actual application scene can be improved.

The invention discloses a clock tree synthesis method and system based on clustering, and the method comprises the steps: carrying out the preliminary grouping of registers through employing a K-means clustering method, generating the position of a first-stage buffer under the condition that the maximum fan-out number limitation constraint, the maximum RC constraint and the position overlapping constraint are satisfied, and generating a second-stage buffer based on the position, and then constructing a subsequent clock tree by adopting a DME algorithm. The problem of clock signal distribution in large-scale integrated circuit design is solved, clock delay, clock skew and the number of buffers can be reduced, and the comprehensive quality of the clock tree is improved.

The invention belongs to the field of driving circuits of gallium nitride (GaN) power devices in motor driving or power electronic conversion, and discloses a design method of a three-level active driving circuit for restraining bridge arm crosstalk of a GaN device, and the method comprises the steps that a circuit is connected in a bridge type topological structure, and the bridge type topological structure comprises an upper bridge arm and a lower bridge arm which are the same in structure; the upper bridge arm and the lower bridge arm are both divided into two parts, namely a traditional driving circuit and an auxiliary circuit, and the auxiliary circuit is divided into a negative voltage self-recovery circuit and a crosstalk suppression circuit. According to the invention, a negative voltage self-recovery circuit and a crosstalk suppression circuit are formed by using the output and reverse conduction characteristics of the charge pump and the auxiliary GaN device. The advantages of the two methods are combined, the defects of a traditional method are effectively overcome, the turn-off speed is increased, the turn-off loss is reduced, and the positive and negative crosstalk is reduced while the turn-on speed is hardly influenced and the reverse turn-on loss is not additionally increased. The overall design is flexible, efficient and reliable.

The invention relates to the technical field of display screen control, and discloses an LED display screen intelligent control system and method, and the system comprises a module M1 which is an environment perception and collection module; the module M2 is a dynamic display optimization module; the module M3 is a multi-mode cooperative control module; the module M4 is an intelligent fault tolerance module; the module M5 is an energy management module; the method comprises the following steps: S1, collecting data in real time through an environment sensing and collecting module; s2, according to environmental parameters; s3, designing a redundant drive circuit; s4, realizing partition management of the display content through a multi-mode cooperative control module; s5, the intelligent fault tolerance module automatically switches a standby communication link; s6, the driving current is dynamically adjusted according to the environment temperature and the display load; according to the invention, the adjustment parameters can be preloaded to the display driving main control unit, so that rapid and accurate adaptive adjustment of the brightness, color temperature and color gamut of the display screen is realized.

The invention belongs to the technical field of electronic design automation, and provides a dynamic power consumption optimization method, electronic equipment and a storage medium, and the method comprises the steps: obtaining a circuit design, and determining a starting point of a specific type in the circuit design; performing backward traversal on the circuit design along a signal propagation direction from the starting point to determine circuit branch structure information and a specific type of termination point in the circuit design; starting from the termination point, establishing an ODC expression, performing forward traversal on the circuit design in an inverse signal propagation direction, and in the forward traversal process, based on the circuit branch structure information, propagating the ODC expression in the circuit design until ODC distribution of the circuit design is determined; based on the ODC distribution, dynamic power consumption optimization is performed on the circuit design. According to the method, the ODC expression can be quickly and efficiently propagated in the whole circuit design, so that a designer can conveniently optimize the dynamic power consumption through ODC distribution.

The invention provides a method for testing the dynamic strain of the surface of a rotating body in an electromagnetic environment. The method comprises the following steps: constructing a bridge by using strain gauges and acquiring dynamic characteristic data of the rotating part under actual constraint conditions; performing simulation calculation according to the dynamic characteristic data, and determining the optimal pasting position of the strain gauge; pasting a strain gauge and formulating a wiring scheme of a strain gauge wire; the strain gauge is connected with a voltage signal amplifier, the amplified signal is connected with a data acquisition system through a conductive slip ring, and the amplified strain signal is recorded and processed; acquiring strain signals in real time and taking the strain signals as test data, and performing whole-course test in a full-rotating-speed range to complete dynamic strain test on the surface of the rotating body. The system has high sensitivity, the sensitivity and the measurement precision of the system are improved through full-bridge configuration, larger output signals are provided, the full bridge can achieve temperature compensation through symmetrical circuit design, and the system has good linear output characteristics and facilitates signal processing and analysis within the strain range.

The invention provides a design optimization method and device for an intracardiac ultrasonic transducer array, a medium and a program product, and relates to the technical field of ultrasonic imaging equipment. The method comprises the following steps: acquiring a marshalling scheme and independent array elements of an ultrasonic transducer array, and marshalling the independent array elements based on the marshalling scheme to form at least two independent equivalent sub-apertures; establishing a spherical coordinate system by taking the geometric center of the ultrasonic transducer array as an original point, determining a pre-deflection direction and an imaging focus of the pre-deflection focus representation array based on the spherical coordinate system, and calculating static time delay; calculating the geometric center coordinate of each equivalent sub-aperture and the flight time of the imaging focus to obtain the dynamic time delay of each equivalent sub-aperture; and obtaining a space sound field based on the static time delay, the dynamic time delay and other parameters. Under the limitation of a limited space, the imaging performance of the ultrasonic transducer array is maintained while array element connection and circuit design are optimized, so that high-quality imaging quality is obtained.

The invention relates to the technical field of circuit board manufacturing, and discloses a circuit board manufacturing method, an impedance compensation method and a circuit board, and the circuit board manufacturing method comprises the steps: obtaining an inner-layer circuit design drawing of the circuit board; dividing the inner-layer circuit design drawing into a preset number of areas; calculating the residual copper rate of each region; and according to a deviation value between the residual copper rate of each region and a preset standard residual copper rate, adjusting the line width of the line in the corresponding region of the inner-layer line design drawing so as to prepare the inner-layer line of the circuit board by using the adjusted inner-layer line design drawing. The problem of inconsistent impedance caused by dielectric thickness change is solved, and high-speed signal transmission of the circuit board is more stable and reliable.

The invention belongs to the field of integrated circuit design, and particularly relates to a chip layout optimization method, system and device based on improved reinforcement learning. The method comprises the following steps: S1, constructing a layout optimization model comprising a feature coding module, a feature fusion module, an experience pool, a strategy network and a value network; the feature coding module is used for extracting a position mask, a line mask and a view mask of the netlist file; the feature fusion module extracts local features and global features and generates comprehensive features; the experience pool, the strategy network and the value network form a reinforcement learning framework. S2, using a large number of random netlists as sample data for training a layout optimization model; and S3, inputting a chart file to be optimized into the trained layout optimization model, outputting an optimized netlist file by the layout optimization model, and generating a corresponding optimized circuit layout chart according to the netlist file. The chip layout optimization method solves the problems that an existing chip layout optimization method is low in efficiency and insufficient in generalization.

The invention relates to the technical field of circuit design, in particular to a digital circuit simulation design method and system. The method comprises the following steps: identifying a design demand document, performing deep semantic analysis and demand constraint mining, and constructing a demand specification constraint parameter set; performing demand complexity evaluation and multi-level division according to the demand specification constraint parameter set, and constructing a basic circuit architecture design blueprint; circuit routing path planning is carried out according to the basic circuit architecture design blueprint, and a standardized circuit topology network is constructed; performing electric signal propagation simulation on the standardized circuit topology network, and performing global circuit adaptability adjustment to obtain a circuit topology design scheme; and carrying out an extreme condition simulation test based on the circuit topology design scheme, and carrying out comprehensive performance evaluation to obtain a circuit performance evaluation report. By deeply understanding the user demand intention, the circuit layout matched with the user demand is designed, and the overall circuit performance is improved.

The invention provides an artificial intelligence-based interface circuit design method, which comprises the following steps of: S1, acquiring an RTL code for describing a logic structure of a digital circuit, and generating a digital circuit layout according to the RTL code by utilizing a preset neural network model; s2, acquiring a preset process library and design parameters of the analog circuit, and generating an analog circuit layout by using a preset neural network model according to the process library and the design parameters of the analog circuit; and S3, fusing the digital circuit layout and the analog circuit layout by using a preset neural network model to obtain the layout of the interface circuit.

The invention provides a text classification method based on quantum transfer learning, and belongs to the field of fusion of quantum computing and artificial intelligence. In consideration of complex feature space and nonlinear characteristics in text classification, quantum circuit design, a self-attention mechanism and a quantum transfer learning process are optimized, so that the learning efficiency and classification accuracy of the model are improved. The high-dimensional feature representation and a complex nonlinear decision process are converted into a quantum self-attention network structure, an optimal strategy of text classification is obtained by utilizing a complex quantum kernel self-attention network (CQKSAN) model, and a quantum superposition and entanglement mechanism is introduced to enhance the expression ability of the model. A simulation result shows that compared with a traditional deep learning algorithm and other mixed quantum-classical algorithms, the algorithm provided by the invention has higher classification precision and learning efficiency. The method not only shows the potential of a mixed quantum-classical method, but also provides a basis for further research of a future full-quantum learning system.

The invention relates to the technical field of energy storage technology, integrated circuit design and battery management systems, and discloses a passport-sensing integrated battery management chip and a battery management system architecture, battery information is collected based on the passport-sensing integrated battery management chip, and unique battery passport information is generated. And then real-time interaction with the BMS main control module is carried out through the daisy chain communication module, so that the health state of the battery is evaluated and managed. The battery cell state data acquisition and traceability functions are realized through the battery cell slave board, the BMS master control module has a fine management function on the battery state, battery safety early warning and daisy chain communication channels are provided to realize real-time interaction between the battery cell slave board information and the BMS master control module information, online and offline information disclosure modes are fused, a collaborative management architecture is established, and the battery cell state data acquisition and traceability functions are realized. Intelligent management and data tracking of the whole life cycle of the battery are realized, and the safety, reliability and traceability of the battery are improved.

The invention provides a packaging substrate structure and a preparation method thereof. The preparation method comprises the following steps: providing a core plate layer; forming a multilayer substrate adding layer covering two opposite surfaces of the core plate layer and electrically connected with the core plate layer; providing an interconnection structure layer which comprises a bottom circuit layer, a bottom dielectric layer and a middle interconnection layer; pressing the interconnection structure layer in a preset area of the substrate adding layer in an inverted manner to obtain a required substrate structure layer; solder mask layers are formed on the two opposite faces of the substrate structure layer, contact holes are formed in the preset positions of the solder mask layers, and at least one contact hole exposes the conductive part of the interconnection structure layer. According to the invention, packaging with finer lines, lighter and lighter weight and higher line density can be realized, and signal transmission loss can be substantially reduced at the same time. Besides, the packaging substrate structure has high design flexibility, and the thickness and the circuit density of the interconnection structure layer can be accurately controlled by adjusting the thickness, the number of layers and the circuit design of each dielectric layer and each circuit layer so as to meet specific packaging requirements.

The invention provides an in-orbit integrated circuit aging fault diagnosis method and diagnosis system, and relates to the technical field of integrated circuit design, and the method comprises the steps: ground training: collecting characteristic parameters, carrying out the characteristic parameter processing based on an SPI protocol algorithm, a digital signal recovery fixed-point decimal algorithm, a wavelet transform filtering algorithm and a deviation standardization algorithm, and carrying out the fault diagnosis; constructing an aging failure fault data set, training through a back propagation algorithm to obtain feed-forward neural network parameters, and transplanting the feed-forward neural network parameters to a feed-forward neural network constructed based on Pytorch and a feed-forward neural network constructed based on FPGA for joint testing; and in-orbit testing: data enters a data buffer area, training data is provided for a learning training module, feedforward neural network parameters are periodically updated by using an exponential weighted moving average algorithm, and the feedforward neural network parameters are transplanted to a feedforward neural network established based on Pytorch and a feedforward neural network established by an FPGA for joint testing. Continuous learning of on-orbit data is realized, and the method adapts to irregular periodic electromagnetic influence of a space environment.

The invention relates to a preparation method of a memory cell and a memory, and relates to the technical field of integrated circuit design and manufacturing, the memory cell comprises an active column, a capacitor, a first grid electrode and a second grid electrode, the active column has a first end surface and a second end surface deviating from each other along a first direction, and the first end surface is used for being connected with a bit line; the active column internally comprises a first doped region, a channel region and a second doped region which are sequentially arranged along a first direction, the channel region is provided with a first outer surface and a second outer surface which are deviated from each other along a second direction, and the channel region internally comprises a stress structure which penetrates through the active column along a third direction; the first direction and the second direction intersect and are perpendicular to the third direction; the capacitor covers the second end surface and circumferentially surrounds part of the side surface of the active column; the first grid electrode is located on the first outer surface of the channel region; the second grid electrode is located on the second outer surface of the channel region, and the performance and reliability of the memory cell can be improved at least under the condition that the size of the memory cell is reduced.

The invention provides a junction temperature measuring circuit of a vehicle inverter power device and a design method and application thereof. The junction temperature measuring circuit comprises two measuring circuits and a clamping power supply, wherein the two measuring circuits are respectively used for measuring two power devices of an upper bridge and a lower bridge; each measuring circuit comprises a self-adaptive switch and a clamping module, and the self-adaptive switch is configured to enable the potential of the measuring end to track the potential of the drain electrode or the source electrode of the measured power device when the measured power device enters a conducting state; when the tested power device is in the off state, the micro-conduction state between the drain electrode or the source electrode of the tested power device and the measuring end is kept; the clamping module realizes positive clamping voltage and negative clamping voltage through a clamping power supply, and the positive clamping voltage and the negative clamping voltage are respectively used for voltage clamping of a measuring end when the measured power device is in a turn-off state. According to the junction temperature measuring circuit provided by the invention, the working junction temperature of the power device of the high-speed switch can be measured timely and accurately.

The invention relates to the technical field of integrated circuit design, and particularly discloses a low-noise programmable amplifier, which comprises a first fully-differential amplifier, a second fully-differential amplifier, a third fully-differential amplifier and a fourth fully-differential amplifier, the second fully differential amplifier comprises a pair of differential input ends and is electrically connected with the first fully differential amplifier through an interstage chopper switch; a pair of input chopping switches, wherein the input end of each input chopping switch is electrically connected with a differential input signal; the output end of each output chopping switch is electrically connected with the output end of the second fully differential amplifier; the input capacitance network is positioned between the pair of input chopping switches and the two pairs of differential input ends; the feedback capacitance network is positioned between the pair of output chopping switches and the two pairs of differential input ends; and the plurality of zeroing switches are positioned between the input and the output of the first fully differential amplifier. The two transconductance amplifiers in the first fully-differential amplifier share the same current, the overall transconductance is doubled compared with single-pair differential input, and the noise of the amplifier is reduced.

The invention relates to the technical field of integrated circuit design verification, and provides a chip power consumption analysis optimization method and system, and the method comprises the steps: obtaining circuit structure information of a chip, carrying out the analysis of the circuit structure information, generating and analyzing a module topological graph and a function logic graph of a circuit, and obtaining static power consumption data and dynamic power consumption data; after a preset analysis model is input and working mode parameters are obtained, a key path in the circuit structure information is reconstructed, based on the reconstructed circuit structure information, dynamic behavior simulation is carried out on the function logic diagram again, simulation power consumption data are generated, the simulation power consumption data and the dynamic power consumption data are subjected to comparative analysis, and the simulation power consumption data are obtained. And generating a power consumption optimization scheme based on the comparison result. By acquiring and analyzing the circuit structure information of the chip, a power consumption optimization scheme is generated, the energy efficiency ratio of the chip is improved, and the problem that an optimization path is difficult to quickly generate for a complex circuit structure during positioning of a power consumption hot spot and circuit optimization reconstruction is solved.

The invention provides a chip power supply network compensation method and device, equipment, a storage medium and a program, relates to the technical field of integrated circuits, in particular to a chip and circuit design technology, can be applied to an application scene of chip test optimization, and the method comprises the following steps: determining a dynamic power consumption violation area of a current power supply network of a target chip; performing compensation priority classification on the dynamic power consumption violation area according to the voltage drop violation distribution information of the dynamic power consumption violation area to obtain a violation priority classification area; and determining a local power supply network compensation strategy of each violation priority classification area according to the compensation priority of the violation priority classification area. According to the embodiment of the invention, the efficiency and precision of chip power supply network compensation can be improved.

The invention relates to the technical field of integrated circuit design and artificial intelligence hardware acceleration, and particularly discloses a quantization precision adaptive switching hardware acceleration architecture. Hardware is divided into a static area and a dynamic area, wherein the static area comprises a pre-processing module, a post-processing module, a control module and a reconfigurable logic loading control block which run all the time; the dynamic region bears a quantization and inverse quantization module composed of a plurality of reconfigurable logic units. The method is characterized in that a model precision instruction is analyzed through a control module, and a reconfigurable logic file with corresponding precision is dynamically loaded to a dynamic area from external starting equipment by a loading control block according to an internal address mapping table, so that seamless switching of different quantization precision is realized on the hardware level, and the whole chip does not need to be burnt again. According to the design, through a modularized and reconfigurable hardware structure, the limitation of fixed-precision hardware in coping with diversified AI models is effectively solved, and the deployment flexibility and energy efficiency are remarkably improved.

An exemplary integrated circuit design lockout system comprises an integrated circuit and a key obfuscated circuit embedded with the integrated circuit. The key obfuscated circuit is configured to verify that a user provides a valid key for the integrated circuit before the user is allowed to operate the integrated circuit. The exemplary integrated circuit design lockout system further comprises a lockout circuit embedded with the key obfuscated circuit, wherein the lockout circuit is configured to allow for a threshold number of failed attempts for the user to provide the valid key before the lockout circuit prohibits the user from making any further attempts at providing the valid key for the integrated circuit.

The invention relates to the field of electronic design automation (EDA), and provides an AMS circuit automatic design method using a large language model. The method aims at solving the problem that an existing AMS circuit design is insufficient in automation degree, and mainly comprises the steps that a schematic circuit diagram and text description are extracted from literatures, and a data set containing the schematic circuit diagram, a netlist and annotation information is constructed; performing connectivity detection on the schematic circuit diagram, and extracting a netlist; carrying out annotation processing to obtain annotation information; constructing a knowledge graph for storing circuit information; obtaining a design strategy by using a large language model, and describing a circuit architecture; according to the design strategy and the local annotation, relevant circuits and test platforms are retrieved, a complete circuit topology is assembled, and simulation is carried out; size optimization is carried out based on constraints, and a Bayesian optimization algorithm is used for solving; and if the initial topological structure cannot meet the performance target, carrying out topological reconstruction. According to the invention, the automation level and efficiency of analog and mixed signal circuit design are improved.

A method (of manufacturing a semiconductor device) includes migrating a circuit design from a first netlist corresponding with a first semiconductor process technology (SPT) to a second netlist corresponding with a second SPT, the migrating including: expanding a first version of the first netlist and a first precursor of the second netlist correspondingly to form a second version of the first netlist and a second precursor of the second netlist; before conducting (A) placement and routing (P&R) of a layout diagram corresponding to the second netlist or (B) a static timing analysis of the layout diagram; performing a logic equivalence check (LEC) between the second version of the first netlist and the second precursor of the second netlist, thereby identifying migration errors, and revising the second precursor of the second netlist to reduce the migration errors, thereby resulting in a third precursor of the second netlist.

The invention relates to a memristor array-based MIMO communication system signal detection method, circuit, device and equipment, which are used in the field of wireless communication signal processing. In order to solve the problem that an existing MIMO signal detection calculation circuit based on a memristor array is very sensitive to conductance errors of memristors, an MIMO channel matrix is expressed as a product of a small-scale fading coefficient matrix and a large-scale fading coefficient matrix, and a matrix calculation expression of ZF signal detection and MMSE signal detection is converted into a new equivalent form. A matrix calculation circuit based on the memristor array is used for calculating the converted equivalent expression, and signal detection is achieved; the invention provides two kinds of matrix calculation circuit design schemes based on the memristor array, two kinds of corresponding MIMO communication system signal detection devices and three kinds of MIMO communication system signal detection equipment based on the memristor array. According to the invention, the sensitivity to the conductivity error of the memristor is lower, and the signal detection performance is better.

The invention provides a circuit design simulation method and system for an angle sensor, and relates to the technical field of circuit design simulation, and the method comprises the steps: constructing a circuit topological structure diagram of the angle sensor, carrying out the multi-physics coupling simulation, and obtaining an output characteristic curve of the angle sensor; performing nonlinear error analysis, constructing an error compensation mapping set, performing parameter iterative optimization, and generating a target compensation parameter combination; and the target compensation parameter combination is embedded into the circuit topological structure diagram for closed-loop verification, and a simulation verification report is generated. According to the method and the device, the technical problem that deviation exists between a simulation result and reality in a complex dynamic environment due to poor environmental adaptability and compensation lag existing in circuit design simulation is solved, intelligent compensation of nonlinear errors is realized through multi-physics field coupling simulation and segmented compensation, and the precision and the efficiency of circuit design simulation are improved.