3808 results about "Circuit design" patented technology

The invention discloses a multichannel high-precision PAF signal synchronous acquisition system and a multichannel high-precision PAF signal synchronous acquisition method, and relates to the technical field of phased array signal acquisition and processing, the multichannel high-precision PAF signal synchronous acquisition system is characterized in that a hydrogen atomic clock time-frequency distribution module is in signal connection with a plurality of signal acquisition processing boards, and each signal acquisition processing board comprises a double-loop phase determination clock circuit and an RFSoC circuit; and the double-loop phase determination clock circuit is in signal connection with the RFSoC circuit. The time-frequency distribution module adopts a time-frequency signal output by a hydrogen atomic clock as a reference, so that the synchronization precision is ensured; the clock architecture of the acquisition processing board card adopts a phase determination mode, so that a Tile clock and a PL logic clock in the board are strictly in phase with an external input reference clock, and ADC acquisition synchronization of all channels is ensured; a phase clock circuit design is determined by adopting double loops, and all output clocks and an input reference clock keep a strict phase relationship; the system adopts a three-step synchronization process, so that the synchronous acquisition of hundreds of paths of PAF signals reaches the ps-level precision.

The invention discloses a circuit EMI suppression-oriented multi-knowledge collaborative distillation and optimization method and system, and the method comprises the steps: constructing a basic large language model based on the circuit design of the electronic industry as a student model, and carrying out the adaptive optimization of the circuit design field. Thirdly, integrating the formalized EMI rule base, the simulation data / model base and the expert experience case base, constructing a multi-source heterogeneous teacher knowledge system, and generating a comprehensive guidance signal G; then, candidate circuit design generated by a student model is evaluated through the system, and a multi-objective loss function including basic distillation, rule conformity, performance fitting and expert experience consistency is constructed; according to the method, the universality is reserved by quantifying differences, compliance is ensured through punishment, the performance difference is reduced, dynamic weight adjustment is introduced, and the model performance reaches a preset target through iterative distillation. The model can understand and process terminologies and design rules in the field of circuit design, and the defect that a general AI model lacks domain knowledge is overcome.

The invention relates to the technical field of power electronics, in particular to a filter equivalent circuit design simulation system suitable for an energy storage converter, which comprises a main circuit topology unit, a control strategy unit, a parameter optimization and design unit, a simulation engine unit and a performance evaluation unit, wherein the main circuit topology unit is used for building a filter equivalent circuit topology of the energy storage converter and configuring passive element parameters of an inductor, a capacitor and a resistor. According to the method, automatic high-robustness optimization of filter parameters is realized through genetic algorithm-particle swarm hybrid optimization, multi-objective collaborative optimization and digital twinning auxiliary optimization, and a'design-optimization-verification-iteration 'closed loop is formed by combining dynamic working condition evaluation, reliability modeling and artificial intelligence auxiliary analysis, so that the method has the advantages of high robustness and high robustness. The harmonic suppression capability, efficiency and long-term operation reliability of the filter are remarkably improved, the design period is shortened, and the development cost is reduced.

The invention belongs to the technical field of integrated circuit design verification, and particularly discloses an SoC performance verification method and device based on dynamic QoS regulation and control, a medium and equipment, and the method comprises the steps: analyzing a chip architecture, and obtaining a chip resource mapping table; constructing an automatic verification environment based on the chip resource mapping table and performing testing; scene parameter configuration is carried out according to a target application scene and based on the chip resource mapping table; and performing dynamic QoS regulation and control based on the configured scene parameters in a tested automatic verification environment so as to verify the performance of the SoC. According to the invention, the accuracy and efficiency of SoC performance verification and the consistency of the result and the actual application scene can be improved.

The invention discloses a clock tree synthesis method and system based on clustering, and the method comprises the steps: carrying out the preliminary grouping of registers through employing a K-means clustering method, generating the position of a first-stage buffer under the condition that the maximum fan-out number limitation constraint, the maximum RC constraint and the position overlapping constraint are satisfied, and generating a second-stage buffer based on the position, and then constructing a subsequent clock tree by adopting a DME algorithm. The problem of clock signal distribution in large-scale integrated circuit design is solved, clock delay, clock skew and the number of buffers can be reduced, and the comprehensive quality of the clock tree is improved.

The invention belongs to the field of driving circuits of gallium nitride (GaN) power devices in motor driving or power electronic conversion, and discloses a design method of a three-level active driving circuit for restraining bridge arm crosstalk of a GaN device, and the method comprises the steps that a circuit is connected in a bridge type topological structure, and the bridge type topological structure comprises an upper bridge arm and a lower bridge arm which are the same in structure; the upper bridge arm and the lower bridge arm are both divided into two parts, namely a traditional driving circuit and an auxiliary circuit, and the auxiliary circuit is divided into a negative voltage self-recovery circuit and a crosstalk suppression circuit. According to the invention, a negative voltage self-recovery circuit and a crosstalk suppression circuit are formed by using the output and reverse conduction characteristics of the charge pump and the auxiliary GaN device. The advantages of the two methods are combined, the defects of a traditional method are effectively overcome, the turn-off speed is increased, the turn-off loss is reduced, and the positive and negative crosstalk is reduced while the turn-on speed is hardly influenced and the reverse turn-on loss is not additionally increased. The overall design is flexible, efficient and reliable.

The invention relates to the technical field of display screen control, and discloses an LED display screen intelligent control system and method, and the system comprises a module M1 which is an environment perception and collection module; the module M2 is a dynamic display optimization module; the module M3 is a multi-mode cooperative control module; the module M4 is an intelligent fault tolerance module; the module M5 is an energy management module; the method comprises the following steps: S1, collecting data in real time through an environment sensing and collecting module; s2, according to environmental parameters; s3, designing a redundant drive circuit; s4, realizing partition management of the display content through a multi-mode cooperative control module; s5, the intelligent fault tolerance module automatically switches a standby communication link; s6, the driving current is dynamically adjusted according to the environment temperature and the display load; according to the invention, the adjustment parameters can be preloaded to the display driving main control unit, so that rapid and accurate adaptive adjustment of the brightness, color temperature and color gamut of the display screen is realized.

The invention belongs to the technical field of electronic design automation, and provides a dynamic power consumption optimization method, electronic equipment and a storage medium, and the method comprises the steps: obtaining a circuit design, and determining a starting point of a specific type in the circuit design; performing backward traversal on the circuit design along a signal propagation direction from the starting point to determine circuit branch structure information and a specific type of termination point in the circuit design; starting from the termination point, establishing an ODC expression, performing forward traversal on the circuit design in an inverse signal propagation direction, and in the forward traversal process, based on the circuit branch structure information, propagating the ODC expression in the circuit design until ODC distribution of the circuit design is determined; based on the ODC distribution, dynamic power consumption optimization is performed on the circuit design. According to the method, the ODC expression can be quickly and efficiently propagated in the whole circuit design, so that a designer can conveniently optimize the dynamic power consumption through ODC distribution.

The invention relates to the technical field of circuit board manufacturing, and discloses a circuit board manufacturing method, an impedance compensation method and a circuit board, and the circuit board manufacturing method comprises the steps: obtaining an inner-layer circuit design drawing of the circuit board; dividing the inner-layer circuit design drawing into a preset number of areas; calculating the residual copper rate of each region; and according to a deviation value between the residual copper rate of each region and a preset standard residual copper rate, adjusting the line width of the line in the corresponding region of the inner-layer line design drawing so as to prepare the inner-layer line of the circuit board by using the adjusted inner-layer line design drawing. The problem of inconsistent impedance caused by dielectric thickness change is solved, and high-speed signal transmission of the circuit board is more stable and reliable.

The invention relates to the technical field of circuit design, in particular to a digital circuit simulation design method and system. The method comprises the following steps: identifying a design demand document, performing deep semantic analysis and demand constraint mining, and constructing a demand specification constraint parameter set; performing demand complexity evaluation and multi-level division according to the demand specification constraint parameter set, and constructing a basic circuit architecture design blueprint; circuit routing path planning is carried out according to the basic circuit architecture design blueprint, and a standardized circuit topology network is constructed; performing electric signal propagation simulation on the standardized circuit topology network, and performing global circuit adaptability adjustment to obtain a circuit topology design scheme; and carrying out an extreme condition simulation test based on the circuit topology design scheme, and carrying out comprehensive performance evaluation to obtain a circuit performance evaluation report. By deeply understanding the user demand intention, the circuit layout matched with the user demand is designed, and the overall circuit performance is improved.

The invention provides an artificial intelligence-based interface circuit design method, which comprises the following steps of: S1, acquiring an RTL code for describing a logic structure of a digital circuit, and generating a digital circuit layout according to the RTL code by utilizing a preset neural network model; s2, acquiring a preset process library and design parameters of the analog circuit, and generating an analog circuit layout by using a preset neural network model according to the process library and the design parameters of the analog circuit; and S3, fusing the digital circuit layout and the analog circuit layout by using a preset neural network model to obtain the layout of the interface circuit.

The invention relates to the technical field of energy storage technology, integrated circuit design and battery management systems, and discloses a passport-sensing integrated battery management chip and a battery management system architecture, battery information is collected based on the passport-sensing integrated battery management chip, and unique battery passport information is generated. And then real-time interaction with the BMS main control module is carried out through the daisy chain communication module, so that the health state of the battery is evaluated and managed. The battery cell state data acquisition and traceability functions are realized through the battery cell slave board, the BMS master control module has a fine management function on the battery state, battery safety early warning and daisy chain communication channels are provided to realize real-time interaction between the battery cell slave board information and the BMS master control module information, online and offline information disclosure modes are fused, a collaborative management architecture is established, and the battery cell state data acquisition and traceability functions are realized. Intelligent management and data tracking of the whole life cycle of the battery are realized, and the safety, reliability and traceability of the battery are improved.

The invention relates to the technical field of integrated circuit design verification, and provides a chip power consumption analysis optimization method and system, and the method comprises the steps: obtaining circuit structure information of a chip, carrying out the analysis of the circuit structure information, generating and analyzing a module topological graph and a function logic graph of a circuit, and obtaining static power consumption data and dynamic power consumption data; after a preset analysis model is input and working mode parameters are obtained, a key path in the circuit structure information is reconstructed, based on the reconstructed circuit structure information, dynamic behavior simulation is carried out on the function logic diagram again, simulation power consumption data are generated, the simulation power consumption data and the dynamic power consumption data are subjected to comparative analysis, and the simulation power consumption data are obtained. And generating a power consumption optimization scheme based on the comparison result. By acquiring and analyzing the circuit structure information of the chip, a power consumption optimization scheme is generated, the energy efficiency ratio of the chip is improved, and the problem that an optimization path is difficult to quickly generate for a complex circuit structure during positioning of a power consumption hot spot and circuit optimization reconstruction is solved.

The invention provides a chip power supply network compensation method and device, equipment, a storage medium and a program, relates to the technical field of integrated circuits, in particular to a chip and circuit design technology, can be applied to an application scene of chip test optimization, and the method comprises the following steps: determining a dynamic power consumption violation area of a current power supply network of a target chip; performing compensation priority classification on the dynamic power consumption violation area according to the voltage drop violation distribution information of the dynamic power consumption violation area to obtain a violation priority classification area; and determining a local power supply network compensation strategy of each violation priority classification area according to the compensation priority of the violation priority classification area. According to the embodiment of the invention, the efficiency and precision of chip power supply network compensation can be improved.

The invention relates to the technical field of integrated circuit design and artificial intelligence hardware acceleration, and particularly discloses a quantization precision adaptive switching hardware acceleration architecture. Hardware is divided into a static area and a dynamic area, wherein the static area comprises a pre-processing module, a post-processing module, a control module and a reconfigurable logic loading control block which run all the time; the dynamic region bears a quantization and inverse quantization module composed of a plurality of reconfigurable logic units. The method is characterized in that a model precision instruction is analyzed through a control module, and a reconfigurable logic file with corresponding precision is dynamically loaded to a dynamic area from external starting equipment by a loading control block according to an internal address mapping table, so that seamless switching of different quantization precision is realized on the hardware level, and the whole chip does not need to be burnt again. According to the design, through a modularized and reconfigurable hardware structure, the limitation of fixed-precision hardware in coping with diversified AI models is effectively solved, and the deployment flexibility and energy efficiency are remarkably improved.

A method (of manufacturing a semiconductor device) includes migrating a circuit design from a first netlist corresponding with a first semiconductor process technology (SPT) to a second netlist corresponding with a second SPT, the migrating including: expanding a first version of the first netlist and a first precursor of the second netlist correspondingly to form a second version of the first netlist and a second precursor of the second netlist; before conducting (A) placement and routing (P&R) of a layout diagram corresponding to the second netlist or (B) a static timing analysis of the layout diagram; performing a logic equivalence check (LEC) between the second version of the first netlist and the second precursor of the second netlist, thereby identifying migration errors, and revising the second precursor of the second netlist to reduce the migration errors, thereby resulting in a third precursor of the second netlist.

The invention provides a circuit design simulation method and system for an angle sensor, and relates to the technical field of circuit design simulation, and the method comprises the steps: constructing a circuit topological structure diagram of the angle sensor, carrying out the multi-physics coupling simulation, and obtaining an output characteristic curve of the angle sensor; performing nonlinear error analysis, constructing an error compensation mapping set, performing parameter iterative optimization, and generating a target compensation parameter combination; and the target compensation parameter combination is embedded into the circuit topological structure diagram for closed-loop verification, and a simulation verification report is generated. According to the method and the device, the technical problem that deviation exists between a simulation result and reality in a complex dynamic environment due to poor environmental adaptability and compensation lag existing in circuit design simulation is solved, intelligent compensation of nonlinear errors is realized through multi-physics field coupling simulation and segmented compensation, and the precision and the efficiency of circuit design simulation are improved.

A key block can be generated from a session key used by a computer-based design tool for a circuit design by encrypting the session key using computer hardware. The key block can be divided, by the computer hardware, into a plurality of sub-blocks. A plurality of enhanced sub-blocks can be generated by the computer hardware by encrypting each sub-block of the plurality of sub-blocks with a different key of a plurality of keys corresponding to a plurality of Intellectual Property (IP) cores of the circuit design. The plurality of enhanced sub-blocks can be stored in a memory.

The invention discloses a clock domain crossing circuit timing sequence closed-loop optimization method and system, and relates to the technical field of integrated circuit design, and the method comprises the steps: reading a circuit netlist and timing sequence constraints, recognizing a converged path, and carrying out the clustering analysis to form a plurality of path groups; establishing a time sequence analysis model, and dynamically calculating the maximum delay constraint of the data signal in the path group; matching and executing at least one time sequence optimization strategy for each path group; and carrying out closed-loop time sequence verification, retaining a legacy path set which does not meet the constraint, and repeatedly executing the time sequence optimization strategy until a convergence condition is reached or the maximum preset number of iterations is reached. According to the method disclosed by the invention, the cross-domain path needing to be optimized in the DMUX structure can be accurately positioned without manual intervention, so that the path identification efficiency is improved, constraint omission or grouping deviation caused by manual operation is avoided, design defects are reduced from the source, and the design reliability of a chip is improved.

The present application relates to the field of solution measurement, in particular to an electrode conductivity sensor conductivity measurement circuit and method, first, the AC excitation generation module generates an amplitude and frequency adjustable AC sine excitation signal under the control of the single-chip microcomputer; then the AC sine excitation signal passes through the precision resistor R0 and the conductivity cell of the electrode sensor to the system ground in turn; then the differential amplification circuit differentially amplifies the voltage between the precision resistor R0 and the electrode sheet of the conductivity cell; the amplified voltage signal is collected by the ADC, and then the voltage data is transmitted to the single-chip microcomputer; finally, the single-chip microcomputer can obtain the conductivity of the solution after the collected voltage data is operated. The present application directly collects the peak and valley voltage values of the AC signal, subtracts to obtain the amplitude of the AC signal, and does not need a rectification filter circuit to detect the amplitude of the AC signal, which can quickly respond to the change of the solution conductivity, eliminates the influence of common-mode interference factors, and simplifies the circuit design.

The invention discloses a high-speed level conversion circuit, and belongs to the technical field of integrated circuit design, the circuit mainly comprises an input signal processing module, a voltage boosting module, a differential signal generation module, a signal amplification module and an output module, the input signal processing module converts a low-voltage input signal into a complementary logic signal pair; the voltage boosting module raises the voltage amplitude of the complementary logic signal by using a charge pump principle; the lifted signal drives a thick gate transistor in the differential signal generation module to generate a differential signal; the signal amplification module adopts a cross coupling structure to quickly amplify the differential signal; and finally, the output module outputs a high-voltage domain signal in an inverted manner. By introducing voltage bootstrap before gate driving, the overdrive voltage of a core switch tube is remarkably increased, so that the problem of low conversion speed of a traditional level conversion circuit is effectively solved on the premise of not increasing the device size and static power consumption, and high-speed and high-efficiency level conversion is realized.

The invention discloses an automatic batch interface connection method, which relates to the technical field of interface connection, and comprises the following steps: S1, confirming an input / output port; s2, parameterizing macro definition; s3, a connection code is generated; s4, generating interfaces in batches; and S5, carrying out batch connection. According to the method, automatic generation of batch interface connections is achieved through parameterized macro definition, the requirement for manual coding is reduced, the risk of human errors is reduced, the efficiency of the verification process is improved, a designer only needs to specify macro parameters in the configuration file, a large number of different interface connections can be rapidly configured, complex connection codes do not need to be written, and the method is convenient and fast to operate. The reusability of codes is enhanced through parameterized macro definition, the same macro definition can be repeatedly used in different items or different verification platforms, high flexibility is provided through the parameterized macro definition, interface connection is supported to be rapidly modified and adapted, and the large-scale integrated circuit design method and device can adapt to various complex scenes in the large-scale integrated circuit design process.

The invention relates to the technical field of hybrid energy, and particularly provides a self-adaptive power distribution multi-source parallel mobile power supply system which comprises a multi-source input interface, a multi-channel input adjusting module, an energy storage module, an energy storage bidirectional adjusting module, a self-adaptive power distribution module and a power output interface. The method is characterized in that an MPPT algorithm is independently executed for each heterogeneous power supply through a multi-channel input adjusting module, and energy extraction is maximized; based on load detection and a multi-stage feedback mechanism, dynamic self-adaptive power distribution is realized; a multi-channel input end is adjusted into a unified standard bus voltage, and an output end dynamically adjusts the voltage according to a load, so that the energy conversion efficiency is improved while the use convenience is ensured; and the standard lithium battery units spliced without tools and the modular circuit design are adopted, so that the flexible combination and disassembly of the system are realized. According to the invention, the complexity of the hybrid energy system is greatly reduced, the system stability is improved, and efficient and lightweight hybrid energy mobile power supply is realized.

The invention discloses a finger-storage-multiply-accumulate three-stacked floating-point number in-memory computing system, and belongs to the field of application-specific integrated circuit design. According to the system, a three-stack type floating-point number calculation framework is designed, a pointing shift and mantissa multiply-accumulate module is designed, and floating-point number multiply-accumulate calculation of global pointing is supported. Compared with a traditional parallel floating-point multiply-accumulate circuit, the parallel floating-point multiply-accumulate circuit has the advantages that a calculation process of global alignment shifting and mantissa multiply-accumulate in sequence and a three-stack type calculation framework are adopted, similar calculation precision is achieved with smaller hardware overhead, low hardware overhead and high calculation precision are both considered, and the comprehensive performance of the calculation framework and the circuit is improved.

The invention relates to a core particle thermal simulation finite element mesh generation method based on a neural network. The method comprises a geometric and thermal feature extraction module, a temperature distribution prediction module and an intelligent grid optimization module. The geometric and thermal feature extraction module realizes accurate prediction of chip temperature distribution through tensor construction in combination with multi-scale convolution, pyramid pooling and deformable convolution; the intelligent grid optimization module adaptively optimizes a finite element grid through coupling of thermal gradient and geometric constraint, reduces the number of grid units and improves calculation efficiency. According to the method, deep learning and finite element mesh generation are combined for the first time, a traditional iterative mesh refinement process is replaced by predicting heat distribution through a neural network, the mesh generation speed is remarkably increased, and meanwhile, the thermal simulation precision is kept within 0.8%. The method is particularly suitable for a complicated 2.5 D / 3D chip packaging structure, can effectively cope with thermal management challenges in modern integrated circuit design, and provides a rapid and accurate thermal simulation tool for chip design.

The invention relates to the technical field of integrated circuit design, in particular to a three-dimensional stacked memory controller supporting lateral expansion, which comprises a memory control logic unit connected with an interface expansion unit and a mode configuration unit, the interface expansion unit and the mode configuration unit are connected with a near memory calculation unit, the near memory calculation unit is connected with the memory control logic unit, and the memory control logic unit is connected with the interface expansion unit. And the on-chip cache unit is connected with the memory control logic unit. The on-chip cache unit is used for storing high-frequency access data; the memory control logic unit is used for forming a hierarchical memory architecture; the interface expansion unit is used for transversely accessing the low-speed memory; the mode configuration unit enables on-chip high-speed cache, three-dimensional stacked memory and low-speed memory access to be independently Bypass; the near memory calculation unit is used for providing transposition, stepping, compression and direct memory calculation functions. Therefore, the problems that in the prior art, a three-dimensional stacked memory and a low-speed memory cannot be efficiently organized and matched, development is complex, and a hierarchical framework is missing are solved.

The invention provides a circuit optimization method, system and device based on model predictive control and a medium, and relates to the technical field of integrated circuit design, and the method comprises the steps: constructing a circuit knowledge graph and a simulation data lookup table according to a circuit design experience document and circuit simulation data; initializing a search feasible region of design points according to the circuit knowledge graph and the simulation data lookup table, and performing multi-point exploration Bayesian optimization to obtain a candidate design point set of the current circuit; and according to the simulation data lookup table, the circuit knowledge graph and the candidate design point set, in combination with a model prediction control framework, executing a reinforcement learning method to obtain an optimal design point of the current circuit, and providing optimal configuration of the current circuit. According to the method, the consumption of simulation computing resources is effectively reduced, the optimization efficiency is improved, and meanwhile, the design is ensured to meet the multi-target performance requirements of gain, power consumption, bandwidth and the like.

The invention relates to the technical field of integrated circuit design and verification, and discloses a chip simulation verification acceleration method, device and equipment and a storage medium, and the method comprises the steps: obtaining simulation analysis of a tested design file and excitation, obtaining a corresponding simulation result, analyzing a module occupying the most simulation time and memory according to the simulation result, and obtaining a simulation result; the method comprises the following steps of: decomposing a simulation process of a whole chip into a plurality of simulation operation tasks by combining a design requirement and a function definition of the chip; distributing the disassembled operation tasks to a multi-core processor for block simulation; and setting a dynamic performance optimization option DPO, performing multiple tests to collect data, and generating a simulation verification result based on a simulation result and an original design expectation. According to the method, the to-be-tested design is disassembled for layered compiling simulation, and the DPO is set for dynamic performance optimization, so that the simulation speed is increased, the chip design period is shortened, the development cost is reduced, and the requirement for rapid development of modern large-scale chips is met.

The invention discloses a band-gap reference source high-order curvature compensation method based on an operational amplifier, and belongs to the technical field of high-precision analog integrated circuit design, and the method comprises the steps: generating an absolute temperature proportion PTAT current and an absolute temperature complementary CTAT current; generating a high-order curvature compensation voltage based on the PTAT current and the CTAT current; amplifying the generated high-order curvature compensation voltage through an operational amplifier, and superposing the amplified high-order curvature compensation voltage to a band-gap reference output stage to obtain compensated band-gap reference output voltage; and carrying out band-gap reference output calibration on the compensated band-gap reference output voltage so as to ensure that the temperature drift coefficient of the output band-gap reference voltage in the preset temperature range is smaller than a preset threshold value. According to the invention, high-order elimination of base-emitter voltage nonlinearity can be realized in a wide temperature range, and a relatively low temperature coefficient and low noise are achieved.

The invention discloses a fault-considered spacecraft integrated chip interface circuit potential path analysis method, a storage medium and equipment, and belongs to the technical field of integrated circuit design and fault analysis. The method aims at solving the problem that an analysis method for a path under a failure mechanism under different environmental stresses is lacked. The method comprises the following steps: constructing an interface circuit simulation model of an integrated device based on a common interface circuit and a potential path structure in a spacecraft electronic system, then supplementing degradation mechanisms in various task stress environments, and determining a fault mode table of the interface circuit of the integrated device; a circuit simulation method is adopted to carry out potential path analysis considering fault factors on an interface circuit under a typical task profile, a fault path response feature library of the interface circuit under the task profile is obtained, then a constraint clue table for interface circuit design is formed, an interface circuit failure associated fault tree model is constructed, and the interface circuit failure associated fault tree model is constructed. And calibrating a relation path between various potential paths and device degradation or local failure for failure positioning and path checking.