2269 results about "Circuit design" patented technology

The invention relates to the technical field of circuit design, in particular to a digital circuit simulation design method and system. The method comprises the following steps: identifying a design demand document, performing deep semantic analysis and demand constraint mining, and constructing a demand specification constraint parameter set; performing demand complexity evaluation and multi-level division according to the demand specification constraint parameter set, and constructing a basic circuit architecture design blueprint; circuit routing path planning is carried out according to the basic circuit architecture design blueprint, and a standardized circuit topology network is constructed; performing electric signal propagation simulation on the standardized circuit topology network, and performing global circuit adaptability adjustment to obtain a circuit topology design scheme; and carrying out an extreme condition simulation test based on the circuit topology design scheme, and carrying out comprehensive performance evaluation to obtain a circuit performance evaluation report. By deeply understanding the user demand intention, the circuit layout matched with the user demand is designed, and the overall circuit performance is improved.

The invention provides a chip power supply network compensation method and device, equipment, a storage medium and a program, relates to the technical field of integrated circuits, in particular to a chip and circuit design technology, can be applied to an application scene of chip test optimization, and the method comprises the following steps: determining a dynamic power consumption violation area of a current power supply network of a target chip; performing compensation priority classification on the dynamic power consumption violation area according to the voltage drop violation distribution information of the dynamic power consumption violation area to obtain a violation priority classification area; and determining a local power supply network compensation strategy of each violation priority classification area according to the compensation priority of the violation priority classification area. According to the embodiment of the invention, the efficiency and precision of chip power supply network compensation can be improved.

The invention relates to the technical field of integrated circuit design and artificial intelligence hardware acceleration, and particularly discloses a quantization precision adaptive switching hardware acceleration architecture. Hardware is divided into a static area and a dynamic area, wherein the static area comprises a pre-processing module, a post-processing module, a control module and a reconfigurable logic loading control block which run all the time; the dynamic region bears a quantization and inverse quantization module composed of a plurality of reconfigurable logic units. The method is characterized in that a model precision instruction is analyzed through a control module, and a reconfigurable logic file with corresponding precision is dynamically loaded to a dynamic area from external starting equipment by a loading control block according to an internal address mapping table, so that seamless switching of different quantization precision is realized on the hardware level, and the whole chip does not need to be burnt again. According to the design, through a modularized and reconfigurable hardware structure, the limitation of fixed-precision hardware in coping with diversified AI models is effectively solved, and the deployment flexibility and energy efficiency are remarkably improved.

The invention discloses a clock domain crossing circuit timing sequence closed-loop optimization method and system, and relates to the technical field of integrated circuit design, and the method comprises the steps: reading a circuit netlist and timing sequence constraints, recognizing a converged path, and carrying out the clustering analysis to form a plurality of path groups; establishing a time sequence analysis model, and dynamically calculating the maximum delay constraint of the data signal in the path group; matching and executing at least one time sequence optimization strategy for each path group; and carrying out closed-loop time sequence verification, retaining a legacy path set which does not meet the constraint, and repeatedly executing the time sequence optimization strategy until a convergence condition is reached or the maximum preset number of iterations is reached. According to the method disclosed by the invention, the cross-domain path needing to be optimized in the DMUX structure can be accurately positioned without manual intervention, so that the path identification efficiency is improved, constraint omission or grouping deviation caused by manual operation is avoided, design defects are reduced from the source, and the design reliability of a chip is improved.

The invention discloses a high-speed level conversion circuit, and belongs to the technical field of integrated circuit design, the circuit mainly comprises an input signal processing module, a voltage boosting module, a differential signal generation module, a signal amplification module and an output module, the input signal processing module converts a low-voltage input signal into a complementary logic signal pair; the voltage boosting module raises the voltage amplitude of the complementary logic signal by using a charge pump principle; the lifted signal drives a thick gate transistor in the differential signal generation module to generate a differential signal; the signal amplification module adopts a cross coupling structure to quickly amplify the differential signal; and finally, the output module outputs a high-voltage domain signal in an inverted manner. By introducing voltage bootstrap before gate driving, the overdrive voltage of a core switch tube is remarkably increased, so that the problem of low conversion speed of a traditional level conversion circuit is effectively solved on the premise of not increasing the device size and static power consumption, and high-speed and high-efficiency level conversion is realized.

The invention discloses a fault-considered spacecraft integrated chip interface circuit potential path analysis method, a storage medium and equipment, and belongs to the technical field of integrated circuit design and fault analysis. The method aims at solving the problem that an analysis method for a path under a failure mechanism under different environmental stresses is lacked. The method comprises the following steps: constructing an interface circuit simulation model of an integrated device based on a common interface circuit and a potential path structure in a spacecraft electronic system, then supplementing degradation mechanisms in various task stress environments, and determining a fault mode table of the interface circuit of the integrated device; a circuit simulation method is adopted to carry out potential path analysis considering fault factors on an interface circuit under a typical task profile, a fault path response feature library of the interface circuit under the task profile is obtained, then a constraint clue table for interface circuit design is formed, an interface circuit failure associated fault tree model is constructed, and the interface circuit failure associated fault tree model is constructed. And calibrating a relation path between various potential paths and device degradation or local failure for failure positioning and path checking.

The invention discloses a multifunctional broadband metamaterial structure with a polarization independent characteristic and a control method. The structure has a switchable tri-state function and a complete polarization operation capability irrelevant to polarization. By introducing the guide circuit design, three different electromagnetic energy regulation and control modes of second-order filtering, broadband absorption and multi-reflection shielding are efficiently integrated in the same structure, the real broadband performance in the band is realized, and meanwhile, the higher reflection efficiency outside the band is kept. Different from a traditional method which depends on a broadband lossless reflecting layer to expand the transmission bandwidth of an absorption structure, the three arrays are considered as an integral operating system, support three-state switching operation and have real broadband and efficient behaviors.

The invention discloses a balanced three-valued dynamic logic gate implementation circuit based on memristors. The balanced three-valued dynamic logic gate implementation circuit comprises a balanced three-valued dynamic NOT gate circuit, a balanced three-valued dynamic NOR gate circuit and a balanced three-valued dynamic NAND gate circuit which are implemented according to the memristors. The dynamic logic circuit provided by the invention is widely applied to the design of a super-large-scale integrated circuit, and can reduce the circuit area and improve the circuit speed.

The invention discloses an ultrahigh-precision low-noise band-gap reference circuit, and relates to the technical field of integrated circuit design, the ultrahigh-precision low-noise band-gap reference circuit comprises a starting turn-off circuit, a reference core circuit, a high-order temperature compensation circuit and a digital trimming circuit, the starting turn-off circuit is connected with the reference core circuit, and the high-order temperature compensation circuit is connected with the digital trimming circuit through a Brokaw type band-gap reference topological structure. Accurate compensation of the voltage is achieved through deep negative feedback of the operational amplifier and a high-order temperature compensation circuit, and the temperature drift of the reference voltage is as low as 0.5-2 ppm / DEG C (-40 DEG C to 130 DEG C) and is increased by 5-10 times compared with a traditional band-gap reference (5-10 ppm / DEG C). The power consumption of the system can be saved by turning off the circuit when the circuit is not used, meanwhile, the digital trimming module is added to replace laser trimming in traditional engineering, the upper limit of the trimming range is improved, high-order temperature compensation and the digital trimming circuit are introduced, the precision of output voltage is improved, different devices are replaced, and the noise of the circuit is reduced. The problems that a traditional high-voltage band-gap reference temperature coefficient is high and noise is large are solved.

The invention relates to the technical field of circuit board conductivity detection, and discloses a circuit board conductivity detection method and system based on deep learning, and the method comprises the steps: obtaining high-resolution image data and circuit design parameters of a to-be-detected circuit board, and generating a circuit board feature data set; calculating theoretical impedance distribution of each area of the circuit board by using a physical constraint neural network based on the circuit board feature data set, and outputting an impedance prediction parameter set; inputting the impedance prediction parameter set and the circuit symbol rule into a neural symbol inference device to generate a conductance fault diagnosis result; and obtaining diagnosis results of a plurality of detection sites, executing cross-site diagnosis fusion, and outputting a unified circuit board conductivity detection report. The method overcomes the limitation that a traditional visual detection method cannot identify electrical characteristic defects, and solves the detection problem of hidden faults such as discontinuous impedance of the high-frequency circuit board.

The embodiment of the invention provides an interlaced PFC circuit and a phase locking method of the interlaced PFC circuit, the interlaced PFC circuit comprises n PFC circuits, n driving circuits and a processor, and the n PFC circuits comprise a main phase PFC circuit and a slave phase PFC circuit. The phase locking method comprises the steps that a processor obtains a master phase driving signal input to a master phase PFC circuit and obtains a slave phase driving signal input to a slave phase PFC circuit; capturing a first rising edge of the slave phase driving signal after the first rising edge of the master phase driving signal occurs to obtain first time; capturing a second rising edge of the master phase driving signal after the first rising edge of the slave phase driving signal occurs to obtain a second time; and controlling the conduction duration of the slave phase driving signal according to the difference value between the first time and the second time. Therefore, quick closed-loop phase locking of the multi-phase interleaving parallel circuit is realized, full-range quick phase locking is realized under the conditions of non-valley bottom opening and valley bottom opening, meanwhile, the circuit design is simplified, and accurate phase locking can be realized without redundant hardware circuits.

The invention belongs to the technical field of analog integrated circuit design and memory read-write, and provides a multi-valued RRAM read-write circuit with a write-and-read function. The multi-valued RRAM read-write circuit is a multi-port device capable of performing read-write simultaneously, in write operation, a low dropout regulator is utilized to provide voltage for the RRAM circuit and the standard resistance circuit, mirror current is generated, the resistance value of the RRAM is set to be the total resistance of the standard resistance circuit, an operational amplifier is connected into the circuit through a CMOS switch, and feedback is formed to stabilize the voltage at the two ends of the RRAM; and in the read operation, the CMOS switch is used for disconnecting the operational amplifier, and the voltage at the two ends of the RRAM device is directly read. Compared with an existing multi-valued read-write circuit, the multi-valued RRAM read-write circuit has the advantages that write-and-read multi-valued RRAM read-write is realized, and meanwhile, the read-write circuit is not separated, so that the write-in speed is increased, and the area of the read-write circuit is saved.

The invention discloses a time sequence convergence method and device based on a clock tree, and relates to the technical field of circuit design. The method comprises the following steps: performing automatic layout on devices; determining a time sequence path needing to be optimized in the one-to-many structure time sequence path; performing establishment time sequence margin optimization, and determining a setting pattern of useful clock skew adjustment based on the optimized establishment time sequence margin; determining the number of buffers based on the setting pattern of useful clock skew adjustment and the optimized setup time sequence margin, and generating a clock tree; on the basis of the generated clock tree, determining whether the time sequence violation of the retention time of the time sequence path needing to be optimized meets a preset requirement or not, and if the preset requirement is not met, adjusting the setting pattern of the useful clock skew adjustment, and returning to the step of generating the clock tree; and completing automatic wiring based on the clock tree meeting the predetermined requirement. According to the invention, the problem of power consumption increase caused by restoration of Hold time sequence violation can be solved.

Systems, apparatuses, methods, and computer program products are disclosed for selecting a quantum circuit. An example method includes identifying, by communications hardware, a set of input attributes. The example method also includes determining, by quantum circuit selection circuitry, a set of quantum circuit selection criteria based on the set of input attributes. The example method also includes choosing, by the quantum circuit selection circuitry, a quantum circuit design from a collection of pre-determined quantum circuit designs and based on the set of quantum circuit selection criteria. The example method also includes generating, by quantum circuit generation circuitry, a quantum circuit for the chosen quantum circuit design. The example method also includes outputting, by the communications hardware, the generated quantum circuit.

The invention relates to the technical field of integrated circuit design, computer system structures and embedded systems, in particular to a high-real-time interrupt management system and method based on an RISC-V. The system comprises an improved platform-level interrupt controller and an optimized processor internal interrupt processing unit. The system and the method are in tight coupling cooperative work through a special interruption field interface and a system bus, and the system further comprises a core local interrupter, an SRAM, an APB bus matrix and other components. The improved platform-level interrupt controller is responsible for sampling, gating, arbitration, flow control and direct memory access transmission of external interrupt, and a plurality of functional modules are arranged in the improved platform-level interrupt controller; an interrupt processing unit in the processor is responsible for hardware handshake, vector jump, nested control and tail biting mechanism implementation. Through hardware field management, multi-level priority arbitration, hardware nesting and tail biting mechanisms, delay and overhead caused by software intervention in a traditional architecture are eliminated, nanosecond response is achieved, the system throughput rate is increased, the software development threshold is lowered, and the method is suitable for strong real-time scenes.

The invention discloses a frequency converter multi-stage cooperative rapid overcurrent protection circuit, and the overcurrent protection circuit cooperates with an IGBT inverter circuit, an IGBT drive circuit, a current sampling circuit and a master control MCU of a frequency converter to construct a three-stage cooperative protection system composed of hardware-stage extreme rapid protection, hardware-stage rapid protection and software-stage intelligent protection. And independent action and information interaction between the stages can be realized through circuit design. Compared with the prior art, protection blind areas are eliminated, nanosecond-microsecond level extreme protection is achieved, a multiple and high-reliability redundancy protection system is constructed, intelligent grading processing of faults is achieved, and the diagnosability of the system is enhanced.

The invention discloses a fixed vacuum capacitor with a short circuit function, which comprises a vacuum capacitor body, a movable conducting rod is arranged in the vacuum capacitor body, and the conducting rod is configured to connect two electrode groups of the vacuum capacitor body when the conducting rod deflects along a set direction so as to realize short circuit of the vacuum capacitor body. The movable conducting rod is arranged in the vacuum capacitor body, and when the conducting rod deflects, the two electrode groups can be connected to realize short circuit, so that the fixed vacuum capacitor has a short circuit function under the condition that the volume of the fixed vacuum capacitor is not changed; according to the design, the tedious problem that the circuit design of the radio frequency matcher needs to be changed by dismounting the fixed vacuum capacitor in specific scenes such as test and debugging of the radio frequency matcher and design of double-frequency and multi-frequency matchers is effectively solved, and the operation convenience is greatly improved; the specific requirements of a user for rapidly switching the working frequency and changing the circuit design of the radio frequency matcher are met, and the working efficiency is improved.

The invention relates to the technical field of digital-analog hybrid integrated circuit design, and particularly provides a FlexRay bus receiver with low noise and wide common-mode input range, which is characterized in that a common-mode voltage division module receives a differential signal output by a bus and carries out voltage division, and then a pre-amplification module carries out amplitude limiting amplification on the signal after voltage division; the hysteresis comparator module generates threshold hysteresis and generates a logic level signal based on the signal after amplitude limiting amplification, and the digital logic receiving module receives and processes the logic level signal, generates a receiving data signal and transmits the receiving data signal to an external controller. According to the invention, the differential signal pair received on the FlexRay bus is subjected to voltage division and amplitude limiting amplification, so that a wider common-mode input range is provided, the problem of large ground potential difference is solved, and the capability of suppressing common-mode noise and the communication stability are improved. Meanwhile, the hysteresis comparator module suppresses noise false triggering by generating threshold hysteresis, and the anti-noise capability of the receiver is remarkably improved.

The invention discloses a multi-channel high-speed low-power-consumption successive approximation analog-to-digital converter, system and method, and relates to the technical field of analog integrated circuit design, the analog-to-digital converter comprises an M-bit auxiliary ADC, n N-bit main ADCs, a multiplexer and a digital error correction circuit, an M-bit non-binary digital code is obtained through quantization of the auxiliary ADC, and the N-bit non-binary digital code is obtained through quantization of the N-bit main ADCs. A group of N-M-bit non-binary digital codes are obtained through quantization of multiple paths of main ADCs respectively, then combination and binary conversion are carried out on M-bit non-binary digital codes and each group of N-M-bit non-binary digital codes through a digital error correction circuit, n groups of binary digital codes are obtained and output, and multi-channel sampling, quantization, conversion and output are achieved. The device has the characteristics of low power consumption, high conversion speed and high precision, and the conversion speed and precision can be improved while the characteristic of low power consumption is maintained.

The embodiment of the invention provides a gallium nitride totem-pole circuit and a control evaluation system of the gallium nitride totem-pole circuit, and the circuit comprises a gallium nitride power device which comprises an integrated semiconductor tube and an integrated drive circuit; the isolation chip is connected between the control module and an integrated driving circuit of the gallium nitride power device and is used for sending the pulse width modulation signal sent by the control module to the integrated driving circuit, and the isolation chip can ensure the electrical safety of weak current and strong current; the gallium nitride power device is used for controlling the on-off state of the integrated semiconductor tube through the integrated driving circuit according to the pulse width modulation signal sent by the isolation chip; under the condition that the integrated semiconductor tube is conducted, the voltage is output to the control module based on the bus voltage through the integrated semiconductor tube, and the driving circuit is integrated on the gallium nitride power device, so that the circuit design can be simplified, overcurrent protection and undervoltage protection are simultaneously carried out, and the safety of the gallium nitride totem pole circuit is improved.

The invention relates to the technical field of integrated circuit design, in particular to a noise shaping assembly line successive approximation type analog-to-digital converter and a control method. Comprising a first stage including an auxiliary successive approximation analog-to-digital converter and a first stage voltage processing module; the second stage comprises a dual-channel noise shaping successive approximation type analog-to-digital converter and a loop filter; the input end of the residual amplifier is connected with the first-stage voltage processing module, and the output end of the residual amplifier is connected with the noise shaping successive approximation type analog-to-digital converter; the first input end of the digital code aligner is connected with the output end of the comparator of the auxiliary analog-to-digital converter, and the second input end of the digital code aligner is connected with the output end of the second-stage comparator. According to the invention, the analog-to-digital conversion speed can be accelerated, the influence of a zero point on a residual voltage amplification coefficient is reduced, the conversion time is shortened, and the input and output common-mode voltages of the time domain converter are stabilized.

The invention relates to the technical field of integrated circuit design automation, and discloses an integrated circuit design whole-process collaborative verification and consistency guarantee method, which comprises the following steps of: constructing a unified design data model, and representing design data from function specifications to physical layout by using a multi-level attribute graph structure; establishing a design intention keeping mechanism, and tracking the transmission of the design intention in the hierarchical refinement process through intention semantic annotation, cross-level entity mapping and intention keeping degree evaluation; executing a hybrid verification strategy, combining formalized verification with dynamic simulation, and guiding verification resource allocation through a coverage rate feedback mechanism; performing constraint consistency check, performing constraint comparison at key nodes of the design process, and automatically identifying and positioning constraint conflicts; according to the method, the capture time of design errors can be brought forward by 80%, the number of design iterations is reduced by 40%, and the design quality and efficiency are remarkably improved.

The invention relates to the technical field of circuit boards, in particular to a method for improving local thickness unevenness of a rigid-flex board and the rigid-flex board. The method comprises the following steps: S1, extracting residual copper rate distribution, setting a residual copper rate threshold value, and identifying a glue filling area and a non-glue filling area of a rigid-flex board plane according to the residual copper rate threshold value; s2, windowing parameters are obtained according to the hole ring height and diameter of the non-glue-filling area, and windowing is conducted on the cover film according to the windowing parameters; after windowing is completed, the covering film is attached to the corresponding position, the hole ring is sleeved with the window, and the local thickness of the rigid-flex board is consistent; or dividing a high-voltage region and a low-voltage region in the non-glue filling region according to the voltage level and the signal characteristic in the circuit design; the copper is thickened in the high-voltage area, and a step is formed by the thickened copper layer in the high-voltage area; when the glue filling area is filled with glue, pressure difference is formed, the glue layer flows towards the low-pressure area, uniform filling of the glue layer is achieved, and the local thickness of the rigid-flex board is consistent. According to the invention, uneven local thickness of the rigid-flex board is improved.

The invention belongs to the related technical field of integrated circuit design, and discloses an integrated circuit design process collaborative optimization method and system, and the optimization method comprises the steps: S1, randomly generating a plurality of groups of process parameters; s2, TCAD simulation is carried out, and an electrical characteristic curve of the device is obtained; s3, extracting electrical characteristics and inputting the electrical characteristics into the intelligent parameter extraction model to obtain compact model parameters; s4, inputting the compact model parameters into the SPICE model, and generating an integrated circuit layout by using an automatic layout generation system; s5, taking the optimized circuit performance index as an optimization target, and adopting a Bayesian optimization method to generate an optimal process parameter of a next iteration round; and S6, judging whether an iteration termination condition is met or not, if not, skipping to S2, and if yes, outputting the current process parameters. According to the method, the process / design barrier can be broken, it is ensured that the process development and the circuit design process can be collaboratively carried out, the whole optimization process is completely automatic, and the high-precision and high-efficiency collaborative optimization process is achieved.

The invention relates to the technical field of integrated circuit design, in particular to a wafer-level chip architecture design-oriented heuristic layout method and system, and the method comprises the steps: core particle combination exploration: taking an exchange chip as a center, and generating a plurality of core particle combinations according to the core particle type, the interface type and the communication protocol consistency; a kernel in-group layout algorithm: performing multi-objective optimization layout on each core particle combination based on a genetic algorithm, wherein optimization objectives comprise area utilization rate, total wiring length and corner number; and wafer overall performance evaluation: copying and expanding the core group layout to the whole wafer, calculating a comprehensive performance index, and outputting a plurality of wafer layouts with the highest comprehensive performance index. According to the method, the wafer-level chip layout architecture with the smallest area, the shortest line length, the lowest corner number, the highest computing power and the lowest cost can be efficiently explored in limited time, the chip design efficiency is improved, and the design cost is reduced.

The invention provides an automatic design method and equipment of a storage circuit and a storage medium. The method comprises the following steps: acquiring demand parameters input by a user in a compiler; importing a plurality of circuit units after the standard memory circuit is disassembled into a compiler; determining a target circuit architecture according to the demand parameters; calling a plurality of corresponding circuit units from a compiler according to the demand parameters; and splicing the called circuit units to positions corresponding to the target circuit architecture to obtain a target storage circuit meeting the demand parameters. On this basis, the demand parameters of the user and the plurality of circuit units obtained by disassembling are input into the compiler, and the target circuit architecture is determined through the compiler, the plurality of corresponding circuit units are called, and the splicing of the plurality of circuit units is executed, that is, the whole design of the target storage circuit can be automatically completed in the compiler. The manual participation degree is reduced, the overall efficiency is high, the possibility of manual misjudgment can be completely eradicated, and the reliability of the whole circuit design is ensured.

The invention relates to the cross technical field of computer-aided engineering and audio equipment design, discloses a circuit design simulation-based disc player design optimization method and system, and aims to solve the problem that the existing disc player design depends on physical prototype trial-manufacture and subjective listening evaluation and lacks multi-physical domain co-simulation capability. The method comprises the following steps: constructing a unified multi-physical domain model comprising a mechanical transducer, an electromechanical transducer and an electronic circuit sub-model; bidirectional coupling co-simulation based on the time sequence is executed, and an output electric signal is generated; extracting objective audio performance indexes such as total harmonic distortion and signal-to-noise ratio; and carrying out multi-objective optimization on the key design parameters by utilizing a genetic algorithm, and outputting a Pareto optimal scheme. The system comprises a model construction module, a co-simulation module, a performance index extraction module and an optimization module. Through high-fidelity full-link simulation and automatic optimization, the design efficiency and the audio fidelity are remarkably improved, and the research and development cost is reduced.

The invention discloses a chip reset control method and device, equipment and a medium, and relates to the technical field of integrated circuit design. The method comprises the following steps: determining a target chip comprising a plurality of functional modules, and constructing a reset matrix for the target chip according to reset requirements of the functional modules; loading and analyzing the reset matrix to determine a reset trigger condition of each functional module, and based on the reset trigger condition, generating a multi-stage reset control signal conforming to a reset control strategy through a preset general reset control circuit; distributing the multi-stage reset control signal to each functional module according to a preset reset time sequence so as to control each functional module to perform reset operation; and adjusting the dynamic control dimension parameters in the reset matrix in real time by presetting a dynamic configuration interface so as to perform reset adjustment and optimization on the target chip after tape-out. Through the technical scheme of the invention, the problems of low efficiency, time sequence conflict and insufficient flexibility in the traditional reset design can be solved.

The invention relates to the technical field of Internet of Things, in particular to a circuit for simultaneously converting UART (Universal Asynchronous Receiver / Transmitter) to multi-path different level communication, which comprises a double-USB input module, a power supply processing module, a USB-UART core conversion module and a multi-path level conversion module, the double-USB input module comprises an MINI-USB interface J6 and a USB-B interface J8, VBUS pins of the two interfaces are connected in parallel through a Schottky diode and then output to the power supply processing module, and data differential pair pins are connected in parallel and then connected to the USB-UART core conversion module; and the power supply processing module comprises an LDO (Low Dropout Regulator) voltage stabilizing chip and a filter capacitor, and is used for converting 5V voltage output by the double-USB input module into 3.3 V stable voltage. The circuit design that the UART is connected with various different levels for communication is adopted, the tool integration technology is achieved, the design that the two USB ports are connected in parallel is adopted, the compatibility of the USB data line can be effectively improved, the demands of customers are met, and the technical difficulty that one UART bus is connected with multiple USB ports is broken through.

The invention provides a storage unit type selection method and device, electronic equipment and a computer storage medium, and relates to the technical field of integrated circuit design. The method comprises the following steps: establishing a storage unit specification general table which can be generated by a target compiler, wherein the specification general table comprises a plurality of sub-tables; receiving a target depth and a target bit width of the storage unit required by a user; respectively generating a candidate scheme capable of realizing a target depth and a target bit width based on each sub-table to obtain a plurality of groups of candidate schemes; on the basis of a preset model selection principle, determining the candidate schemes, which can be matched with the target depth and the target bit width in a splicing mode, in all the candidate schemes as feasible schemes; based on a preset back-end physical constraint condition, selecting a global optimal scheme from the feasible schemes; the compiling general table is established in advance, multiple sets of candidate schemes are automatically established for each sub-table in the compiling general table, then layer-by-layer screening is performed according to a preset rule to determine a global optimal scheme, and the layout efficiency is improved.