48 results about "Resolution enhancement technologies" patented technology

One embodiment of the present invention provides a system that applies resolution enhancement techniques (RETs) selectively to a layout of an integrated circuit. Upon receiving the layout of the integrated circuit, the system identifies a plurality of critical regions within the layout based on an analysis of one or more of, timing, dynamic power, and off-state leakage current. The system then performs a first set of aggressive RET operations on the plurality of critical regions. The system also performs a second set of less aggressive RET operations on other non-critical regions of the layout.

A multiple mask and a multiple masking layer technique can be used to pattern a single IC layer. A resolution enhancement technique can be used to define one or more fine-line patterns in a first masking layer, wherein each fine-line feature is sub-wavelength. Moreover, the pitch of each fine-line pattern is less than or equal to that wavelength. The portions of the fine-line features not needed to implement the circuit design are then removed or designated for removal using a mask. After patterning of the first masking layer, another mask can then be used to define coarse features in a second masking layer formed over the patterned first masking layer. At least one coarse feature is defined to connect two fine-line features. The IC layer can be patterned using the composite mask formed by the patterned first and second masking layers.

A contrast-base resolution enhancing technology (RET) receives an indication of an edge fragment in a photolithographic design. The edge fragment has a tag classification that defines a contrast of the edge fragment. The contrast-based RET applies a resolution enhancement to the edge fragment based on the tag classification. The resolution enhancement introduces an additional feature in the photolithographic design. The additional feature changes the contrast of the edge fragment.

A method and apparatus for integrated circuit layout optimization are provided. In the conventional art, the major challenges in building integrated circuits (IC) at sub-wavelength geometries include i) to ensure the design intent is faithfully transferred onto silicon; ii) to ensure the design is manufacturable, or with acceptable yield subject to process variations. The present invention provides the method to process a layout database to optimize or correct or fix layout violations or enhancements. The layout violations are identified through various means such as design rules, recommended rules, timing/signal integrity/power constraints, lithography rules, Resolution Enhancement Technologies (RET) requirements and preferences, and process and manufacturing constraints. Particularly, the method, techniques and procedures of creating software tools of the present invention used to perform the layout violations or enhancements are disclosed.

A system and method for optimizing an illumination source to print a desired pattern of features dividing a light source into pixels and determining an optimum intensity for each pixel such that when the pixels are simultaneously illuminated, the error in a printed pattern of features is minimized. In one embodiment, pixel solutions are constrained from solutions that are bright, continuous, and smooth. In another embodiment, the light source optimization and resolution enhancement technique(s) are iteratively performed to minimize errors in a printed pattern of features.

A method of performing a resolution enhancement technique such as OPC on an initial layout description involves fragmenting a polygon that represents a feature to be created into a number of edge fragments. One or more of the edge fragments is assigned an initial simulation site at which the image intensity is calculated. Upon calculation of the image intensity, the position and/or number of initial simulation sites is varied. New calculations are made of the image intensity with the revised placement or number of simulation sites in order to calculate an OPC correction for the edge fragment. In other embodiments, fragmentation of a polygon is adjusted based on the image intensities calculated at the simulation sites. In one embodiment, the image intensity gradient vector calculated at the initial simulation sites is used to adjust the simulation sites and/or fragmentation of the polygon.

A system for calculating mask data to create a desired layout pattern on a wafer reads all or a portion of a desired layout pattern. Mask data having pixels with transmission characteristics is defined along with corresponding optimal mask data pixel transmission characteristics. An objective function is defined having one or more penalty functions that promote solutions representing a desired resolution enhancement technique. Optimization of the objective function determines the transmission characteristics of the pixels in the mask data that is used to create one or more corresponding masks or reticles.

A contrast-based resolution enhancing technology (RET) determines a distribution of contrast values for edge fragments in a design layout or portion thereof. Resolution enhancement is applied to the edge fragments in a way that increases the number of edge fragments having a contrast value that exceeds a predetermined threshold.

A method of calculating process conditions for performing optical and process correction (OPC) or other resolution enhancement techniques on a layout design. Process conditions are estimated on a layout database on a substantially uniform grid. Contour curves are created from the estimated process conditions. The contour curves are then compared against the features in the layout to determine edge placement errors. From the edge placement errors, OPC or other corrections for the features can be made.

An image reversal method is described that removes the etch resistance requirement from a resist. A high resolution resist pattern comprised of islands, lines, or trenches is formed with a large process window by exposing through one or more masks including phase edge masks and optionally with resolution enhancement techniques. A complementary material replacement (CMR) layer comprised of an organic polymer or material such as fluorosilicate glass which has a lower etch rate than the resist is coated over the resist pattern. CMR and resist layers are etched simultaneously to provide an image reversed pattern in the CMR layer which is etch transferred into a substrate. The method avoids edge roughness like bird's beak defects in the etched pattern and is useful for applications including forming contact holes in dielectric layers, forming polysilicon gates, and forming trenches in a damascene process. It is also valuable for direct write methods where an image reversal scheme is desired.

A method and apparatus for compensating for flare intensity variations across an integrated circuit. A layout description for a physical layer of an integrated circuit or portion thereof is divided into a number of regions such as adjacent tiles. An estimate of the flare intensity in each region is determined. The flare intensity values calculated are divided into a number of ranges. In one embodiment, a data layer in a layout description is defined for each range of flare values computed. Features to be printed in an area having a flare value in a particular range are associated with a corresponding additional data layer. The features associated with each additional data layer are analyzed with a resolution enhancement technique that is selected or adjusted to compensate for differing flare values occurring in the integrated circuit.

A multiple mask and a multiple masking layer technique can be used to pattern a single IC layer. A resolution enhancement technique can be used to define one or more fine-line patterns in a first masking layer, wherein each fine-line feature is sub-wavelength. Moreover, the pitch of each fine-line pattern is less than or equal to that wavelength. The portions of the fine-line features not needed to implement the circuit design are then removed or designated for removal using a mask. After patterning of the first masking layer, another mask can then be used to define coarse features in a second masking layer formed over the patterned first masking layer. At least one coarse feature is defined to connect two fine-line features, wherein the coarse feature(s) can be derived from a desired layout using a shrink/grow operation. The IC layer can be patterned using the composite mask formed by the patterned first and second masking layers.

The invention discloses a method for obtaining a space image of a non-ideal lithography system based on an Abbe vector imaging model. The specific steps comprise: rasterizing a mask pattern M into N * N sub-regions; rasterizing a light source surface into a plurality of point light sources according to the shape of a partially coherent light source, and showing coordinates of the point light source corresponding to each grid area with the coordinates (xs, ys) of the central point; calculating a space image I (Alphas, Betas) on a wafer in the non-ideal lithography system during illumination ofeach point light source; and superimposing the space image I (Alphas, Betas) corresponding to each point light source according to the Abbe method, and obtaining the space image I on the wafer in thenon-ideal lithography system during illumination of the partially coherent light source. The light source surface can be rasterized into multiple point light sources, and the functions of analyzing scalar aberrations and polarization aberrations of lithographic projection systems and defocus parameters of lithography systems can also be achieved. Therefore, the space image obtained in the method has high accuracy, and the method can be effectively applied in research on methods for optimization of resolution enhancement techniques.