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470 results about "Signal integrity" patented technology

Signal integrity or SI is a set of measures of the quality of an electrical signal. In digital electronics, a stream of binary values is represented by a voltage (or current) waveform. However, digital signals are fundamentally analog in nature, and all signals are subject to effects such as noise, distortion, and loss. Over short distances and at low bit rates, a simple conductor can transmit this with sufficient fidelity. At high bit rates and over longer distances or through various mediums, various effects can degrade the electrical signal to the point where errors occur and the system or device fails. Signal integrity engineering is the task of analyzing and mitigating these effects. It is an important activity at all levels of electronics packaging and assembly, from internal connections of an integrated circuit (IC), through the package, the printed circuit board (PCB), the backplane, and inter-system connections. While there are some common themes at these various levels, there are also practical considerations, in particular the interconnect flight time versus the bit period, that cause substantial differences in the approach to signal integrity for on-chip connections versus chip-to-chip connections.

Chip signal integrity test analysis method, device and equipment and storage medium

The invention relates to the field of chip testing, in particular to a chip signal integrity test analysis method, device and equipment and a storage medium. The method comprises the following steps: extracting a chip performance index based on a chip design requirement document; performing saturation frequency excitation setting based on the chip performance index to generate an excitation test signal; performing a multi-port signal excitation test and parallel signal sampling based on the excitation test signal to generate a high signal-to-noise ratio response data set; obtaining a chip layout design file; performing chip communication link analysis on the chip layout design file, and constructing communication line layout data; performing signal mapping and waveform quality evaluation on the communication line layout data based on the high signal-to-noise ratio response data set to obtain a node signal distortion rate; and performing signal integrity quantization and theoretical signal integrity score comparison based on the node signal distortion rate, and marking a fault node. According to the invention, the chip testing efficiency is improved, and the signal abnormal part of the chip is accurately and efficiently detected.
Owner:SHENZHEN XINZHIYUAN TECHNOLOGY CO LTD

High speed plug connector

Plug connectors for use with high speed signals. The connector includes an insulative housing having a base portion and a tongue portion extending from the base portion, and conductive terminals held by the housing. Each conductive terminal has a mating portion held on a side of the tongue portion, a tail portion extending out of the housing, and an intermediate portion held in the base portion. The conductive terminals comprise signal terminals and ground terminals. A shielding member is disposed in the housing and includes features configured to provide shielding to signal terminals and electrically connect ground terminals. The shielding member also includes features configured to improve impedance consistency along conduction paths. Such a configuration meets signal integrity requirements in connectors designed for higher frequencies, while conforming to a standard that constrains mating and mounting interfaces.
Owner:AMPHENOL COMML PROD (CHENGDU) CO LTD

3D packaging structure and manufacturing method thereof

The invention discloses a 3D packaging structure and a manufacturing method thereof, and the method employs a glass wafer as a first carrier plate, and solves the problems of reliability and signal interference caused by the mismatching of thermal expansion coefficients of an organic material adapter plate and a Si-based silicon bridge chip. In S1, a blind hole is etched by taking a glass wafer as a base material, and Cu is metallized and filled, and the thermal expansion coefficient of glass is similar to that of a silicon bridge, so that the risk of thermal stress deformation is reduced. And S2, through groove etching, temporary carrier plate bonding and thinning, a through groove hole is formed, and the rigid structure of the glass carrier plate maintains the stability of the packaging structure during high-density integration. And S3, the silicon bridge Die is embedded into the through groove hole, the low thermal expansion characteristic of the glass is well matched with the silicon bridge, the interface stress is reduced, the dielectric property of the glass support plate is excellent, the signal dielectric loss is reduced, and the signal integrity is improved by matching with the silicon bridge Die. And S4, after the functional chip is mounted on the adapter plate, the glass-based adapter plate ensures reliable connection, signal attenuation distortion is inhibited, and a reliable packaging scheme is provided for high-density integration.
Owner:ZHUHAI TIANCHENG ADVANCED SEMICON TECH CO LTD

Module FPC laminated structure optimization system based on signal integrity

The invention relates to the technical field of FPC (Flexible Printed Circuit) laminated structure optimization, in particular to a module FPC laminated structure optimization system based on signal integrity, which comprises a laminated parameter sensitivity extraction module used for defining the thickness of a dielectric layer, the thickness of a copper foil and a dielectric constant as closed interval values with upper and lower boundaries according to FPC design specifications. According to the method, the accumulated deviation area and the normalized confidence score are obtained in combination with integral operation, conversion from a frequency domain to a time domain and from qualitative analysis to quantitative evaluation is achieved, tiny flaws of impedance continuity are captured, inferior paths are screened based on the confidence score, and a physical junction area is positioned. The geometric gravity center of the deviation area is calculated to be matched with the slope and the length of the gradient line, a smoothly-transited geometric figure is constructed, structural compensation can be achieved in areas where impedance is prone to sudden change such as a reinforcing plate junction and covering film pressing, and signal reflection caused by physical sudden change of a stacked structure is eliminated.
Owner:万年联创显示科技有限公司

Nondestructive detection method and system for large-burial-depth pipeline

The invention discloses a large-burial-depth pipeline nondestructive detection method and system, and relates to the technical field of pipeline positioning. The system combines a region feasibility identification module, an initial positioning module, a multi-type nondestructive detection unit, a multi-path anomaly identification module, an underground structure matching module, an intelligent obstacle avoidance compensation module and a signal fusion module, and adopts a multi-source information fusion and intelligent path planning technology. And high-precision and non-intrusive nondestructive detection of the metal pipeline with the burial depth exceeding 5 meters is realized. Through comprehensive evaluation of ground obstacles and underground interference sources, the detection path layout is optimized, and the problems of signal interference, multi-path reflection and detection blind areas in the urban complex underground environment are effectively solved. The system can accurately reject non-target structure reflection signals, dynamically generate an obstacle avoidance compensation path, and improve the detection coverage rate and the signal integrity. And finally, three-dimensional space positioning and digital map coordinate output are realized, and the accuracy of pipeline positioning and the reliability of depth estimation are remarkably improved.
Owner:WUHAN SURVEYING GEOTECHN RES INST OF MCC

Dynamic stress test method and system for folding screen mobile phone mainboard

The invention belongs to the technical field of mobile phone mainboard testing, and particularly relates to a dynamic stress testing method and system for a folding screen mobile phone mainboard, and the method comprises the steps: constructing a testing parameter set and a stress loading model to simulate a real folding working condition; installing a mainboard to be tested and applying periodic bending stress; in the stress loading process, electrical and signal integrity and functional state parameters of the mainboard are monitored and collected in real time; stress-performance coupling analysis is carried out on the collected data, dynamic correlation between stress and performance is established, the performance state is evaluated, and fault early warning is carried out; and finally generating a test report. The system comprises a test control and modeling module, a stress loading execution module, an online monitoring module, a coupling analysis module and a report generation module, the actual bending process can be more accurately reproduced by constructing a stress loading model, the authenticity and effectiveness of the test are improved, time sequence alignment and key parameter extraction are achieved, and the test efficiency is improved. And the real-time association between the dynamic stress and the multi-dimensional performance parameters is established.
Owner:SHENZHEN HAO CHENG COMM TECH CO LTD

Method for testing signal quality of IO interface of memory module

The invention relates to the technical field of data storage, and discloses a method for testing the signal quality of an IO interface of a memory module, and the method comprises the steps: verifying the signal integrity of the I / O interface in the memory module based on an eye diagram analysis method; after the signal is verified to be complete, the morphological characteristics of the input eye pattern and the output eye pattern are quantitatively compared, whether morphological characteristic changes occur in the signal transmission process or not is judged, and the morphological characteristic changes at least comprise logic level flipping errors, time sequence recognition errors and signal quality degradation; if the morphological characteristics of the input eye pattern are consistent with the morphological characteristics of the output eye pattern, the test is successful; and if the morphological characteristics of the input eye pattern are inconsistent with the morphological characteristics of the output eye pattern, determining that the test fails. Visual and quantitative verification of signal integrity is realized through eye pattern analysis, multi-dimensional indexes such as voltage, time sequence and noise are covered, and the signal transmission quality is reflected more comprehensively compared with a single parameter test.
Owner:SHENZHEN JINGCUN TECH CO LTD

Partial discharge signal noise suppression method, system, equipment and medium

The invention discloses a partial discharge signal noise suppression method, system and device and a medium, and the method comprises the following steps: receiving an original partial discharge signal, calculating the kurtosis value of the original partial discharge signal, and constructing a kurtosis criterion; constructing a variational mode decomposition model, and optimizing parameters of the variational mode decomposition model by using a northern eagle algorithm; variational mode decomposition is performed on the original partial discharge signal based on the optimized parameters, the kurtosis value of each mode component is calculated, and an effective mode component and a noise mode component are divided according to the kurtosis criterion; reconstructing the effective modal component to obtain an intermediate signal; and performing signal enhancement on the intermediate signal by using a wavelet denoising method based on an improved threshold to obtain a denoised partial discharge signal. According to the method, the noise suppression precision, the algorithm stability, the operation efficiency and the signal integrity of partial discharge signal processing can be effectively improved.
Owner:ZHANGZHOU POWER SUPPLY COMPANY STATE GRID FUJIANELECTRIC POWER +1

Signal integrity simulation analysis method for digital radio frequency hybrid microsystem

The invention discloses a signal integrity simulation analysis method for a digital radio frequency hybrid microsystem, and belongs to the field of advanced packaging of integrated circuits. According to the method, a complete analysis process accompanied with product research and development is established, systematic work of qualitative simulation evaluation, rule design and quantitative analysis verification is sequentially carried out in various stages of project approval demonstration, scheme design, design verification and the like of product design, and process conditions, material characteristics and rationality and feasibility of system layout are rapidly evaluated; qualitative support is provided for agile design of the scheme; designing rules and optimization ranges of structures such as a radio frequency link, a digital link and a coupling shield are formulated according to process and material rules, and accurate initial input is provided for comprehensive design of a product; according to the layout wiring form, digital, radio frequency and coupling areas are formed through division, time domain analysis, frequency domain analysis and near field analysis are carried out in a targeted mode, quantitative reference is provided for judging design reasonability, and an effective basis is provided for optimizing design content.
Owner:58TH RES INST OF CETC

DDR5 dynamic ODT regulation and control method, device and equipment based on multi-working-condition perception and medium

The invention discloses a DDR5 dynamic ODT regulation and control method, device and equipment based on multi-working-condition perception and a medium, and relates to the field of computer memories, and the method comprises the steps: obtaining a power supply ripple value and a DRAM chip temperature value of a system; querying a preset ripple-temperature-ODT value corresponding table by taking the power supply ripple value and the DRAM chip temperature value as a joint index to obtain a corresponding target ODT value; and writing the target ODT value into an ODT control register of the DDR5 chip through a mode register setting command. Multi-working-condition sensing is achieved by synchronously monitoring power supply ripples and chip temperature, the optimal ODT value is directly obtained based on a joint index query preset optimization mapping table, and finally configuration is written through a standard MRS command. Comprehensive state monitoring, pre-stored expert knowledge and a standard hardware interface are combined, microsecond-level fast decision making and reliable regulation and control are achieved, on the premise that an existing DDR5 standard is completely compatible, signal integrity is effectively guaranteed, system power consumption is optimized, and the overall performance and energy efficiency of a memory subsystem are improved.
Owner:成都芯忆联信息技术有限公司

Desktop computer mainboard on-board BGA central processor DDR6 memory structure intelligent control system

The invention relates to the technical field of computer hardware, and particularly discloses an intelligent control system for a desktop computer mainboard on-board BGA central processing unit DDR6 memory structure, which comprises a hardware sensing layer, a behavior modeling layer, a collaborative decision-making layer and a dynamic execution layer, intelligent cooperative control of a processor and a memory subsystem from physical and electrical characteristics to logic access behaviors is realized by sensing a hardware state in real time, constructing a digital twin model, collaboratively optimizing a prefetching and scheduling strategy and executing feedback in a closed loop, so that the memory access efficiency is improved, the delay is reduced, and the system stability is enhanced. The system not only pays attention to an access mode of a software level, but also quantifies physical layer constraints such as signal integrity and power supply noise into computable model parameters, so that a subsequent optimization decision is established on the basis of digital twinning reflecting a real hardware state, and the problem that traditional control logic is disjointed from physical reality is solved; and a data foundation is laid for unification of high performance and high stability.
Owner:SHENZHEN ERYING TECH CO LTD

Ground plane segmentation method and device for hybrid PCB

The invention discloses a ground plane segmentation method and device for a hybrid PCB, and belongs to the field of PCB design, and the method comprises the steps: inputting the characteristic parameters of the hybrid PCB into a land division decision model, enabling the land division decision model to carry out the layer-by-layer judgment according to the characteristic parameters, and outputting a first land division strategy; constructing an electromagnetic simulation model based on the first land division strategy, executing predefined simulation analysis according to the electromagnetic simulation model, and optimizing the first land division strategy through a preset optimization rule base when a simulation analysis result does not meet a preset requirement to generate a second land division strategy; and based on the first land division strategy or the second land division strategy, automatically generating a segmentation line through PCB design software, and placing a connection bridge and a compensation element so as to complete the ground plane segmentation of the hybrid PCB. Therefore, by implementing the method, the targeted ground plane segmentation design can be performed according to the related parameters of the hybrid PCB, so as to ensure the signal integrity and electromagnetic compatibility of various hybrid PCBs.
Owner:RADIO & TELEVISION METROLOGY & TESTING CHENGDU CO LTD +3

Electric connector and electric connector combination

The invention provides an electric connector and an electric connector combination. The electric connector comprises an insulating seat body and a plurality of terminal rows. Each terminal row comprises a plurality of grounding terminals and a plurality of differential signal terminal pairs which are alternately arranged along a first direction, and the plurality of terminal rows are arranged at intervals along a second direction. Each grounding terminal is provided with a body part and three elastic contact parts. Each signal terminal of each differential signal terminal pair is provided with a body part and an elastic contact part. On the two adjacent terminal columns, the orthographic projection of the two elastic contact parts of each differential signal terminal pair in the second direction is located in the width coverage range of the elastic contact parts of the corresponding grounding terminals; and the orthographic projection of the elastic contact part, positioned in the middle, of each grounding terminal in the second direction is positioned in the width coverage range of the elastic contact part of the corresponding differential signal terminal pair. According to the electric connector, the signal integrity can be improved.
Owner:MOLEX INTERCONNECT SHANGHAI +1

Data acquisition method and system with reusable differential signal interface

The invention relates to the technical field of data acquisition, in particular to a data acquisition method and system with a reusable differential signal interface. The device comprises a bottom plate and a data acquisition card used for acquiring analog signals, uniform interfaces are adopted and comprise a plurality of differential signal pairs used for transmitting commands, a plurality of differential signal pairs used for transmitting data and a plurality of differential signal pairs used for transmitting clocks. According to the reusable differential signal interface disclosed by the invention, the signal integrity and reliability of long-distance transmission of signals on a bottom plate are improved through differential signals, a system can stably work in a severe electromagnetic environment, and the reusable interface can be in mixed plug-in connection with different data acquisition cards of voltage, current, strain, temperature and the like according to requirements. According to the method, step-by-step power-on is adopted, identity recognition and software configuration are only performed on a digital logic level after insertion, and simulation power supply is performed after recognition is passed, so that chain risks such as power supply impact, bus locking and even system downtime caused by insertion faults or incompatible modules are eliminated.
Owner:CHENGDU UNIV OF INFORMATION TECH

Anti-dazzle anti-interference display touch screen and terminal equipment

An anti-dazzle anti-interference display touch screen and terminal equipment, comprising a display screen, a sensing surface of the display screen is bonded with a touch module, and a part of the touch module is covered with an electromagnetic shielding layer to ensure the integrity of a display signal of the display touch screen and prevent external interference; the touch module comprises a functional piece and a cover plate which are bonded with each other, at least one side of the cover plate is provided with an anti-dazzle structure, and a rough structure of the anti-dazzle structure can convert direct light into diffuse reflection, so that dazzle of the display touch screen is reduced, visibility is improved, and durability is enhanced.
Owner:FUJIAN WIWO ELECTRONIC TECH CO LTD

Dynamic impedance matching method and system for radio frequency switch and attenuator

The invention relates to the technical field of communication, discloses a dynamic impedance matching method and system for a radio frequency switch and an attenuator, and aims to solve the technical problems that signal reflection is increased, insertion loss is increased and system performance is reduced due to the fact that a traditional fixed impedance matching network cannot adapt to port impedance change during state switching of the radio frequency switch and the attenuator. The method comprises the following steps: monitoring control signal changes of a radio frequency switch and an attenuator in real time, and generating a state identification code representing a current working state; and taking the identification code as an index, and retrieving a corresponding optimal tunable network control parameter from a pre-stored calibration parameter lookup table. By means of the scheme, rapid and accurate impedance matching can be achieved under all working state combinations, reflection loss and insertion loss are remarkably reduced, signal integrity and linearity are improved, and the overall performance and environmental adaptability of the system under broadband and multi-state application are improved.
Owner:SHENZHEN NEARZENITH CONPER TECH CO LTD

A high-speed link signal equalization method based on a three-dimensional memristor equalizer

ActiveCN120321074BLine balance variation compensationTransmitter/receiver shaping networksData setAlgorithm
The application discloses a high-speed link signal equalization method based on a three-dimensional memristor type equalizer, which comprises the following steps: obtaining a distorted signal and generating an ideal received signal, and then constructing a data set; training a recurrent neural network by using the data set to obtain a trained weight parameter; obtaining a conductance value matrix in the three-dimensional memristor type equalizer by mapping the weight parameter; deploying the conductance value to the three-dimensional memristor type equalizer according to the conductance value matrix; and finally inputting the distorted signal into the three-dimensional memristor type equalizer to obtain an optimized signal after compensation distortion. Compared with the traditional feedforward equalizer and decision feedback equalizer method, the application effectively reduces the time domain waveform distortion, improves the high-speed signal integrity, has wide applicability, can be used for the training and deployment application of the memristor type equalizer of various complex high-speed links, and deploys the above-mentioned conductance value to the three-dimensional memristor cross array, so as to improve the integrated density and reduce the area occupied by the equalizer.
Owner:ZHEJIANG UNIV

PCIe link state monitoring system and monitoring method thereof

PendingCN122086698AEnable non-invasive observationeffective positioningHardware monitoringReal time analysisPHY
The invention discloses a PCIe link state monitoring system and a monitoring method thereof. The PCIe link state monitoring system comprises a PCIe monitoring subsystem, a PCIe controller subsystem and a PHY (Physical Layer) module, wherein the PCIe controller subsystem and the PHY module are connected through a PIPE interface, and the PCIe monitoring subsystem is used for monitoring state information of a PCIe link; four levels of leaky bucket modules are integrated on the same layer of the PCIe monitoring subsystem, and the four levels of leaky bucket modules are used for dropping correctable error information in the state information of the PCIe link into leaky buckets, carrying out overflow counting to obtain leaky bucket overflow times, carrying out error pattern recognition according to the leaky bucket overflow times and preset different execution thresholds, and outputting the error pattern recognition result. Link recovery is carried out by adopting a progressive link recovery strategy; therefore, extra special equipment does not need to be introduced into the PCIe link, the observability of the PCIe link can be improved, and correctable errors caused by the signal integrity problem on the link can be analyzed and diagnosed in real time, so that a corresponding link recovery strategy is adopted.
Owner:XIAMEN UNIV

Connector fixing device and circuit board assembly

The invention relates to the technical field of connectors, in particular to a connector fixing device and a circuit board assembly, a connector is provided with a connecting terminal, the connecting terminal is used for being in crimping fit with a plug hole of a circuit board, and the connector fixing device comprises a support frame and a crimping structure; the supporting frame is arranged on the connector in a crossing mode and connected with the circuit board. The crimping structure is arranged on the support frame, and the crimping structure is located on one side, deviating from the circuit board, of the connector so as to crimp the connector on the circuit board at least from the crimping direction of the connecting terminal, so that the phenomena of floating or part falling and the like of the connector after crimping can be avoided to a certain extent, and the integrity and reliability of system signals are improved.
Owner:XFUSION DIGITAL TECH CO LTD

Co-packaged optical engine and networking

The utility model discloses a kind of co-encapsulation type light engine and networking.The co-encapsulation type light engine includes data processing bare core and the light chip stacked above the data processing bare core;The light chip is configured as the way of optical signal transceiver data;The data processing bare core is configured to process the data.The scheme provided by the utility model cancels silicon medium plate, adapter plate etc. intermediate substrate, further shorten transmission path, improve data transmission efficiency, in addition, this close coupling can also significantly reduce signal loss, improve high-speed signal integrity.
Owner:ZHEJIANG EAGLE SEMICON TECH CO LTD +1

Statistical channel analysis with feedback burst error

The application discloses a computing system configured to measure a step response of a channel in an electronic device, determine a feedback voltage added to the channel by a decision feedback equalizer in response to detecting inter-symbol interference in a received symbol, and predict signal integrity of the channel based at least in part on the step response of the channel and the feedback voltage. The computing system may utilize the predicted signal integrity to determine a probability that a feedback voltage added to the channel by the decision feedback equalizer is wrong, and determine a signal integrity of the channel based at least in part on the step response of the channel, the feedback voltage, and a probability that the feedback voltage added to the channel by the decision feedback equalizer is wrong.
Owner:SIMENS INDASTRI SOFTVEAR INK

A structure for efficiently controlling impedance continuity of a high-speed connector

The application relates to the field of PCB design, in particular to a structure for efficiently controlling the impedance continuity of a high-speed connector, which comprises a plurality of modular anti-pad areas and modular high-speed vias capable of extending horizontally or vertically; each modular high-speed via comprises two first high-speed vias and second high-speed vias arranged horizontally side by side, third high-speed vias and fourth high-speed vias arranged symmetrically above and below the first high-speed vias and the second high-speed vias, fifth high-speed vias and sixth high-speed vias located on the two sides of the first high-speed vias and the second high-speed vias and with the center of the circle located on the symmetric axis of the first high-speed vias and the third high-speed vias, and the modular high-speed vias are in a structure symmetric above and below and left and right. Compared with the prior art, the application has the advantages that the design of the application is optimized on the PCB, the shape is uniformly designed, signal integrity simulation is confirmed, and the application is added to a packaging library, so that the optimization of the connector pad can be realized only by synchronously packaging the library.
Owner:SHANGHAI EMBEDWAY INFORMATION TECH

Electromagnetic compatibility design method for low-orbit satellite system

The invention discloses an electromagnetic compatibility design method for a low-orbit satellite system, and aims to solve the problems that the traditional design focuses on a single machine, measures are isolated, and complex electromagnetic interference of the low-orbit satellite system cannot be handled. The method comprises the following steps: S1, analyzing a system-level electromagnetic environment and requirements, determining parameters, and identifying an interference source and a coupling path; s2, providing a layered and graded electromagnetic compatibility framework including platform and load isolation, power supply interference suppression, satellite-borne cable network optimization and grounding system construction; s3, performing frequency resource and signal integrity management, planning a frequency spectrum, and optimizing a clock and a digital circuit; s4, providing a software anti-interference and fault-tolerant mechanism, and realizing data verification, instruction voting and state monitoring; s5, performing on-orbit electromagnetic compatibility prediction; and S6, carrying out ground test verification. According to the method, a full-link design system is formed, interference risks are avoided in advance, and the operation stability and data reliability of the satellite in a complex electromagnetic environment are improved.
Owner:SHANGHAI LANJIAN HONGQING TECH CO LTD

Implementation method and device of half-size NAND, electronic equipment and storage medium

The invention provides a half-size NAND implementation method and device, electronic equipment and a storage medium, and relates to the technical field of flash memory design, and the method comprises the following steps: obtaining a pin layout of standard SDP NAND particles; the standard SDP NAND particle comprises a first data channel and a second data channel; wherein the second data channel is not used; performing optimization processing on the pin layout to obtain an optimized pin layout; wherein the optimization processing comprises the step of rearranging the positions of the key signal pins; carrying out packaging size reduction processing based on the optimized pin layout to obtain half-size NAND particles; wherein the package size reduction processing comprises the step of deleting unused pins; half-sized NAND particles are laid out on a PCB to achieve signal integrity and save space. In the mode, by optimizing the pin layout and removing the redundant channel structure, packaging miniaturization, capacity multiplication, signal quality improvement and wiring difficulty reduction are realized.
Owner:SHENZHEN CITY TECHWIN SEMICONDUCTOR COMPANY LIMITED

High-isolation low-loss filtering structure and method for PCB strip line

The invention discloses a high-isolation low-loss filtering structure and method for a PCB strip line. According to the high-isolation low-loss filtering structure provided by the invention, the main transmission strip line, the filtering auxiliary strip line with the spur line structure and the grounding layer with the hollowed-out area are integrated in the PCB, so that external discrete filter elements and welding procedures and shielding separation cavities required by the external discrete filter elements are effectively omitted, and therefore, the size of a module is remarkably reduced; weight and complexity. Meanwhile, due to the integrated design, impedance discontinuity and signal reflection caused by the fact that signals are converted between the inner layer and the surface layer of the PCB through the via holes are avoided, and signal integrity is guaranteed. And finally, on the premise of not introducing additional elements, high-performance filtering is realized, and an effective solution is provided for miniaturization and high performance of the radio frequency front-end module.
Owner:SICHUAN JIUZHOU ELECTRIC GROUP CO LTD

High-speed printed circuit board differential pair transmission path equal-length matching optimization method

The invention discloses an equal-length matching optimization method for differential pair transmission paths of a high-speed printed circuit board, and belongs to the technical field of signal integrity modeling and simulation. Comprising the following steps: constructing a multi-conductor transmission line model containing a reference conductor, extracting a parameter matrix per unit length, judging the uniformity and symmetry of a structure, and introducing a local modal substrate and a continuous modal coupling term which change along with space for describing modal conversion caused by gradual change of the structure, the propagation delay inequality of the two signal paths is calculated, a phase calibration operator is constructed, modal conversion and the delay mismatch effect are brought into a unified propagation equation to be solved, the phase calibration operator is applied at a recoupling reference plane to carry out alignment processing on voltage and current, and finally equivalent differential mode impedance is obtained through calculation. According to the method, integrated modeling is carried out by integrating the joint effect of mode conversion and time delay mismatch, and the impedance simulation precision of the difference pair snake-shaped compensation structure recoupling region is remarkably improved.
Owner:UNIV OF JINAN +1

A method, system, and medium for crosstalk suppression and timing optimization of a high frequency circuit

PendingCN122293234AAchieve multi-dimensional quantitative representationRealize dynamic collaborationSensor arrayFrequency spectrum
This invention provides a method, system, and medium for crosstalk suppression and timing optimization in high-frequency circuits. A sensor array is deployed along the critical signal path to simultaneously acquire high-frequency crosstalk spectrum and timing eye diagram parameters, generating a crosstalk intensity matrix (CIM) and a timing margin heatmap (TMM) to achieve multi-dimensional quantitative characterization of signal integrity. Based on the CIM, the main interference source is located, and the impedance of the affected line is dynamically adjusted and a reverse compensation current is injected to cancel high-frequency crosstalk at its source. The margin attenuation is predicted using a pre-trained model, and the clock phase of the affected line is fine-tuned to compensate for timing deviations. The optimized efficiency index per unit energy consumption after compensation is calculated, triggering a dynamic update or re-compensation mechanism for the strategy library. This invention achieves dynamic synergy between crosstalk suppression and timing optimization based on a closed-loop architecture composed of monitoring data, neural network prediction, dual-loop compensation, energy efficiency verification, and strategy learning.
Owner:YUANXIN SEMICON (SHANGHAI) CO LTD

Signal integrity simulation method and system, computer equipment and storage medium

The invention provides a signal integrity simulation method and system, computer equipment and a storage medium. The method comprises the following steps: acquiring execution scripts supported by a simulation tool and a first mapping relationship between each execution script and each simulation process; obtaining text information of each execution script, inputting the text information into a preset language model, and obtaining a first intention text group having a second mapping relationship with the execution script and a second intention text group having a third mapping relationship with a calling sequence of the execution script; an input first natural language instruction is analyzed through the language model, a first intention instruction is obtained, and the first intention instruction comprises a target first intention text and a target second intention text; generating a calling code of the execution script according to the first intention instruction; and controlling the simulation tool to execute a simulation process according to the calling code to obtain a simulation result. According to the scheme, signal integrity simulation can be automatically carried out according to user requirements, and the operation threshold is lower.
Owner:JULIN TECH (SHANGHAI) CO LTD