995 results about "Signal integrity" patented technology

The invention relates to a modeling and optimizing method for inter-layer signal crosstalk of a PCB (Printed Circuit Board). Frequency response data of all dielectric layers of the PCB under different temperature and humidity conditions are collected, and a mapping model with the temperature gradient and the humidity diffusion gradient as input and the dielectric constant as output is established. And calculating the dynamic distribution of mutual capacitance and mutual inductance under the environment change by combining the spatial layout parameters of the differential signal pair, and constructing a crosstalk sensitivity evaluation model with coupled frequency, environment and layout. And high-risk areas with crosstalk sensitivity caused by environment change are identified, and the crosstalk change rate of each area is quantified. For a sensitive area, a temperature and humidity compensation medium structure is introduced to stabilize local dielectric characteristics and reduce the influence of the environment on crosstalk. And according to the compensated medium distribution, adjusting a differential signal wiring path and impedance matching by adopting an optimization method with the aim of minimizing the crosstalk change rate, and generating a wiring layout with environmental robustness. According to the invention, the signal integrity and the transmission reliability of the multi-layer PCB in a temperature and humidity changing environment can be effectively improved.

The invention relates to the technical field of brain-computer interfaces, in particular to a method, a device and equipment for detecting the cognitive state of attention glasses in real time. The method comprises the following steps: acquiring multi-channel electroencephalogram data of attention glasses, acquiring multi-dimensional features corresponding to the multi-channel electroencephalogram data, and generating a detection sequence; performing time sequence analysis on the detection sequence, extracting change characteristics to construct a cognitive sequence, and generating state description according to the cognitive sequence; performing trend analysis on the state description, performing feature extraction on an analysis result corresponding to the trend analysis, constructing a conversion rule according to the extracted features, and generating a prediction sequence according to the conversion rule; performing threshold division on the prediction sequence, marking state intervals, constructing a criterion sequence, and generating an evaluation result according to the criterion sequence for performing signal detection to obtain detection information; and performing data conversion on the detection information, constructing a display sequence to mark a state type, and generating cognitive state information. And data continuity and signal integrity in a feature extraction process are realized.

The invention relates to the technical field of laser processing, and discloses a laser processing device and method suitable for TGV forming, and the method comprises the steps: S1, a glass substrate is scanned in a confocal manner, a three-dimensional topological graph is obtained, and the three-dimensional topological graph comprises the three-dimensional coordinate, the thickness gradient and the positioning mark of the glass substrate; s2, based on the three-dimensional topological graph, a through hole body is formed through ultraviolet femtosecond laser etching, and intermediate infrared laser is synchronously and dynamically controlled to etch the side wall of the through hole body to generate a taper through hole with a preset taper angle; and S3, the incident angle of the ultraviolet femtosecond laser is adjusted on the side wall of the taper through hole according to the three-dimensional topological graph, and a plurality of heat dissipation grooves are etched through the ultraviolet femtosecond laser. According to the laser processing device and method suitable for TGV forming, signal integrity optimization and active heat dissipation functions are achieved in the same through hole, the application range of the TGV is widened, and the stability of the TGV during use is improved.

The invention relates to the technical field of submarine engineering and information processing, in particular to a submarine cable positioning method and system, and the method comprises the steps: synchronously collecting magnetic field, structured light and underwater acoustic signal data, and fusing inertial navigation information to construct a unified space-time reference system; precise registration of heterogeneous data is realized by adopting sliding time window screening, multi-modal noise reduction and rigid body transformation; constructing a graph structure model for expressing cable space-signal features based on the fused data, and reasoning cable path topology by using a graph convolutional network; reconstructing a cable center line through three-dimensional visualization, embedding the cable center line into submarine topography, and realizing risk area dynamic clustering by combining signal integrity score and burial depth estimation; historical time sequence data are fused, a long short-term memory network is adopted to predict cable drift, detectable attenuation and burial depth change trends, risk levels are divided based on prediction results, and spatial distribution early warning and disposal suggestions are output. According to the invention, the cable positioning precision and the risk assessment intelligent level in a complex seabed environment are improved.

The invention discloses an unmanned aerial vehicle soft landing control method based on track prediction and multi-source cooperative decoy, and the method comprises the steps: introducing a communication protocol recognition mechanism in a blocking process of an instruction link of an unmanned aerial vehicle, and achieving the conversion from extensive broadband suppression to protocol precise interference; the problems that in the prior art, power consumption is high, interference on legal communication is large, and the frequency hopping unmanned aerial vehicle resisting effect is insufficient can be effectively solved. In the scheme, signal integrity is guaranteed through monitoring and preprocessing, an unmanned aerial vehicle link protocol is identified through feature extraction and protocol library matching, and then a targeted interference template is generated, so that the interference effect can accurately fall on key positions such as a leader sequence, a CRC field, a subcarrier or a control frame and the like; therefore, synchronization, verification or data transmission can be destroyed under the condition of low power, and accidental damage of broadband noise to services such as co-frequency Wi-Fi and Bluetooth is avoided.

The invention relates to the field of chip testing, in particular to a chip signal integrity test analysis method, device and equipment and a storage medium. The method comprises the following steps: extracting a chip performance index based on a chip design requirement document; performing saturation frequency excitation setting based on the chip performance index to generate an excitation test signal; performing a multi-port signal excitation test and parallel signal sampling based on the excitation test signal to generate a high signal-to-noise ratio response data set; obtaining a chip layout design file; performing chip communication link analysis on the chip layout design file, and constructing communication line layout data; performing signal mapping and waveform quality evaluation on the communication line layout data based on the high signal-to-noise ratio response data set to obtain a node signal distortion rate; and performing signal integrity quantization and theoretical signal integrity score comparison based on the node signal distortion rate, and marking a fault node. According to the invention, the chip testing efficiency is improved, and the signal abnormal part of the chip is accurately and efficiently detected.

The invention discloses a logic board comprehensive performance testing device and testing method, and relates to the technical field of electronic equipment testing. A time sequence signal, a power consumption curve and infrared temperature data are synchronously acquired through a logic board interface, a time-space aligned fusion data set is generated by using a dynamic time warping algorithm, a power consumption coupling analysis model is input, a dynamic incidence matrix of a signal integrity parameter and power consumption fluctuation is acquired, and key coupling characteristics are extracted through singular value decomposition. And constructing an adaptive neighborhood density clustering model according to the correlation mode parameters and the temperature gradient distribution, generating an abnormal region probability graph, and marking electrothermal coupling abnormal coordinates and confidence. And inputting the fusion data, the correlation parameters and the abnormal probability graph into a graph neural network, taking a time sequence signal spectrum entropy, a local temperature mean value and a power consumption fluctuation variance as node features, taking an electrothermal coupling coefficient as an edge weight, iteratively updating a node state through a graph attention mechanism, and outputting a defect type and a three-dimensional coordinate. And the defect detection accuracy is effectively improved.

The invention discloses a co-packaging type optical engine module and networking. The co-packaged optical engine module comprises a photonic integrated chip and a processor bare core, and the photonic integrated chip is stacked above the processor bare core and electrically connected with the processor bare core; the photonic integrated chip is configured to transmit and receive data in an optical signal mode, and an optical signal transmitting and receiving end of the photonic integrated chip is located on one side far away from the processor bare core; the processor die is configured to process the data. According to the scheme provided by the invention, intermediate substrates such as a silicon dielectric plate and an adapter plate are canceled, the transmission path is further shortened, the data transmission efficiency is improved, in addition, the signal loss can be remarkably reduced by the tight coupling, and the high-speed signal integrity is improved.

The invention relates to a back drilling method for reducing circuit board via hole stubs, which comprises the following steps: S1, blind hole pre-processing: performing laser pre-processing at the tail end of a target via hole stub to form a positioning blind hole; s2, back drilling, wherein a drill bit with an impedance monitoring module is adopted to conduct tracking drilling on the positioning blind hole; s3, monitoring a dynamic resistance value, and collecting an electrical impedance value of the impedance monitoring module in real time; and S4, tool retracting is conducted, and when it is monitored that the electrical impedance value reaches a preset value, drilling is stopped immediately, and the drill bit is retracted. According to the method, the laser preprocessing technology and the impedance feedback technology are combined, dependence and uncertainty on empirical judgment are reduced, the production process is simplified, the machining cost is reduced, and accurate control over the back drilling via hole stub can be achieved. The length of the via hole stub can be effectively reduced, reflection, scattering and delay in high-speed signal transmission are reduced, signal integrity is improved, and the method is particularly suitable for design of high-frequency and high-density interconnected circuit boards.

The invention discloses a PCBA (Printed Circuit Board Assembly) processing component layout optimization method and system, and relates to the technical field of electronic design automation. Data stream information of each functional module of a PCBA is collected, data stream characteristics are analyzed, and key signal paths and interaction relationships are determined; the method comprises the following steps of: dividing priorities for different data streams according to functional requirements and signal importance of a PCBA (Printed Circuit Board Assembly), and determining a core signal; by optimizing component layout, reducing roundabout and intersection of signal paths, reducing signal transmission loss and interference, reasonably dividing functional areas and compactly arranging associated components according to data stream directions and core signals, it is ensured that the signal transmission paths are clear and efficient, meanwhile, the transmission quality of high-priority signals is preferentially guaranteed, and the transmission efficiency is improved. By adopting a transmission line with strong anti-interference capability, adding a signal buffer and filter circuit and other measures, the signal integrity is obviously improved, and the signal is kept stable and reliable in the transmission process, so that the performance of the whole PCBA system is improved.

The invention belongs to the technical field of server detection, and discloses a server PCB automatic detection system based on operation data acquisition and analysis. The system is composed of an operation data distributed acquisition module, a preprocessing and synchronous time sequence correction module, a signal integrity real-time detection module, a thermal field dynamic distribution analysis module, a time sequence drift intelligent analysis module, a multi-dimensional joint feature extraction module and an abnormal mode adaptive identification module. A fault trend depth prediction module; and a self-learning feedback and online optimization module. Acquisition units carrying FPGA hardware are arranged at key nodes of a PCB of a server, distributed acquisition of current, voltage, temperature and other multi-source electrical data is achieved by means of the high-speed parallel acquisition characteristic of the acquisition units, after asynchronism and noise interference of the acquired data are eliminated through a preprocessing and synchronous time sequence correction module, all functional modules work cooperatively, and the multi-source electrical data are acquired. A whole-process online dynamic detection system from data acquisition to anomaly analysis is constructed, and anomaly can be quickly captured in a fault germination stage.

The invention discloses a memory signal integrity enhancing system based on multi-dimensional parameter self-adaption, and belongs to the technical field of signal transmission. The system comprises a multi-dimensional signal acquisition module, a multi-dimensional parameter analysis module, a self-adaptive adjustment module, a memory signal optimization module and a feedback monitoring module, the multi-dimensional signal acquisition module is combined with multi-dimensional parameter analysis, signals of a data bus, an address bus and a control bus are synchronously acquired, a dynamic adjustment strategy is generated according to a model, and the self-adaptive adjustment module and the memory signal optimization module are optimized according to the dynamic adjustment strategy. Different optimization means are adopted for different parameter types, a customized optimization system with one parameter and one scheme is formed, it is ensured that the optimized target signal is optimal in amplitude stability, time sequence accuracy, anti-noise capacity and impedance matching degree, the feedback monitoring module is combined with the multi-dimensional parameter analysis module, and the multi-dimensional parameter analysis module is combined with the feedback monitoring module. And through full-dimension index monitoring and dynamic calibration, the continuous adaptability of the system to the running state of the memory and the long-term stability of signal integrity are guaranteed.

The invention discloses a U.2 interface-based server intelligent integrated hierarchical storage system and method, relates to the technical field of computer server storage, and is used for solving the problem of optimization of multi-type SSD data access efficiency and storage resource utilization rate. Firstly, a multi-protocol parallel channel is established by redefining U.2 interface reserved pins, signal integrity parameters are monitored in real time and fused with equipment I / O access features, and an I / O feature sequence of physical layer state information is generated; then, based on a time sequence convolutional neural network, extracting access mode multi-scale features, calculating a data block access heat probability, mapping and determining a target storage hierarchy, and generating a scheduling instruction containing a source physical address, the target hierarchy and a migration priority; the migration execution module realizes zero-copy migration of the data block between the shared DRAM pool and the SSD according to the instruction; and the resource coordination module monitors system load in real time, dynamically adjusts migration concurrency and an I / O sampling strategy, and realizes self-adaptive optimization of storage performance and resource utilization.

The invention provides a preparation method of an HDMI (High Definition Multimedia Interface) high-performance common-mode suppressor made of a nanocrystalline material, relates to the technical field of electronic component preparation, and aims to meet the harsh requirement of HDMI high-frequency high-speed signals on common-mode noise suppression, the method comprises the following steps: constructing a multi-layer heterogeneous magnetic film with a gradient interface on a microstructured substrate by utilizing multi-target magnetron sputtering; a selective energy field assisted annealing technology is adopted to realize precise nanocrystallization and magnetic anisotropy regulation and control of the magnetic film; and a high-precision three-dimensional coil structure is integrated by combining a micromachining process. The prepared common-mode suppressor is small in size and high in integration level, shows excellent common-mode suppression efficiency, wide working bandwidth and excellent signal integrity in a high-frequency band, has high reliability, and is suitable for a new generation of HDMI (High-Definition Multimedia Interface).

A probe card for a circuit probe test system and methods of fabrication thereof. The probe card includes a substrate portion, and a probe head including a guide plate located below the substrate portion and having a plurality of openings through the guide plate, and a conductive trace on the guide plate that extends between a pair of the openings. A plurality of probe pins extend through the openings through the guide plate, where a pair of probe pins are electrically connected by the conductive trace to form a loopback signal path. Accordingly, the loopback signals may be routed through the conductive trace located on and / or within the guide plate rather than through the substrate portion of the probe card. This may significantly reduce the total length of the loopback signal path, which may thereby improve the signal integrity (SI) during loopback testing of a device-under-test.

The invention provides an electrolytic copper foil which is at least provided with a low-roughness surface, copper nodules on the low-roughness surface are rod-shaped protrusions and / or granular protrusions, the distance between every two adjacent protrusions ranges from 10 nm to 650 nm, the height of the copper nodules of the rod-shaped protrusions ranges from 300 nm to 800 nm, and the height of the copper nodules of the granular protrusions ranges from 80 nm to 250 nm. And the number of the rod-shaped bulge copper nodules and / or the granular bulges is 50-150 in every 25 mu m < 2 > of the area of the low-roughness surface. The invention further provides a preparation method and application of the electrolytic copper foil. The electrolytic copper foil provided by the invention has a low-roughness surface, so that the signal integrity of the copper foil substrate is improved, the problem of large signal transmission loss in the prior art is solved, the peeling strength between the copper foil and the substrate is improved, and the defect of insufficient peeling strength in the prior art is overcome.

The invention provides an integrated circuit packaging system with an isolation structure. The system comprises an isolation barrier building assembly which divides a function module and a signal path into a plurality of isolation areas; the electrical performance test assembly is responsible for applying an electrical performance test signal of the integrated circuit at the input end of the integrated circuit, collecting an output signal of the integrated circuit at the output end, and analyzing the electrical performance test signal and the output signal to obtain a quality parameter of the electrical performance test signal; and the signal path adjustment component is responsible for providing adjustment suggestions for the signal path of the current integrated circuit according to the analysis result of the quality parameters. According to the invention, electrical isolation and physical protection are ensured; the signal quality and the system performance under the isolation structure are evaluated through analysis of the test signal and the output signal; providing an optimization suggestion according to a test result, and adjusting a signal path and an isolation barrier design; and the integrated circuit packaging system with the isolation structure is ensured to reach the optimal level in the aspects of electrical performance, signal integrity and reliability.

The invention relates to a performance simulation optimization method and system for a high-speed connector, and the method comprises the following steps: carrying out the grid processing of a physical structure of the high-speed connector, and obtaining a three-dimensional structure discrete grid model; based on the three-dimensional structure discrete grid model and a time domain finite element, electromagnetic field distribution of the high-speed connector is solved, and a multi-order electromagnetic field distribution matrix is obtained; based on the multi-order electromagnetic field distribution matrix, performing spectral analysis on the output signal of the high-speed connector to obtain a performance score of the connector and a performance analysis report of the connector; when the performance score is lower than a preset performance threshold value, analyzing a key performance influence factor set of the high-speed connector based on a performance analysis report; and the high-speed connector is simulated and optimized based on the key performance influence factor set, so that the performance score of the high-speed connector is higher than a preset performance threshold, and the problem that the electromagnetic property of the high-speed connector and the influence of the electromagnetic property on the signal integrity are difficult to accurately predict by a traditional method is solved.

A photoelectric packaging structure disclosed by the present invention comprises a packaging substrate, an optical chip, an electric chip, a lens and a micro connector, the packaging substrate is provided with a first upper surface, the first upper surface is provided with a groove, the optical chip is installed in the groove, the optical chip is provided with a second upper surface, the second upper surface is flush with the first upper surface, and the optical chip is installed in the groove. The electric chip is electrically connected with the second upper surface and the first upper surface at the same time; the lens is arranged on the packaging substrate, is positioned on one side of the optical chip and is optically coupled with the optical chip; the micro connector is installed on the packaging substrate, the micro connector is connected with an optical fiber, and the optical chip is optically coupled with the optical fiber through the lens and the micro connector. According to the photoelectric packaging structure, the signal transmission path is shortened, the possibility of impedance mismatching and signal crosstalk is reduced, the high-frequency performance and signal integrity of packaging are improved, efficient optical coupling of the optical chip and the optical fiber is achieved, the stability and efficiency of optical signal transmission are improved, and the cost is reduced. And the aspects of compactness, connection efficiency, optical coupling performance and the like are remarkably improved.

Plug connectors for use with high speed signals. The connector includes an insulative housing having a base portion and a tongue portion extending from the base portion, and conductive terminals held by the housing. Each conductive terminal has a mating portion held on a side of the tongue portion, a tail portion extending out of the housing, and an intermediate portion held in the base portion. The conductive terminals comprise signal terminals and ground terminals. A shielding member is disposed in the housing and includes features configured to provide shielding to signal terminals and electrically connect ground terminals. The shielding member also includes features configured to improve impedance consistency along conduction paths. Such a configuration meets signal integrity requirements in connectors designed for higher frequencies, while conforming to a standard that constrains mating and mounting interfaces.

The invention relates to the technical field of circuit board processing, and discloses a circuit board back drilling stub control method, device and equipment and a medium, and the circuit board back drilling stub control method comprises the steps: carrying out the board thickness measurement of a circuit board, obtaining the original board thickness data, carrying out the difference analysis, and carrying out the piling and measurement processing according to the analysis result; obtaining a plate thickness data set corresponding to each pile; measuring and analyzing the target back drilling hole position to obtain grouped plate thickness data, calculating the influence degree of the plate thickness on the length of the back drilling stub, comparing the influence degree with a preset threshold value, and judging a back drilling depth adjusting scheme; and according to a judgment result, back drilling processing depth parameters of the whole or the partitions are calculated, and differentiated depth optimization control is achieved. According to the method, the stub range can be effectively reduced in multi-batch and high-layer PCB machining, the back drilling depth control precision is improved, and it is ensured that the stub length is stable and meets the high-specification signal integrity requirement.

The invention relates to the technical field of high-speed rail fault detection, and discloses an intelligent fault detection system for a high-speed rail. A data acquisition module of the system acquires a heterogeneous operation log data set, including vibration, temperature, current time sequence data and control signal data, of a high-speed rail core component in a preset monitoring period; the stability evaluation module performs multi-dimensional stability analysis on the data set to generate vibration, temperature and current stability indexes and signal integrity indexes; the detection configuration optimization module takes a multi-dimensional index as an index, performs self-adaptive search in a pre-constructed high-dimensional fault detection configuration space, and determines a dynamic detection step length; and the fault detection execution module drives the multi-sensor array to execute periodic detection based on the dynamic detection step length, generates a real-time monitoring data stream, and extracts abnormal features through a fault mode recognition engine. The system can comprehensively capture the operation state of the component, adaptively adjust the detection configuration, improve the fault detection accuracy and real-time performance, and guarantee the operation safety of the high-speed rail.

The invention discloses an unmanned aerial vehicle instruction link blocking interference method and device based on communication protocol identification, which can effectively solve the problems of high power consumption, large interference on legal communication and insufficient anti-frequency hopping unmanned aerial vehicle effect in the prior art by introducing a communication protocol identification mechanism in the unmanned aerial vehicle instruction link blocking process. Firstly, signal integrity is guaranteed through monitoring and preprocessing, then an unmanned aerial vehicle link protocol is identified through feature extraction and protocol library matching, and then a targeted interference template is generated, so that the interference effect can accurately fall on key positions such as a leader sequence, a CRC field, a subcarrier or a control frame and the like; and synchronization, verification or data transmission can be destroyed under a low-power condition, so that accidental damage of broadband noise to same-frequency Wi-Fi and Bluetooth services is avoided. Meanwhile, through a frequency hopping prediction model and a scheduling mechanism, the interference signal can follow the frequency hopping switching of the unmanned aerial vehicle in real time.

Provided is a semiconductor package having improved signal integrity (SI) and a chip stack structure of a plurality of semiconductor chips. The semiconductor package includes a package substrate, a chip stack structure on the package substrate and including at least two semiconductor chips, and an external connection terminal on a lower surface of the package substrate. A first semiconductor chip arranged uppermost in the chip stack structure is connected to a first bonding pad of the package substrate through a first wire. A second semiconductor chip arranged under the first semiconductor chip in the chip stack structure is connected to a second bonding pad of the package substrate through a second wire. When the first bonding pad is farther from the external connection terminal than the second bonding pad, the external connection terminal is connected to the first bonding pad through a wiring line of the package substrate.

A terminal module includes a differential signal terminal pair, two ground terminals and an insulative bracket. Each ground terminal has a plate surface. The insulative bracket is integrally molded to locally clad the differential signal terminal pair and the two ground terminals. The insulative bracket has a surface which corresponds to the plate surfaces of the two ground terminals, the surface is provided with two depressed segments. At least a part of a position of each depressed segment corresponds to the plate surface of the corresponding ground terminal, each depressed segment is an elongated structure and a length direction of each depressed segment extends along a length direction of the corresponding ground terminal. As such, good signal integrity efficacy can be maintained when a signal is transmitted by the two signal terminals, so that crosstalk between the two adjacent differential signal terminal pairs can be lowered.

The invention discloses a 3D packaging structure and a manufacturing method thereof, and the method employs a glass wafer as a first carrier plate, and solves the problems of reliability and signal interference caused by the mismatching of thermal expansion coefficients of an organic material adapter plate and a Si-based silicon bridge chip. In S1, a blind hole is etched by taking a glass wafer as a base material, and Cu is metallized and filled, and the thermal expansion coefficient of glass is similar to that of a silicon bridge, so that the risk of thermal stress deformation is reduced. And S2, through groove etching, temporary carrier plate bonding and thinning, a through groove hole is formed, and the rigid structure of the glass carrier plate maintains the stability of the packaging structure during high-density integration. And S3, the silicon bridge Die is embedded into the through groove hole, the low thermal expansion characteristic of the glass is well matched with the silicon bridge, the interface stress is reduced, the dielectric property of the glass support plate is excellent, the signal dielectric loss is reduced, and the signal integrity is improved by matching with the silicon bridge Die. And S4, after the functional chip is mounted on the adapter plate, the glass-based adapter plate ensures reliable connection, signal attenuation distortion is inhibited, and a reliable packaging scheme is provided for high-density integration.

The invention discloses a preparation method of a photoelectric co-packaging CPO glass substrate and the CPO glass substrate. The method comprises the following steps: providing a glass substrate with two preset photon integration (PIC) areas and an electronic integration (EIC) area; for each glass substrate, manufacturing a TGV through hole and a blind groove in a PIC area and an EIC area; the two glass substrates are attached face to face to form a glass substrate stacking body, and the butt joint blind grooves form micro-channels for heat dissipation medium flowing; cutting the glass substrate stack to obtain a first part corresponding to the PIC region and a second part corresponding to the EIC region; functionalizing the TGV through holes of the two parts to obtain a first module and a second module; and integrating the two modules on a common glass substrate to form the CPO glass substrate. According to the method, low-loss optical coupling and high-density electrical interconnection are realized in the same layout, crosstalk and reflection are reduced, and signal integrity and bandwidth are improved; and meanwhile, the heat management efficiency and reliability are optimized, and the requirements of EIC heat dissipation and PIC temperature control are both considered.

The invention provides a plug shielding contact, a bent male connector and a connector assembly. The plug shielding contact comprises a contact part, a plugging end common ground part and a plug shielding contact, insertion cavities are arranged on the insertion end common ground piece; the plug shielding contact is provided with a shielding cavity along the plugging direction; the contact part comprises an injection molding part and a shielding sheet assembly. The shielding sheet assembly comprises a first shielding sheet and a second shielding sheet which are oppositely arranged on the two sides of the injection molding part, and a differential signal pair used for differential signal transmission is arranged in the injection molding part; the head end of the injection molding part is provided with a connecting plug capable of extending into the shielding cavity; according to the scheme, the structure is improved and optimized, so that the signal integrity in the connector transmission process is improved, and the signal transmission of a hardware link can be effectively ensured.

The invention discloses a tactile sensor based on TSV switching, and belongs to the technical field of tactile sensors, the tactile sensor comprises three main body parts of an MEMS device, a TSV device and an ASIC device, and the tactile sensor is realized through an MEMS-ASIC wafer level integration method, the electrical intercommunication between the MEMS and the ASIC is realized through TSV switching, the signal integrity is enhanced, the electromagnetic interference is reduced, and the tactile sensor can be applied to the field of tactile sensors. And the reliability of the MEMS tactile sensor is improved. Transfer of part of the lead and the Pad is achieved through TSV switching, signal output and reading of the MEMS tactile sensor are facilitated, meanwhile, layout design is simplified, and process difficulty is lowered.

A stacked I / O connector for use with a high speed, high density transceiver that generates a large amount of heat. The connector may be formed with a web-like housing into which leadframe assemblies are inserted. The web-like housing may have openings in the front, back, top and / or sides, enabling airflow through the connector with little resistance. Sidewall openings may open into a channel between the housing and a wall of cage, enabling air flowing to cool transceivers inserted into the cage to pass through the connector assembly with low resistance and high cooling efficiency. A cage for the connector may have openings selectively positioned such that air flowing through the cage to cool transceivers mated to the I / O connector may pass through the connector with low resistance, enhancing cooling efficiency. Such a connector may be used with OSFP transceivers to meet signal integrity and thermal requirements at 112 GBps and beyond.