756 results about "Signal integrity" patented technology

The invention discloses an unmanned aerial vehicle soft landing control method based on track prediction and multi-source cooperative decoy, and the method comprises the steps: introducing a communication protocol recognition mechanism in a blocking process of an instruction link of an unmanned aerial vehicle, and achieving the conversion from extensive broadband suppression to protocol precise interference; the problems that in the prior art, power consumption is high, interference on legal communication is large, and the frequency hopping unmanned aerial vehicle resisting effect is insufficient can be effectively solved. In the scheme, signal integrity is guaranteed through monitoring and preprocessing, an unmanned aerial vehicle link protocol is identified through feature extraction and protocol library matching, and then a targeted interference template is generated, so that the interference effect can accurately fall on key positions such as a leader sequence, a CRC field, a subcarrier or a control frame and the like; therefore, synchronization, verification or data transmission can be destroyed under the condition of low power, and accidental damage of broadband noise to services such as co-frequency Wi-Fi and Bluetooth is avoided.

The invention relates to the field of chip testing, in particular to a chip signal integrity test analysis method, device and equipment and a storage medium. The method comprises the following steps: extracting a chip performance index based on a chip design requirement document; performing saturation frequency excitation setting based on the chip performance index to generate an excitation test signal; performing a multi-port signal excitation test and parallel signal sampling based on the excitation test signal to generate a high signal-to-noise ratio response data set; obtaining a chip layout design file; performing chip communication link analysis on the chip layout design file, and constructing communication line layout data; performing signal mapping and waveform quality evaluation on the communication line layout data based on the high signal-to-noise ratio response data set to obtain a node signal distortion rate; and performing signal integrity quantization and theoretical signal integrity score comparison based on the node signal distortion rate, and marking a fault node. According to the invention, the chip testing efficiency is improved, and the signal abnormal part of the chip is accurately and efficiently detected.

The invention discloses a memory signal integrity enhancing system based on multi-dimensional parameter self-adaption, and belongs to the technical field of signal transmission. The system comprises a multi-dimensional signal acquisition module, a multi-dimensional parameter analysis module, a self-adaptive adjustment module, a memory signal optimization module and a feedback monitoring module, the multi-dimensional signal acquisition module is combined with multi-dimensional parameter analysis, signals of a data bus, an address bus and a control bus are synchronously acquired, a dynamic adjustment strategy is generated according to a model, and the self-adaptive adjustment module and the memory signal optimization module are optimized according to the dynamic adjustment strategy. Different optimization means are adopted for different parameter types, a customized optimization system with one parameter and one scheme is formed, it is ensured that the optimized target signal is optimal in amplitude stability, time sequence accuracy, anti-noise capacity and impedance matching degree, the feedback monitoring module is combined with the multi-dimensional parameter analysis module, and the multi-dimensional parameter analysis module is combined with the feedback monitoring module. And through full-dimension index monitoring and dynamic calibration, the continuous adaptability of the system to the running state of the memory and the long-term stability of signal integrity are guaranteed.

The invention discloses a U.2 interface-based server intelligent integrated hierarchical storage system and method, relates to the technical field of computer server storage, and is used for solving the problem of optimization of multi-type SSD data access efficiency and storage resource utilization rate. Firstly, a multi-protocol parallel channel is established by redefining U.2 interface reserved pins, signal integrity parameters are monitored in real time and fused with equipment I / O access features, and an I / O feature sequence of physical layer state information is generated; then, based on a time sequence convolutional neural network, extracting access mode multi-scale features, calculating a data block access heat probability, mapping and determining a target storage hierarchy, and generating a scheduling instruction containing a source physical address, the target hierarchy and a migration priority; the migration execution module realizes zero-copy migration of the data block between the shared DRAM pool and the SSD according to the instruction; and the resource coordination module monitors system load in real time, dynamically adjusts migration concurrency and an I / O sampling strategy, and realizes self-adaptive optimization of storage performance and resource utilization.

The invention provides an electrolytic copper foil which is at least provided with a low-roughness surface, copper nodules on the low-roughness surface are rod-shaped protrusions and / or granular protrusions, the distance between every two adjacent protrusions ranges from 10 nm to 650 nm, the height of the copper nodules of the rod-shaped protrusions ranges from 300 nm to 800 nm, and the height of the copper nodules of the granular protrusions ranges from 80 nm to 250 nm. And the number of the rod-shaped bulge copper nodules and / or the granular bulges is 50-150 in every 25 mu m < 2 > of the area of the low-roughness surface. The invention further provides a preparation method and application of the electrolytic copper foil. The electrolytic copper foil provided by the invention has a low-roughness surface, so that the signal integrity of the copper foil substrate is improved, the problem of large signal transmission loss in the prior art is solved, the peeling strength between the copper foil and the substrate is improved, and the defect of insufficient peeling strength in the prior art is overcome.

A photoelectric packaging structure disclosed by the present invention comprises a packaging substrate, an optical chip, an electric chip, a lens and a micro connector, the packaging substrate is provided with a first upper surface, the first upper surface is provided with a groove, the optical chip is installed in the groove, the optical chip is provided with a second upper surface, the second upper surface is flush with the first upper surface, and the optical chip is installed in the groove. The electric chip is electrically connected with the second upper surface and the first upper surface at the same time; the lens is arranged on the packaging substrate, is positioned on one side of the optical chip and is optically coupled with the optical chip; the micro connector is installed on the packaging substrate, the micro connector is connected with an optical fiber, and the optical chip is optically coupled with the optical fiber through the lens and the micro connector. According to the photoelectric packaging structure, the signal transmission path is shortened, the possibility of impedance mismatching and signal crosstalk is reduced, the high-frequency performance and signal integrity of packaging are improved, efficient optical coupling of the optical chip and the optical fiber is achieved, the stability and efficiency of optical signal transmission are improved, and the cost is reduced. And the aspects of compactness, connection efficiency, optical coupling performance and the like are remarkably improved.

Plug connectors for use with high speed signals. The connector includes an insulative housing having a base portion and a tongue portion extending from the base portion, and conductive terminals held by the housing. Each conductive terminal has a mating portion held on a side of the tongue portion, a tail portion extending out of the housing, and an intermediate portion held in the base portion. The conductive terminals comprise signal terminals and ground terminals. A shielding member is disposed in the housing and includes features configured to provide shielding to signal terminals and electrically connect ground terminals. The shielding member also includes features configured to improve impedance consistency along conduction paths. Such a configuration meets signal integrity requirements in connectors designed for higher frequencies, while conforming to a standard that constrains mating and mounting interfaces.

The invention relates to the technical field of circuit board processing, and discloses a circuit board back drilling stub control method, device and equipment and a medium, and the circuit board back drilling stub control method comprises the steps: carrying out the board thickness measurement of a circuit board, obtaining the original board thickness data, carrying out the difference analysis, and carrying out the piling and measurement processing according to the analysis result; obtaining a plate thickness data set corresponding to each pile; measuring and analyzing the target back drilling hole position to obtain grouped plate thickness data, calculating the influence degree of the plate thickness on the length of the back drilling stub, comparing the influence degree with a preset threshold value, and judging a back drilling depth adjusting scheme; and according to a judgment result, back drilling processing depth parameters of the whole or the partitions are calculated, and differentiated depth optimization control is achieved. According to the method, the stub range can be effectively reduced in multi-batch and high-layer PCB machining, the back drilling depth control precision is improved, and it is ensured that the stub length is stable and meets the high-specification signal integrity requirement.

The invention relates to the technical field of high-speed rail fault detection, and discloses an intelligent fault detection system for a high-speed rail. A data acquisition module of the system acquires a heterogeneous operation log data set, including vibration, temperature, current time sequence data and control signal data, of a high-speed rail core component in a preset monitoring period; the stability evaluation module performs multi-dimensional stability analysis on the data set to generate vibration, temperature and current stability indexes and signal integrity indexes; the detection configuration optimization module takes a multi-dimensional index as an index, performs self-adaptive search in a pre-constructed high-dimensional fault detection configuration space, and determines a dynamic detection step length; and the fault detection execution module drives the multi-sensor array to execute periodic detection based on the dynamic detection step length, generates a real-time monitoring data stream, and extracts abnormal features through a fault mode recognition engine. The system can comprehensively capture the operation state of the component, adaptively adjust the detection configuration, improve the fault detection accuracy and real-time performance, and guarantee the operation safety of the high-speed rail.

The invention discloses an unmanned aerial vehicle instruction link blocking interference method and device based on communication protocol identification, which can effectively solve the problems of high power consumption, large interference on legal communication and insufficient anti-frequency hopping unmanned aerial vehicle effect in the prior art by introducing a communication protocol identification mechanism in the unmanned aerial vehicle instruction link blocking process. Firstly, signal integrity is guaranteed through monitoring and preprocessing, then an unmanned aerial vehicle link protocol is identified through feature extraction and protocol library matching, and then a targeted interference template is generated, so that the interference effect can accurately fall on key positions such as a leader sequence, a CRC field, a subcarrier or a control frame and the like; and synchronization, verification or data transmission can be destroyed under a low-power condition, so that accidental damage of broadband noise to same-frequency Wi-Fi and Bluetooth services is avoided. Meanwhile, through a frequency hopping prediction model and a scheduling mechanism, the interference signal can follow the frequency hopping switching of the unmanned aerial vehicle in real time.

A terminal module includes a differential signal terminal pair, two ground terminals and an insulative bracket. Each ground terminal has a plate surface. The insulative bracket is integrally molded to locally clad the differential signal terminal pair and the two ground terminals. The insulative bracket has a surface which corresponds to the plate surfaces of the two ground terminals, the surface is provided with two depressed segments. At least a part of a position of each depressed segment corresponds to the plate surface of the corresponding ground terminal, each depressed segment is an elongated structure and a length direction of each depressed segment extends along a length direction of the corresponding ground terminal. As such, good signal integrity efficacy can be maintained when a signal is transmitted by the two signal terminals, so that crosstalk between the two adjacent differential signal terminal pairs can be lowered.

The invention discloses a 3D packaging structure and a manufacturing method thereof, and the method employs a glass wafer as a first carrier plate, and solves the problems of reliability and signal interference caused by the mismatching of thermal expansion coefficients of an organic material adapter plate and a Si-based silicon bridge chip. In S1, a blind hole is etched by taking a glass wafer as a base material, and Cu is metallized and filled, and the thermal expansion coefficient of glass is similar to that of a silicon bridge, so that the risk of thermal stress deformation is reduced. And S2, through groove etching, temporary carrier plate bonding and thinning, a through groove hole is formed, and the rigid structure of the glass carrier plate maintains the stability of the packaging structure during high-density integration. And S3, the silicon bridge Die is embedded into the through groove hole, the low thermal expansion characteristic of the glass is well matched with the silicon bridge, the interface stress is reduced, the dielectric property of the glass support plate is excellent, the signal dielectric loss is reduced, and the signal integrity is improved by matching with the silicon bridge Die. And S4, after the functional chip is mounted on the adapter plate, the glass-based adapter plate ensures reliable connection, signal attenuation distortion is inhibited, and a reliable packaging scheme is provided for high-density integration.

The invention discloses a preparation method of a photoelectric co-packaging CPO glass substrate and the CPO glass substrate. The method comprises the following steps: providing a glass substrate with two preset photon integration (PIC) areas and an electronic integration (EIC) area; for each glass substrate, manufacturing a TGV through hole and a blind groove in a PIC area and an EIC area; the two glass substrates are attached face to face to form a glass substrate stacking body, and the butt joint blind grooves form micro-channels for heat dissipation medium flowing; cutting the glass substrate stack to obtain a first part corresponding to the PIC region and a second part corresponding to the EIC region; functionalizing the TGV through holes of the two parts to obtain a first module and a second module; and integrating the two modules on a common glass substrate to form the CPO glass substrate. According to the method, low-loss optical coupling and high-density electrical interconnection are realized in the same layout, crosstalk and reflection are reduced, and signal integrity and bandwidth are improved; and meanwhile, the heat management efficiency and reliability are optimized, and the requirements of EIC heat dissipation and PIC temperature control are both considered.

The invention provides a plug shielding contact, a bent male connector and a connector assembly. The plug shielding contact comprises a contact part, a plugging end common ground part and a plug shielding contact, insertion cavities are arranged on the insertion end common ground piece; the plug shielding contact is provided with a shielding cavity along the plugging direction; the contact part comprises an injection molding part and a shielding sheet assembly. The shielding sheet assembly comprises a first shielding sheet and a second shielding sheet which are oppositely arranged on the two sides of the injection molding part, and a differential signal pair used for differential signal transmission is arranged in the injection molding part; the head end of the injection molding part is provided with a connecting plug capable of extending into the shielding cavity; according to the scheme, the structure is improved and optimized, so that the signal integrity in the connector transmission process is improved, and the signal transmission of a hardware link can be effectively ensured.

The invention relates to the technical field of FPC (Flexible Printed Circuit) laminated structure optimization, in particular to a module FPC laminated structure optimization system based on signal integrity, which comprises a laminated parameter sensitivity extraction module used for defining the thickness of a dielectric layer, the thickness of a copper foil and a dielectric constant as closed interval values with upper and lower boundaries according to FPC design specifications. According to the method, the accumulated deviation area and the normalized confidence score are obtained in combination with integral operation, conversion from a frequency domain to a time domain and from qualitative analysis to quantitative evaluation is achieved, tiny flaws of impedance continuity are captured, inferior paths are screened based on the confidence score, and a physical junction area is positioned. The geometric gravity center of the deviation area is calculated to be matched with the slope and the length of the gradient line, a smoothly-transited geometric figure is constructed, structural compensation can be achieved in areas where impedance is prone to sudden change such as a reinforcing plate junction and covering film pressing, and signal reflection caused by physical sudden change of a stacked structure is eliminated.

The invention discloses a brain-computer interface signal enhancement method and system based on sound wave coupling, and relates to the technical field of brain-computer interface signal processing.The method comprises the steps that multichannel brain-computer interface signals are collected, missing sampling points of the signals are detected, and a missing signal matrix is generated; a NeRF sound field model is established according to the spatial position, the emission angle and the sound pressure intensity of the corresponding moment of the missing signal matrix, and sound field distribution characteristics are obtained; inputting the missing signal matrix and the sound field distribution characteristics into a nested generation network to generate a complemented electroencephalogram signal; based on the difference between the complemented electroencephalogram signals and the sound field prediction frequency spectrum, physical and physiological consistency loss is calculated, and complementation effect evaluation is conducted on the complemented electroencephalogram signals; inputting the consistency loss and the complementation effect evaluation into a reinforcement learning strategy network, and determining sound wave emission parameters; sound wave stimulation is adjusted in real time through sound wave emission parameters, updated electroencephalogram signals are collected, deletion detection is repeated, and brain-computer interface signal enhancement is achieved. And the signal integrity and availability are obviously improved.

The invention provides a photoelectric chip common packaging piece, an optical communication module and a preparation method, the photoelectric chip common packaging piece comprises a carrier plate, an optical chip and an electric chip, one side of the carrier plate is provided with a mounting surface, the mounting surface is provided with an electric interconnection structure, the carrier plate is internally provided with a conductive through hole and an optical interconnection structure, and the conductive through hole is electrically connected with the electric interconnection structure; the optical chip and the electric chip are both arranged on the mounting surface of the carrier plate, the optical chip is electrically connected to the electric chip through an electric interconnection structure, one side, facing the mounting surface, of the optical chip comprises an optical device, and an optical signal emitted by the optical device penetrates through the carrier plate through the optical interconnection structure. Compared with the prior art, efficient conversion and transmission of optical signals and electric signals are achieved, the interconnection distance between chips is shortened to a large extent, signal transmission loss and delay are reduced, signal integrity is improved, and therefore reliable transmission of high-frequency signals is achieved.

A high-speed transmission circuit comprises, as part of a signal path, a connector pin disposed on a pad that comprises an unused pad region. The unused pad region is not considered part of the signal path but is part of a resonant sub-circuit. In various embodiments, by properly adjusting the dimensions of the pad region and other structures in the high-speed transmission circuit, resonant frequencies of the sub-circuit are shifted to a frequency range that is outside of the frequency range of interest in the signal path, thereby, reducing insertion loss and increasing signal integrity without compromising mechanical stability.

The invention relates to the technical field of integrating instruments, in particular to a multi-interface heat flow integrating instrument, which comprises a multi-system input interface unit, and is characterized in that pulse signals, 4-20mA current signals and differential voltage signals are accessed through a phoenix terminal array; the input end of the heterogeneous switch matrix is electrically connected with the output end of the multi-system input interface unit, and the heterogeneous switch matrix is used for matching signal types and frequency bands of output signals of different types of sensors; and the input end of the optomagnetic double-coupling driving module is connected with the control port of the heterogeneous switch matrix, so that the signal integrity and the system safety are improved. Compared with the prior art, by arranging the multi-system input interface unit, the standby power consumption is greatly reduced, the system response speed is improved, the structure has the characteristics of high adaptability, high compatibility and low power consumption, and a high-reliability and intelligent access platform is provided for parallel deployment of various heat flow sensors.

The invention provides a cable quality detection method and system. The method comprises the steps of applying a multi-band test signal to an input end of a to-be-tested cable in response to detection of completion of production of a current batch of cables, and collecting output response data of the test signal through a sensor array arranged on the to-be-tested cable; constructing a signal attenuation model and a noise distribution model of the to-be-tested cable based on the output response data; performing simulation analysis on the signal attenuation model and the noise distribution model to generate a communication performance predicted value of the cable, the communication performance predicted value including signal integrity, a signal-to-noise ratio and an error rate; and comparing the communication performance prediction value with a preset performance threshold, and if a deviation exists, adjusting boundary condition parameters of the to-be-tested cable and then confirming the communication performance prediction value again until the communication performance prediction value meets the preset performance threshold. According to the invention, the quality consistency and the communication reliability of the cable before leaving a factory are remarkably improved.

The invention relates to a photoelectric coupling structure and a manufacturing method thereof. The photoelectric coupling structure comprises a substrate; the electronic integrated chip and the first chips are located on the substrate, and the multiple first chips are arranged around the periphery of the electronic integrated chip at intervals; a redistribution layer on the electronic integrated chip and the first chip; the plurality of second chips are positioned on the rewiring layer and are arranged at intervals along the boundary extension direction of the electronic integrated chip; the plurality of photonic integrated chips are positioned on the rewiring layer and are arranged around the second region at intervals; wherein the projection of the photonic integrated chip is at least partially overlapped with the projection of the first chip, and the projection of the photonic integrated chip is at least partially overlapped with the projection of the electronic integrated chip; the photonic integrated chip is electrically connected with the electronic integrated chip through the rewiring layer. Therefore, the signal integrity of the high-speed signal in the photoelectric coupling structure in the transmission process can be improved, the transmission loss is reduced, the packaging occupied area is reduced, and the packaging structure integration degree is improved.

The invention discloses a large-burial-depth pipeline nondestructive detection method and system, and relates to the technical field of pipeline positioning. The system combines a region feasibility identification module, an initial positioning module, a multi-type nondestructive detection unit, a multi-path anomaly identification module, an underground structure matching module, an intelligent obstacle avoidance compensation module and a signal fusion module, and adopts a multi-source information fusion and intelligent path planning technology. And high-precision and non-intrusive nondestructive detection of the metal pipeline with the burial depth exceeding 5 meters is realized. Through comprehensive evaluation of ground obstacles and underground interference sources, the detection path layout is optimized, and the problems of signal interference, multi-path reflection and detection blind areas in the urban complex underground environment are effectively solved. The system can accurately reject non-target structure reflection signals, dynamically generate an obstacle avoidance compensation path, and improve the detection coverage rate and the signal integrity. And finally, three-dimensional space positioning and digital map coordinate output are realized, and the accuracy of pipeline positioning and the reliability of depth estimation are remarkably improved.

The invention provides an artificial intelligence-based industrial computer predictive maintenance method, which comprises the following steps of: acquiring real-time monitoring values of clock signal jitter, signal integrity parameters and electromagnetic compatibility characteristics from mainboard circuit operation data to form multi-dimensional time sequence data, and performing feature extraction to obtain initial distribution of abnormal signals related to aging; carrying out primary distribution clustering analysis on the abnormal signals to obtain signal abnormal groups in an aging mode, and carrying out weighted analysis on interaction influence of clock signal jitter and microcrack propagation in the groups by adopting a preset convolution kernel to obtain abnormal signal group features; and identifying interference factors influencing system stability evaluation from the electromagnetic compatibility characteristic variation coupling characteristic data, and classifying the interference factors in combination with the priority initial sequence.

The invention belongs to the technical field of mobile phone mainboard testing, and particularly relates to a dynamic stress testing method and system for a folding screen mobile phone mainboard, and the method comprises the steps: constructing a testing parameter set and a stress loading model to simulate a real folding working condition; installing a mainboard to be tested and applying periodic bending stress; in the stress loading process, electrical and signal integrity and functional state parameters of the mainboard are monitored and collected in real time; stress-performance coupling analysis is carried out on the collected data, dynamic correlation between stress and performance is established, the performance state is evaluated, and fault early warning is carried out; and finally generating a test report. The system comprises a test control and modeling module, a stress loading execution module, an online monitoring module, a coupling analysis module and a report generation module, the actual bending process can be more accurately reproduced by constructing a stress loading model, the authenticity and effectiveness of the test are improved, time sequence alignment and key parameter extraction are achieved, and the test efficiency is improved. And the real-time association between the dynamic stress and the multi-dimensional performance parameters is established.

The invention provides a PCB optimization method for video analog signal transmission. The problems of signal integrity, electromagnetic interference and impedance matching of analog signals in traditional PCB design are solved. The method comprises the following steps: arranging analog signals and digital signals in a layered manner by adopting a four-layer plate design; arranging an independent grounding plane on the analog signal layer, and connecting the independent grounding plane to the main grounding layer through grounding via holes with the diameter of 0.3 mm and the spacing of not more than 5mm; a shielding layer is added to a key signal path; linear path layout is adopted according to the signal flow direction, and the distance between key components is controlled within 30 mm; uniform line width is kept, standard definition video signals are 8mil, high definition video signals are 10mil, and corners of signal lines are in 45-degree dip angle or circular arc transition. Compared with the traditional design, the PCB designed by the method has the advantages that the video signal noise is reduced by more than 15dB, the image quality is remarkably improved, the system stability is greatly enhanced, and the PCB is particularly suitable for application scenes such as medical imaging equipment, high-definition monitoring systems and professional video processing equipment.

The invention discloses a multi-dimensional test case generation method and device, and relates to the technical field of test case generation, and the method comprises the steps: building a unified causal diagram model through analyzing a schematic circuit diagram, designing a constraint document, simulating data and other multi-source inputs according to the verification demands of a complex electronic system, and automatically generating a multi-dimensional test case, the technical problems that in related technologies, model type dependency is high, natural language constraint analysis operation is lacked, schematic diagrams, design specifications, signal integrity simulation and other data generated in the design stage exist in an isolated mode, overrun scenes are ignored, and the scene coverage local limit is high are solved, and the purpose that multi-source design data are fused, so that the design efficiency is improved is achieved. The unified causal graph model is constructed, and the complete expression of the design intention and the dominance of the implicit knowledge are realized, so that the technical effects of remarkably improving the coverage range of the test scene and the utilization efficiency of the test resources are achieved.

The invention relates to the technical field of data storage, and discloses a method for testing the signal quality of an IO interface of a memory module, and the method comprises the steps: verifying the signal integrity of the I / O interface in the memory module based on an eye diagram analysis method; after the signal is verified to be complete, the morphological characteristics of the input eye pattern and the output eye pattern are quantitatively compared, whether morphological characteristic changes occur in the signal transmission process or not is judged, and the morphological characteristic changes at least comprise logic level flipping errors, time sequence recognition errors and signal quality degradation; if the morphological characteristics of the input eye pattern are consistent with the morphological characteristics of the output eye pattern, the test is successful; and if the morphological characteristics of the input eye pattern are inconsistent with the morphological characteristics of the output eye pattern, determining that the test fails. Visual and quantitative verification of signal integrity is realized through eye pattern analysis, multi-dimensional indexes such as voltage, time sequence and noise are covered, and the signal transmission quality is reflected more comprehensively compared with a single parameter test.

The invention discloses a partial discharge signal noise suppression method, system and device and a medium, and the method comprises the following steps: receiving an original partial discharge signal, calculating the kurtosis value of the original partial discharge signal, and constructing a kurtosis criterion; constructing a variational mode decomposition model, and optimizing parameters of the variational mode decomposition model by using a northern eagle algorithm; variational mode decomposition is performed on the original partial discharge signal based on the optimized parameters, the kurtosis value of each mode component is calculated, and an effective mode component and a noise mode component are divided according to the kurtosis criterion; reconstructing the effective modal component to obtain an intermediate signal; and performing signal enhancement on the intermediate signal by using a wavelet denoising method based on an improved threshold to obtain a denoised partial discharge signal. According to the method, the noise suppression precision, the algorithm stability, the operation efficiency and the signal integrity of partial discharge signal processing can be effectively improved.

The invention relates to the technical field of electronic design automation, and provides an intelligent three-dimensional design optimization system for an ink-jet circuit board. The system comprises a field programmable gate array core control module, a microcontroller co-processing module, a multi-channel stepping motor driving module, a multi-mode communication interface module, a sensor feedback and state monitoring module and a three-dimensional layout optimization structure. High-precision real-time control and management are realized through heterogeneous cooperation of the programmable gate array core control module and the microcontroller cooperative processing module; in cooperation with multi-channel stepping motor driving, multi-mode communication and sensor feedback, a three-dimensional layout optimization structure is used for carrying out system space optimization on components, signals and a power supply, and heat dissipation, electromagnetic compatibility and signal integrity are remarkably improved. According to the system, the control precision and the real-time monitoring and remote management efficiency are effectively improved, the response speed, the operation stability and the maintainability of the system are enhanced, and high integration level and high reliability are achieved.

An adaptive calibration detection method for an analog-to-digital converter chip comprises the following steps: acquiring an input analog signal of the analog-to-digital converter chip, and sampling the input analog signal to obtain a sampling signal; performing spectrum analysis on the sampling signal to obtain a spectrum characteristic parameter of the sampling signal; judging whether the analog-to-digital converter chip has a nonlinear error, an offset error or a gain error or not according to the frequency spectrum characteristic parameters; if an error exists, calculating a calibration parameter based on a preset calibration model in combination with the spectrum characteristic parameter; according to the calibration parameters, the conversion process of the analog-to-digital converter chip is adjusted in real time so as to compensate the errors, automatic detection and calibration of various errors of the analog-to-digital converter chip are achieved, the calibration precision and efficiency are improved, and meanwhile the performance of the high-speed channel signal integrity chip can be accurately evaluated.