1244 results about "Digital circuitry" patented technology

A high-energy efficiency, low-power consumption passive radio frequency identification tag chip. A high-energy efficiency bridge rectifier circuit is constructed in an analog circuit portion by using an NMOS transistor, and an alternating-current voltage signal is converted into a direct-current signal. Meanwhile, a three-stage amplitude-limiting circuit is added to prevent an induced voltage from being too large and thus breaking down a transistor. The load at two ends of an antenna is changed by using an encoded signal to control the MOS transistor turning on and off, and then voltage values at the two ends of the antenna are adjusted by controlling a leakage current, achieving the purposes of load modulation and signal transmission. High-precision, high-speed decoding is achieved at a digital circuit portion by using a pulse position modulation decoder. The encoded signal is generated by using a Manchester encoder based on FSM control. An anti-collision circuit is used to handle a possible situation in which a plurality of RFID tags simultaneously exist in an interrogation zone. A uniquely designed read timing control circuit is used in an EEPROM memory portion, so that the power consumption of the circuit may be effectively reduced. The described chip has the characteristics of high energy efficiency, low power consumption, and low adjustment index, and is widely applied to the field of RFID identification.

Aspects of the subject disclosure may include, for example, a device including a detector configured to identify a narrow-band absorption occurring within a signal spectrum of an optical signal propagating through a gaseous medium, wherein the optical signal is configured to communicate digital information via an optical communication link including a transmitter, a receiver and an optical transport medium therebetween. The device further includes a mitigation controller configured to control a digital circuit to mitigate at least a portion of a vulnerability of the optical communication link, the vulnerability associated with the narrow-band absorption. Other embodiments are disclosed.

The invention discloses a method for verifying a digital circuit module in an integrated circuit, which belongs to the technical field of circuit testing and comprises the following specific steps: I, analyzing functional requirements and performance indexes of the circuit module and constructing a virtual model; iI, identifying abnormity and boundary conditions in the circuit module and generating a test case; iII, performing function verification on the circuit module and evaluating module performance; iV, optimizing the current circuit configuration according to a performance evaluation result; v, carrying out randomness verification on the circuit to detect potential vulnerability and design defects; according to the method, the circuit performance can be remarkably improved, the workload of manual parameter adjustment is reduced, the design complexity and verification difficulty are reduced, the performance of a circuit module in various scenes is improved, an input area which may cause problems can be focused on under limited test resources, the comprehensiveness and verification efficiency of the verification process are improved, and the verification efficiency is improved. And the stability evaluation of the circuit is more accurate, and the verification can be continuously improved.

A mixed-signal circuit may include an analog circuit and a digital circuit coupled to the analog circuit, wherein the analog circuit is configured to, in a normal operation mode, provide an analog signal to the digital circuit, and wherein the digital circuit is configured to, in the normal operation mode, provide a digital signal to the analog circuit, the mixed-signal circuit may further include a test signal generator configured to, during a test operation mode, receive the digital signal from the digital circuit, generate a test signal based on the digital signal, and provide the test signal to the digital circuit, wherein the test signal generator is configured to generate the test signal using an emulation of the analog circuit, and wherein the mixed-signal circuit is tested based on an output of the digital circuit that is generated in response to the test signal.

The invention relates to the technical field of circuit design, in particular to a digital circuit simulation design method and system. The method comprises the following steps: identifying a design demand document, performing deep semantic analysis and demand constraint mining, and constructing a demand specification constraint parameter set; performing demand complexity evaluation and multi-level division according to the demand specification constraint parameter set, and constructing a basic circuit architecture design blueprint; circuit routing path planning is carried out according to the basic circuit architecture design blueprint, and a standardized circuit topology network is constructed; performing electric signal propagation simulation on the standardized circuit topology network, and performing global circuit adaptability adjustment to obtain a circuit topology design scheme; and carrying out an extreme condition simulation test based on the circuit topology design scheme, and carrying out comprehensive performance evaluation to obtain a circuit performance evaluation report. By deeply understanding the user demand intention, the circuit layout matched with the user demand is designed, and the overall circuit performance is improved.

The invention provides an artificial intelligence-based interface circuit design method, which comprises the following steps of: S1, acquiring an RTL code for describing a logic structure of a digital circuit, and generating a digital circuit layout according to the RTL code by utilizing a preset neural network model; s2, acquiring a preset process library and design parameters of the analog circuit, and generating an analog circuit layout by using a preset neural network model according to the process library and the design parameters of the analog circuit; and S3, fusing the digital circuit layout and the analog circuit layout by using a preset neural network model to obtain the layout of the interface circuit.

The invention discloses a single-line return-to-zero code LED drive control chip circuit which comprises a power management circuit, a start reset circuit, an oscillator circuit, a bias current circuit, a digital circuit and a light emitting diode drive circuit. The light emitting diode driving circuit comprises a driving channel of a white light emitting diode chip, a driving channel of a red light emitting diode chip, a driving channel of a green light emitting diode chip and a driving channel of a blue light emitting diode chip, and the power management circuit is used for ensuring that the power supply is turned off when all-zero data or no data is input by analyzing the states of the previous data and the next data in the power management signal. The single-line return-to-zero code LED driving control chip solves the problems that the current single-line return-to-zero code LED driving control chip with a three-channel design does not have a sleep mode, so that effective power consumption management is lacked when the brightness and the color of an LED are controlled, and the whole LED device still has static power consumption waste in a non-light-emitting state.

The invention discloses a cluster model acceleration method and device based on an FPGA, and relates to the technical field of model acceleration, and the method comprises the steps: converting a cluster simulation model into a digital circuit structure file, and burning the digital circuit structure file into an FPGA board card; splitting the digital circuit structure file into a plurality of independent calculation modules according to functions; packaging the calculation module into a plurality of IP cores based on the requirements of different individuals in the cluster; in response to input data received in the DDR of the FPGA board card, the hardware state machine triggers all the IP cores to execute corresponding tasks in parallel, and the calculation process of each IP core is controlled by taking a main clock of the FPGA board card as a reference; and each IP core writes the task processing result into a DDR (Double Data Rate) of the FPGA board card, and reads the DDR to obtain a simulation result of the cluster simulation model. The technical problems that an existing model acceleration method is poor in real-time performance and high in economic cost in a large-scale cluster simulation scene are solved, and therefore in the large-scale cluster simulation scene, high real-time performance of simulation can be guaranteed, and the economic cost can be effectively reduced.

The various implementations described herein include techniques and apparatuses for multi-channel biopotential signal acquisition, biopotential signal pre-processing, and adaptive signal conditioning. In one aspect, an analog frontend circuit includes an instrumentation amplifier (INA) and an analog-to-digital circuit (ADC) in a forward signal path. A digital circuit receives input from the ADC. An adaptive baseline tracking and compensation circuit tracks and compensates moving motion artifact driven changes. A power line interference (PLI) detection and compensation circuit tracks a desired number of PLI harmonics, and magnitude, phase and frequency for the PLI harmonics in real time. A digital-to-analog converter (DAC) circuit combines output of the adaptive baseline tracking and compensation circuit and the PLI detection and compensation circuit to output an analog output. A passive filter receives the analog output and drives an analog compensation signal at an input of the INA.

The invention relates to the field of digital circuit experiment teaching, in particular to a digital circuit experiment platform and method applying a multi-modal large model and a medium, and the method comprises the steps: inputting experiment task description, analyzing and extracting structured semantic information, and forming task representation; retrieving a circuit function block from the electronic component knowledge base, constructing a context enhancement cue word, guiding a multi-modal large language model to generate a Verilog HDL code, and outputting the Verilog HDL code after grammar check and function verification; a Yosys tool is used for carrying out logic synthesis on the codes to generate a standard JSON netlist, and then the standard JSON netlist is converted into an SVG-format circuit diagram through a Netlistsvg tool; and an electronic component knowledge base updating mechanism is constructed to realize knowledge cyclic evolution and adaptive enhancement, so that the intelligent level and practical training efficiency of circuit experiment teaching are remarkably improved.

The invention provides a PCIe (Peripheral Component Interconnect Express)-Ethernet high-speed data transmission system based on an FPGA (Field Programmable Gate Array), which belongs to the field of communication of digital circuits and comprises a PCIe interface module, a gigabit Ethernet interface module, a DDR3 (Double Data Rate 3) cache module and an AXI (Advanced eXtensible Interface) bus control module. The high-speed data transmission capability of the PCIe interface and the flexible port expansion capability of the gigabit Ethernet interface are integrated, and a user datagram protocol (UDP)-based control logic is constructed to realize data interaction between the PCIe and the gigabit Ethernet, so that high-speed and reliable data transmission is realized; and the high requirements of a high-speed signal acquisition and playback system and the like on the data transmission rate and reliability are met.

The invention discloses a synchronization unit verification method and device of a digital circuit, equipment and a medium, and relates to the technical field of computers, and the method comprises the steps: embedding an assertion statement rule and an assertion coverage rate evaluation rule in a synchronization unit; the assertion statement rule is used for monitoring the operation state and signal characteristics of the synchronization unit in the data synchronization process, the assertion statement rule is implemented in a parameterization mode to adapt to the function requirements of different circuit units, and the assertion coverage rate evaluation rule is used for counting the execution condition of the assertion statement rule; executing front-end simulation verification of the synchronization unit by utilizing the plurality of test cases, and judging whether a violation condition which is not consistent with the assertion statement rule exists in a case execution result or not: if not, calculating an execution coverage rate of the assertion statement rule based on an assertion coverage rate evaluation rule; and evaluating whether the synchronization unit passes the front-end simulation verification according to the execution coverage rate. According to the method, the possibility of omission of problems due to incomplete verification is reduced, and the execution coverage rate is improved.

A driving assembly management system, a fault detection method, and an electric power-assisted bicycle. The driving assembly management system comprises: an Internet-of-things device, multiple digital assemblies, and a bus; each digital assembly comprises: a driving assembly and a digital circuit connected to the driving assembly; the digital circuit comprises: an assembly signal processing circuit, a first processor, and a first memory; an input end of the assembly signal processing circuit is connected to a signal acquisition end of the driving assembly; the first processor is further connected to the assembly signal processing circuit; the first memory is connected to the first processor; and the Internet-of-things device is communicatively connected to the first processor in the multiple digital assemblies, so as to perform fault detection according to working state data and identification information of the multiple digital assemblies.

A method is provided for transmitting transmission data from a sensor controller that detects a pen to the pen through a sensor electrode group. The pen includes a pen tip electrode arranged near a pen tip, and an analog circuit that detects edges of a signal led to the pen tip electrode. The pen also includes a digital circuit that performs a correlation operation of an output signal of the analog circuit and known patterns to detect the transmission data. The sensor controller is configured to generate a pulse signal representing the transmission data. The sensor controller is configured to transmit the pulse signal, by using a main signal and a sub signal of the pulse signal so as to enhance the edges, thereby transmitting the transmission data through the sensor electrode group.

The invention discloses a method for deploying a flame detection spiking neural network on an FPGA (Field Programmable Gate Array). According to the method, codes of the flame detection spiking neural network are written by using a Viis HLS tool, an IP (Internet Protocol) core file is generated and burnt on the FPGA, a related digital circuit is generated, the processing speed of the flame detection spiking neural network is accelerated, and the operation power consumption is reduced. And in the design process, the technical means such as ATAN arc tangent activation function calculation and short-circuit logic calculation strategies are realized by utilizing a lookup table, so that unnecessary calculation and power consumption can be reduced, the use amount of a DSP (Digital Signal Processor) is remarkably reduced, the hardware calculation operation process is simplified, and the pulse neural network can run on an FPGA (Field Programmable Gate Array) with relatively low power consumption. Therefore, the method provided by the invention provides a set of solution for implementing effective deployment on the low-power-consumption edge equipment based on the FPGA for a flame detection application scene.

A method controls duty cycle distortion of clock signals. An electronic device obtains an input clock signal having a first frequency and a sampling clock signal having a second frequency that is lower than the first frequency. The sampling clock signal has a random noise distribution. The sampling clock signal is applied to sample high voltage duty cycles and low voltage duty cycles of the input clock signal for a duration of time to obtain a sampling result. The electronic device determines a duty cycle distortion level of the input clock signal in the duration of time based on the sampling result. A duty cycle control signal is generated based on the duty cycle distortion level to control the high voltage duty cycles of the input clock signal.

The invention provides a digital-analog hybrid simulation method and device.The method comprises the steps that a simulation modeling file is generated according to design information of an analog circuit of a chip, and the simulation modeling file comprises a digital netlist, device library configuration, device mapping configuration, simulation control parameters, simulation signal variables and digital-analog interface conversion rules; and performing digital circuit simulation according to the design information of the digital circuit of the chip and the simulation modeling file, and generating a digital-analog hybrid simulation result of the chip. According to the method provided by the invention, the compatibility between digital-analog hybrid simulation tools can be improved.

The present invention discloses a radio frequency cancellation circuit and an anti-interference receiver. The radio frequency cancellation circuit includes a radio frequency phase detection circuit, a baseband filtering and processing circuit, and a vector modulation circuit; the baseband filtering and processing circuit includes an AD circuit, a DA circuit, and a microprocessor; the output signal of the radio frequency phase detection circuit is converted into a digital circuit by the AD circuit, and then digitally filtered and phase adjusted by the microprocessor, and then converted into a reference low-frequency baseband signal by the DA circuit. The anti-interference receiver adopts the radio frequency circuit to eliminate in-band interference. In the present invention, due to the use of software radio technology, through the microprocessor and the supporting circuit, the cancellation strategy can be adjusted in real time according to the spectrum form and signal bandwidth of the interference signal, so as to achieve a good adaptive cancellation effect.

The invention provides an automatic frequency locking circuit based on a time-to-voltage converter and a phase-locked loop, and relates to the technical field of phase-locked loops, a first frequency-halving unit and a second frequency-halving unit respectively carry out frequency-halving processing on a reference signal and a frequency division signal of a current comparison period to obtain a first square wave signal and a second square wave signal; the first square wave signal and the second square wave signal are transmitted to the time-to-voltage converter; the time voltage converter comprises a phase generation unit, a first charge pump and a second charge pump, the phase generation unit generates an enable signal according to the first square wave signal and the second square wave signal, and the first charge pump and the second charge pump respond to control of the enable signal and collect single pulse signals from the first square wave signal and the second square wave signal respectively so as to supply power to the input end of the comparator; the comparator compares power supply voltages of the two input ends to achieve frequency comparison of the reference signal and the frequency division signal. And selection in a plurality of phase signals is not needed, and required digital circuit modules are reduced, so that the delay of the reference signal and the frequency division signal in the conversion process is reduced.

The invention provides a test vector construction method, which is used for constructing a test vector set required by a to-be-tested digital circuit, and comprises the following steps: S1, obtaining the to-be-tested digital circuit and a to-be-tested fault list corresponding to the to-be-tested digital circuit, the to-be-tested fault list comprising a plurality of circuit faults; s2, multiple rounds of simplification operation are executed until the number of circuit faults which can be detected by all the obtained test vectors is larger than or equal to a preset threshold value, all the test vectors obtained by each round of simplification operation are stored in a variable-capacity vector pool, the capacity of the vector pool corresponding to each round is a preset multiple of the capacity of the vector pool corresponding to the previous round, and the test vectors are stored in the variable-capacity vector pool; wherein each round of simplification operation comprises a static simplification stage and a dynamic simplification stage, the static simplification stage repeatedly fills a vector pool and reduces the number of test vectors in the vector pool, and the dynamic simplification stage fills a part of the uncertain items in the test vectors with the uncertain items obtained in the static simplification stage as 0 or 1.

The invention relates to the technical field of calculation, and discloses a continuous time digital Isin model hardware solver based on combinational logic, which comprises a plurality of neurons; the data initialization module is used for carrying out initialization assignment on corresponding coefficients of the hardware solver; after the control signal is used for carrying out initialization assignment on neurons, iterative calculation is started; the neuron updating module is used for carrying out matrix operation on an interaction relation weight matrix formed by the initialized weight coefficients and initialized neurons, and adding the matrix operation and bias to obtain the cumulative sum of each neuron in the current neuron state; the neuron activation module is used for adding nonlinear factors for iterative calculation; the high precision of a digital circuit is utilized, but the continuity of a physical system is also utilized at the same time, so that acceleration hardware which is lower in energy consumption and faster in digit solving is realized.

The invention belongs to the technical field of semiconductor design automation, and provides a digital circuit wiring method and related equipment. The method comprises the steps that wiring grid parameters of all wiring layers in a digital circuit to be wired are acquired, and grid lines of a wiring grid are used for restraining a wiring track; on the basis of the wiring grid parameters, the digital circuit is divided into a plurality of wiring subareas, and the area size of each wiring layer in each wiring subarea is different; traversing each signal path, and determining an access point for performing wiring indexing on each signal path; based on the access points of the signal paths in the wiring partitions, wiring the signal paths in the wiring partitions in parallel through wiring threads respectively configured for the wiring partitions; and combining the wirings of the signal paths in the wiring partitions to obtain a complete wiring of the digital circuit. According to the technical scheme provided by the invention, the wiring efficiency of the digital circuit can be improved.

A method includes: receiving a circuit design including circuit stages; deriving initial logic conditions for nets in a fanout cone from an input port in accordance with a primordial event; initializing a priority queue of logic transition events with the primordial event; determining a trigger event from the priority queue, the trigger event having a timestamp equal to or earlier than all others in the priority queue and representing a logic transition at an input pin of a current circuit stage; simulating an arc of the circuit design from the input pin of the current circuit stage to an input pin of a fanout circuit stage to generate a propagated event; computing a propagated event timestamp based on: the trigger event timestamp; and a delay associated with the arc; enqueuing the propagated event on the priority queue; and generating a static analysis report based on the propagated event timestamp.

The invention discloses a parallel-serial conversion circuit based on a composite dielectric gate photosensitive detector, and belongs to the field of integrated circuits. The parallel-serial conversion circuit comprises a composite dielectric gate photosensitive detector pixel, a ramp generator, a clamping circuit, a switch S1, a pre-charging circuit, a comparator, a counter, 8-256 decoders, a first AND gate, 256 second AND gates and a 256 input OR gate. According to the parallel-serial conversion circuit, all digital circuit parts are converted into analog circuits, so that the circuit design complexity is reduced, the circuit simulation and layout design iteration period is shortened, the power consumption and the area of a chip are effectively reduced, and the design of a subsequent miniaturized system is facilitated.

The invention provides a parallel-serial conversion circuit and method based on clock edge alignment, and the circuit comprises a clock jump delay circuit which is used for carrying out the phase delay of an input signal of an analog circuit, a frequency division module which is used for carrying out the frequency division processing of the signal after phase delay, and a clock edge alignment module. The input signal is directly subjected to frequency division processing and then is sent to the digital circuit; the clock synchronization detection circuit is used for carrying out synchronization detection on the signal after phase delay and frequency division processing and the signal output by the digital circuit; the logic control module is used for sending a control signal to the clock hopping delay circuit according to a synchronous detection result; the clock hopping delay circuit adjusts the phase of the analog clock according to the control signal until synchronous detection results are consistent, and clock edge alignment of the analog circuit and the digital circuit is completed; and performing data parallel-serial conversion according to the analog circuit and the digital circuit after the clock edges are aligned. According to the invention, clock alignment can be automatically realized.

A digital circuit according of the invention is a digital circuit provided in a semiconductor device to control analog elements. The digital circuit includes a digital communication circuit, a random access memory, a temporary parameter store, and an output circuit. The digital communication circuit receives a control message including a command and data in one communication transaction. The random access memory stores a look-up table. The look-up table has an address and a data set corresponding to the address. The data set includes a plurality of analog-element control parameters. The temporary parameter store temporarily stores the data received by the digital communication circuit in the communication transaction. The temporary parameter store prepares a data set to be stored to one address of the look-up table. The output circuit outputs a setting-parameter.

The neuron Logic Gate Metal-Oxide-Semiconductor (νLGMOS) circuits to mimic neurons' “integrate-and-fire” behaviors in biological neural network system can be fabricated with industry Complementary Metal-Oxide Semiconductor (CMOS) logic process technology, with which digital computational circuits are fabricated. A processing system having analog νLGMOS circuits, conversion circuitry and digital circuits optimized for power and cost for varieties of applications can be then fabricated with the same CMOS logic process technology for IC chips. Meanwhile analog νLGMOS circuits inspired from biological neural network systems can be simulated, designed, and fabricated for IC chips for the applications of biomedical fields.

The invention provides a wireless connection method and system for digital circuit JATG debugging, a medium and equipment, and the method comprises the steps: 1, achieving the wireless connection through employing a JATG interface signal wireless unvarnished transmission A-end part and a B-end part, enabling the A-end part to be connected with an adapter through a JATG interface flat cable, enabling the B-end part to be connected with a JATG interface of target equipment, and enabling the A-end part to be connected with the adapter through a JATG interface flat cable; data transmission is carried out between the A-end component and the B-end component through WIFI signals. The adapter is connected with the debugging computer through a USB data line and communicates with target equipment through a wireless signal; 2, setting a multi-bit dial switch to set a unique matching address for each B-end component; and step 3, controlling the A-end component and the corresponding B-end component to be wirelessly matched and connected through a dial switch or a USB serial port command after power-on, and performing online debugging, testing and program updating on target equipment by using IDE software interface operation after wireless connection is completed.

An acceleration sensor circuit is disclosed. The acceleration sensor circuit includes a package; an accelerometer to generate acceleration data samples during a peak tracking window; a sample register, to store the acceleration data samples; an acceleration calculation digital circuit, to calculate an acceleration magnitude sample based on the stored acceleration data samples; a peak register, to store a current peak acceleration value; a sample compare circuit, to compare the acceleration magnitude sample to the current peak acceleration value, where the peak register is configured to replace the current peak acceleration value with the acceleration magnitude sample in response to the sample compare circuit determining that the acceleration magnitude sample is greater than the current peak acceleration value; and a memory, configured to store the current peak acceleration value, and to transmit the current peak acceleration value to an external circuit in response to an end of the peak tracking window.

The invention discloses a digital circuit optimization method and system based on logic clustering. The method comprises the following steps: S1, counting fan-out information of all registers in a circuit netlist; s2, according to the fan-out information of the registers, screening out the registers of which the fan-out quantity is greater than a first preset threshold value and the logic series is greater than a second preset threshold value and which are located on the critical path, and generating a candidate register list; s3, obtaining register fan-out first-level combinatorial logic information; s4, performing clustering operation on the logic units based on the first-level combinational logic information, and dividing physically adjacent logic units into the same cluster according to the physical position relationship of the logic units; s5, associating the clustered logic units together and adjusting the connection relation of the logic units; s6, carrying out equivalence check; and S7, rearranging and wiring the circuit according to the modified netlist. The physical distance of a time sequence path can be effectively reduced, the time sequence performance of the circuit is optimized, and the method is suitable for large-scale integrated circuit design.