937 results about "Digital circuitry" patented technology

The invention relates to the technical field of circuit design, in particular to a digital circuit simulation design method and system. The method comprises the following steps: identifying a design demand document, performing deep semantic analysis and demand constraint mining, and constructing a demand specification constraint parameter set; performing demand complexity evaluation and multi-level division according to the demand specification constraint parameter set, and constructing a basic circuit architecture design blueprint; circuit routing path planning is carried out according to the basic circuit architecture design blueprint, and a standardized circuit topology network is constructed; performing electric signal propagation simulation on the standardized circuit topology network, and performing global circuit adaptability adjustment to obtain a circuit topology design scheme; and carrying out an extreme condition simulation test based on the circuit topology design scheme, and carrying out comprehensive performance evaluation to obtain a circuit performance evaluation report. By deeply understanding the user demand intention, the circuit layout matched with the user demand is designed, and the overall circuit performance is improved.

The invention provides an artificial intelligence-based interface circuit design method, which comprises the following steps of: S1, acquiring an RTL code for describing a logic structure of a digital circuit, and generating a digital circuit layout according to the RTL code by utilizing a preset neural network model; s2, acquiring a preset process library and design parameters of the analog circuit, and generating an analog circuit layout by using a preset neural network model according to the process library and the design parameters of the analog circuit; and S3, fusing the digital circuit layout and the analog circuit layout by using a preset neural network model to obtain the layout of the interface circuit.

The invention discloses a cluster model acceleration method and device based on an FPGA, and relates to the technical field of model acceleration, and the method comprises the steps: converting a cluster simulation model into a digital circuit structure file, and burning the digital circuit structure file into an FPGA board card; splitting the digital circuit structure file into a plurality of independent calculation modules according to functions; packaging the calculation module into a plurality of IP cores based on the requirements of different individuals in the cluster; in response to input data received in the DDR of the FPGA board card, the hardware state machine triggers all the IP cores to execute corresponding tasks in parallel, and the calculation process of each IP core is controlled by taking a main clock of the FPGA board card as a reference; and each IP core writes the task processing result into a DDR (Double Data Rate) of the FPGA board card, and reads the DDR to obtain a simulation result of the cluster simulation model. The technical problems that an existing model acceleration method is poor in real-time performance and high in economic cost in a large-scale cluster simulation scene are solved, and therefore in the large-scale cluster simulation scene, high real-time performance of simulation can be guaranteed, and the economic cost can be effectively reduced.

The various implementations described herein include techniques and apparatuses for multi-channel biopotential signal acquisition, biopotential signal pre-processing, and adaptive signal conditioning. In one aspect, an analog frontend circuit includes an instrumentation amplifier (INA) and an analog-to-digital circuit (ADC) in a forward signal path. A digital circuit receives input from the ADC. An adaptive baseline tracking and compensation circuit tracks and compensates moving motion artifact driven changes. A power line interference (PLI) detection and compensation circuit tracks a desired number of PLI harmonics, and magnitude, phase and frequency for the PLI harmonics in real time. A digital-to-analog converter (DAC) circuit combines output of the adaptive baseline tracking and compensation circuit and the PLI detection and compensation circuit to output an analog output. A passive filter receives the analog output and drives an analog compensation signal at an input of the INA.

The invention relates to the field of digital circuit experiment teaching, in particular to a digital circuit experiment platform and method applying a multi-modal large model and a medium, and the method comprises the steps: inputting experiment task description, analyzing and extracting structured semantic information, and forming task representation; retrieving a circuit function block from the electronic component knowledge base, constructing a context enhancement cue word, guiding a multi-modal large language model to generate a Verilog HDL code, and outputting the Verilog HDL code after grammar check and function verification; a Yosys tool is used for carrying out logic synthesis on the codes to generate a standard JSON netlist, and then the standard JSON netlist is converted into an SVG-format circuit diagram through a Netlistsvg tool; and an electronic component knowledge base updating mechanism is constructed to realize knowledge cyclic evolution and adaptive enhancement, so that the intelligent level and practical training efficiency of circuit experiment teaching are remarkably improved.

The invention provides a PCIe (Peripheral Component Interconnect Express)-Ethernet high-speed data transmission system based on an FPGA (Field Programmable Gate Array), which belongs to the field of communication of digital circuits and comprises a PCIe interface module, a gigabit Ethernet interface module, a DDR3 (Double Data Rate 3) cache module and an AXI (Advanced eXtensible Interface) bus control module. The high-speed data transmission capability of the PCIe interface and the flexible port expansion capability of the gigabit Ethernet interface are integrated, and a user datagram protocol (UDP)-based control logic is constructed to realize data interaction between the PCIe and the gigabit Ethernet, so that high-speed and reliable data transmission is realized; and the high requirements of a high-speed signal acquisition and playback system and the like on the data transmission rate and reliability are met.

The invention discloses a synchronization unit verification method and device of a digital circuit, equipment and a medium, and relates to the technical field of computers, and the method comprises the steps: embedding an assertion statement rule and an assertion coverage rate evaluation rule in a synchronization unit; the assertion statement rule is used for monitoring the operation state and signal characteristics of the synchronization unit in the data synchronization process, the assertion statement rule is implemented in a parameterization mode to adapt to the function requirements of different circuit units, and the assertion coverage rate evaluation rule is used for counting the execution condition of the assertion statement rule; executing front-end simulation verification of the synchronization unit by utilizing the plurality of test cases, and judging whether a violation condition which is not consistent with the assertion statement rule exists in a case execution result or not: if not, calculating an execution coverage rate of the assertion statement rule based on an assertion coverage rate evaluation rule; and evaluating whether the synchronization unit passes the front-end simulation verification according to the execution coverage rate. According to the method, the possibility of omission of problems due to incomplete verification is reduced, and the execution coverage rate is improved.

The invention discloses a method for deploying a flame detection spiking neural network on an FPGA (Field Programmable Gate Array). According to the method, codes of the flame detection spiking neural network are written by using a Viis HLS tool, an IP (Internet Protocol) core file is generated and burnt on the FPGA, a related digital circuit is generated, the processing speed of the flame detection spiking neural network is accelerated, and the operation power consumption is reduced. And in the design process, the technical means such as ATAN arc tangent activation function calculation and short-circuit logic calculation strategies are realized by utilizing a lookup table, so that unnecessary calculation and power consumption can be reduced, the use amount of a DSP (Digital Signal Processor) is remarkably reduced, the hardware calculation operation process is simplified, and the pulse neural network can run on an FPGA (Field Programmable Gate Array) with relatively low power consumption. Therefore, the method provided by the invention provides a set of solution for implementing effective deployment on the low-power-consumption edge equipment based on the FPGA for a flame detection application scene.

The invention provides a digital-analog hybrid simulation method and device.The method comprises the steps that a simulation modeling file is generated according to design information of an analog circuit of a chip, and the simulation modeling file comprises a digital netlist, device library configuration, device mapping configuration, simulation control parameters, simulation signal variables and digital-analog interface conversion rules; and performing digital circuit simulation according to the design information of the digital circuit of the chip and the simulation modeling file, and generating a digital-analog hybrid simulation result of the chip. According to the method provided by the invention, the compatibility between digital-analog hybrid simulation tools can be improved.

The invention provides an automatic frequency locking circuit based on a time-to-voltage converter and a phase-locked loop, and relates to the technical field of phase-locked loops, a first frequency-halving unit and a second frequency-halving unit respectively carry out frequency-halving processing on a reference signal and a frequency division signal of a current comparison period to obtain a first square wave signal and a second square wave signal; the first square wave signal and the second square wave signal are transmitted to the time-to-voltage converter; the time voltage converter comprises a phase generation unit, a first charge pump and a second charge pump, the phase generation unit generates an enable signal according to the first square wave signal and the second square wave signal, and the first charge pump and the second charge pump respond to control of the enable signal and collect single pulse signals from the first square wave signal and the second square wave signal respectively so as to supply power to the input end of the comparator; the comparator compares power supply voltages of the two input ends to achieve frequency comparison of the reference signal and the frequency division signal. And selection in a plurality of phase signals is not needed, and required digital circuit modules are reduced, so that the delay of the reference signal and the frequency division signal in the conversion process is reduced.

The invention provides a test vector construction method, which is used for constructing a test vector set required by a to-be-tested digital circuit, and comprises the following steps: S1, obtaining the to-be-tested digital circuit and a to-be-tested fault list corresponding to the to-be-tested digital circuit, the to-be-tested fault list comprising a plurality of circuit faults; s2, multiple rounds of simplification operation are executed until the number of circuit faults which can be detected by all the obtained test vectors is larger than or equal to a preset threshold value, all the test vectors obtained by each round of simplification operation are stored in a variable-capacity vector pool, the capacity of the vector pool corresponding to each round is a preset multiple of the capacity of the vector pool corresponding to the previous round, and the test vectors are stored in the variable-capacity vector pool; wherein each round of simplification operation comprises a static simplification stage and a dynamic simplification stage, the static simplification stage repeatedly fills a vector pool and reduces the number of test vectors in the vector pool, and the dynamic simplification stage fills a part of the uncertain items in the test vectors with the uncertain items obtained in the static simplification stage as 0 or 1.

The invention relates to the technical field of calculation, and discloses a continuous time digital Isin model hardware solver based on combinational logic, which comprises a plurality of neurons; the data initialization module is used for carrying out initialization assignment on corresponding coefficients of the hardware solver; after the control signal is used for carrying out initialization assignment on neurons, iterative calculation is started; the neuron updating module is used for carrying out matrix operation on an interaction relation weight matrix formed by the initialized weight coefficients and initialized neurons, and adding the matrix operation and bias to obtain the cumulative sum of each neuron in the current neuron state; the neuron activation module is used for adding nonlinear factors for iterative calculation; the high precision of a digital circuit is utilized, but the continuity of a physical system is also utilized at the same time, so that acceleration hardware which is lower in energy consumption and faster in digit solving is realized.

The invention belongs to the technical field of semiconductor design automation, and provides a digital circuit wiring method and related equipment. The method comprises the steps that wiring grid parameters of all wiring layers in a digital circuit to be wired are acquired, and grid lines of a wiring grid are used for restraining a wiring track; on the basis of the wiring grid parameters, the digital circuit is divided into a plurality of wiring subareas, and the area size of each wiring layer in each wiring subarea is different; traversing each signal path, and determining an access point for performing wiring indexing on each signal path; based on the access points of the signal paths in the wiring partitions, wiring the signal paths in the wiring partitions in parallel through wiring threads respectively configured for the wiring partitions; and combining the wirings of the signal paths in the wiring partitions to obtain a complete wiring of the digital circuit. According to the technical scheme provided by the invention, the wiring efficiency of the digital circuit can be improved.

A method includes: receiving a circuit design including circuit stages; deriving initial logic conditions for nets in a fanout cone from an input port in accordance with a primordial event; initializing a priority queue of logic transition events with the primordial event; determining a trigger event from the priority queue, the trigger event having a timestamp equal to or earlier than all others in the priority queue and representing a logic transition at an input pin of a current circuit stage; simulating an arc of the circuit design from the input pin of the current circuit stage to an input pin of a fanout circuit stage to generate a propagated event; computing a propagated event timestamp based on: the trigger event timestamp; and a delay associated with the arc; enqueuing the propagated event on the priority queue; and generating a static analysis report based on the propagated event timestamp.

A digital circuit according of the invention is a digital circuit provided in a semiconductor device to control analog elements. The digital circuit includes a digital communication circuit, a random access memory, a temporary parameter store, and an output circuit. The digital communication circuit receives a control message including a command and data in one communication transaction. The random access memory stores a look-up table. The look-up table has an address and a data set corresponding to the address. The data set includes a plurality of analog-element control parameters. The temporary parameter store temporarily stores the data received by the digital communication circuit in the communication transaction. The temporary parameter store prepares a data set to be stored to one address of the look-up table. The output circuit outputs a setting-parameter.

The invention provides a wireless connection method and system for digital circuit JATG debugging, a medium and equipment, and the method comprises the steps: 1, achieving the wireless connection through employing a JATG interface signal wireless unvarnished transmission A-end part and a B-end part, enabling the A-end part to be connected with an adapter through a JATG interface flat cable, enabling the B-end part to be connected with a JATG interface of target equipment, and enabling the A-end part to be connected with the adapter through a JATG interface flat cable; data transmission is carried out between the A-end component and the B-end component through WIFI signals. The adapter is connected with the debugging computer through a USB data line and communicates with target equipment through a wireless signal; 2, setting a multi-bit dial switch to set a unique matching address for each B-end component; and step 3, controlling the A-end component and the corresponding B-end component to be wirelessly matched and connected through a dial switch or a USB serial port command after power-on, and performing online debugging, testing and program updating on target equipment by using IDE software interface operation after wireless connection is completed.

An acceleration sensor circuit is disclosed. The acceleration sensor circuit includes a package; an accelerometer to generate acceleration data samples during a peak tracking window; a sample register, to store the acceleration data samples; an acceleration calculation digital circuit, to calculate an acceleration magnitude sample based on the stored acceleration data samples; a peak register, to store a current peak acceleration value; a sample compare circuit, to compare the acceleration magnitude sample to the current peak acceleration value, where the peak register is configured to replace the current peak acceleration value with the acceleration magnitude sample in response to the sample compare circuit determining that the acceleration magnitude sample is greater than the current peak acceleration value; and a memory, configured to store the current peak acceleration value, and to transmit the current peak acceleration value to an external circuit in response to an end of the peak tracking window.

The invention discloses a digital circuit optimization method and system based on logic clustering. The method comprises the following steps: S1, counting fan-out information of all registers in a circuit netlist; s2, according to the fan-out information of the registers, screening out the registers of which the fan-out quantity is greater than a first preset threshold value and the logic series is greater than a second preset threshold value and which are located on the critical path, and generating a candidate register list; s3, obtaining register fan-out first-level combinatorial logic information; s4, performing clustering operation on the logic units based on the first-level combinational logic information, and dividing physically adjacent logic units into the same cluster according to the physical position relationship of the logic units; s5, associating the clustered logic units together and adjusting the connection relation of the logic units; s6, carrying out equivalence check; and S7, rearranging and wiring the circuit according to the modified netlist. The physical distance of a time sequence path can be effectively reduced, the time sequence performance of the circuit is optimized, and the method is suitable for large-scale integrated circuit design.

The invention discloses a variable-sampling-rate current waveform and electromagnetic response acquisition system and a control method. The variable-sampling-rate current waveform and electromagnetic response acquisition system comprises nine parts, namely a sensor circuit, a signal conditioning circuit, an analog-to-digital conversion circuit, an analog-to-digital isolation circuit, a main control circuit, a synchronous circuit, a storage circuit, a man-machine interaction circuit and a power management module. The voltage signal is firstly processed by the signal conditioning circuit to meet the sampling requirement of the 24-bit ADC module, and then the ADC module converts an analog voltage signal into a binary digital signal based on a reference voltage; and under the action of a clock signal of the synchronization module, the converted digital signal is firstly transmitted to an external SRAM (Static Random Access Memory) through DMA (Direct Memory Access) to be cached and stored. Interference of digital circuits such as a single-chip microcomputer and crosstalk of analog signals among different channels are effectively reduced, and the problems that an acquisition system is single in sampling rate, high in short-circuit noise level, large in shallow detection blind area and low in urban underground space complex target electromagnetic detection precision are solved.

The invention provides a zero-voltage starting control module, a driving circuit and an active clamping converter, and the module comprises a timing unit which carries out the timing of a first time length; the time length acquisition unit is used for acquiring the time length from the turn-off of the clamping tube to the complete release of the secondary inductive current of the transformer to obtain a second time length; the comparison unit is used for comparing the first duration with the second duration; and the dead time adjusting unit is used for adjusting the conduction time and the first duration of the clamping tube in the next period based on the comparison result of the current period so as to realize self-adaptive zero-voltage starting control. The circuit is realized by adopting a digital circuit, accurate control can be realized, the control range is relatively wide, zero-voltage conduction control is dynamically realized, the system efficiency is improved, the use of a capacitor in an analog circuit is reduced, and the area cost of a chip is reduced.

The invention discloses a digital circuit design method and device, equipment and a medium, and relates to the technical field of digital circuits, and the method comprises the steps: determining a target type of a to-be-designed digital circuit, and collecting a first training set corresponding to the target type; each training sample in the first training set comprises an input feature item used for designing a target type of historical digital circuit and the actual result quality of the historical digital circuit, and the input feature item comprises a high-level language source code and an HLS constraint parameter; constructing an initial prediction model based on the multi-layer perceptron mixed structure, training the initial prediction model by using the first training set, and searching and optimizing the model architecture based on the network structure to obtain a target prediction model; and predicting the actual result quality corresponding to each parameter combination in a target design space of a to-be-designed digital circuit by using the model, and designing the digital circuit by using the parameter combination of which the quality meets the Pareto frontier. And predicting an accurate actual quality result by utilizing a prediction model without intermediate representation so as to carry out digital circuit design.

The invention belongs to the technical field of hardware and information security, and particularly relates to a digital PUF circuit based on an FPGA and a use method of the digital PUF circuit. In the PUF circuit, entropy source extraction and PUF response generation are separately processed, and the resistance value of a memristor in a high resistance state is collected through a memristor resistance value collection circuit; the resistance value distribution of each memristor in a high-resistance state has randomness, so that the high-resistance-state resistance value of the memristor can be used as an entropy source of the PUF circuit; a memristor-based entropy source is subjected to digital processing and is applied to a digital PUF circuit, resistance values of different memristors in a high-resistance state are randomly selected through digital chaotic signals, and finally PUF response is output by comparing the resistance values of the two memristors selected randomly in the high-resistance state. Compared with a traditional analog PUF circuit which is easily influenced by factors such as voltage fluctuation and device parameter drift, the digital PUF circuit based on the FPGA designed by the invention is higher in reliability and is not easily influenced by the factors such as the voltage fluctuation.

The invention discloses a motor control digital circuit and a driving system, and the circuit comprises a first delay time sequence module which transmits a secondary delay pulse to an acceleration and deceleration synchronization module based on a synchronization signal and delay time; the acceleration and deceleration synchronization module obtains path input after receiving the secondary delay pulse, and selects acceleration and deceleration path write-in and acceleration and deceleration position write-in sent to the acceleration and deceleration module; the stepping direction selection module receives the stepping and direction signals of the acceleration and deceleration module and the stepping and direction signals of the distance compensation module, and outputs stepping control and direction control of the motor according to the stepping direction selection signals; and the absolute position module outputs an absolute position based on stepping control and direction control of the motor. A synchronous control function and an absolute position function are added into an existing acceleration and deceleration function, so that a user can freely switch among three modes of acceleration and deceleration, synchronous acceleration and deceleration and distance compensation, an original complex algorithm is realized through a digital circuit, and the working efficiency and the integration degree are improved.

The invention discloses a low-power-consumption dynamic voltage control method and a low-power-consumption dynamic voltage control circuit, the low-power-consumption dynamic voltage control circuit comprises an analog circuit module and a digital circuit module which are arranged in a top module unit of a chip, and the analog circuit module comprises an OSC clock generation circuit which is used for generating a clock required by the digital circuit module. And the digital circuit module digit comprises a low-power-consumption dynamic voltage control circuit. According to the invention, the function of high-dynamic real-time adjustment of the voltage control code with extremely low power consumption is realized through pre-opening and pre-closing of the clock.

The invention belongs to the technical field of semiconductor design automation, and provides a digital circuit engineering correction method and related equipment. The method comprises the following steps: after wiring of a digital circuit is completed, performing static time sequence analysis based on actual circuit resistance-capacitance parasitic parameters of a time sequence path in the digital circuit to obtain global time sequence information of the time sequence path, and screening out an abnormal time sequence path containing an abnormal logic unit from the digital circuit based on the global time sequence information; performing logic unit change on the abnormal time sequence path containing the abnormal logic unit, and performing wiring change on the digital circuit after the logic unit change; and if the wiring violation does not exist in the digital circuit, returning to execute the step of performing the static time sequence analysis based on the actual circuit resistance-capacitance parasitic parameter of each time sequence path in the digital circuit until the abnormal time sequence path does not exist in the digital circuit. According to the technical scheme provided by the invention, the correction efficiency of the digital circuit engineering can be improved.

The invention discloses a stimulation generation circuit for a nerve stimulator, and relates to the technical field of integrated circuits, and the circuit comprises a digital circuit which is used for generating a control signal of a stimulation waveform containing specific frequency, amplitude, pulse width, interval and number of times; the stimulation current generating circuit is used for generating stimulation current; the stimulation voltage generating circuit is used for generating stimulation voltage; the control signal is used for controlling the conduction duration and the conduction sequence of the switch A, the switch B, the switch C and the switch D, and the output stage circuit generates stimulation currents with different stimulation waveforms; the conduction duration and the conduction sequence of the signal voltage switch, the switch A, the switch B, the switch C, the switch D, the charging switch and the discharging switch are controlled, and the output stage circuit generates stimulation voltages with different stimulation waveforms. According to the invention, the conduction sequence and duration of different switches of the output stage circuit are controlled through the control signal, electrical stimulation of different modes and different waveforms can be realized, and diversified stimulation treatment is realized.

The invention discloses a reciprocity circuit leakage electromagnetic signal single-station detection system and method based on a photoconductive effect, and the system employs the reciprocity characteristic of a circuit as a receiving device, and measures the scattered signal of a leakage electromagnetic signal by a plasma formed by the photoconductive effect of a semiconductor material. The leakage electromagnetic vector signal measuring device comprises a light source module, a semiconductor chip, a signal receiving and transmitting module and an upper control module. According to the method, interference of a non-uniform probe on a field is avoided, a mechanical scanning mode is replaced by an optical scanning mode, the measurement efficiency is greatly improved, the reciprocity characteristic of a circuit is used as a receiving device, dependence on an additional receiving device is eliminated, and therefore the remarkable ultra-wideband measurement capacity is achieved; particularly, a brand-new ultra-wideband and super-resolution measurement means is provided for detection of leakage electromagnetic signals of a radio frequency circuit and a high-speed digital circuit which are low in frequency.

A display driver and a display device including the same are disclosed. The display driver includes a voltage adjustment part that receives a driving voltage from a power supply and outputs a first voltage and a second voltage; a frame memory that receives the first voltage and stores pixel data of input images; a digital circuit part that is driven by receiving the second voltage and includes a memory, a plurality of functional blocks, and a power controller; and a control part that generates a control signal for controlling the driving voltage in response to a signal input from the digital circuit part.

The various implementations described herein include techniques and apparatuses for multi-channel biopotential signal acquisition, biopotential signal pre-processing, and adaptive signal conditioning. In one aspect, an analog frontend circuit includes an instrumentation amplifier (INA) and an analog-to-digital circuit (ADC) in a forward signal path. A digital circuit receives input from the ADC. An adaptive baseline tracking and compensation circuit tracks and compensates moving motion artifact driven changes. A power line interference (PLI) detection and compensation circuit tracks a desired number of PLI harmonics, and magnitude, phase and frequency for the PLI harmonics in real time. A digital-to-analog converter (DAC) circuit combines output of the adaptive baseline tracking and compensation circuit and the PLI detection and compensation circuit to output an analog output. A passive filter receives the analog output and drives an analog compensation signal at an input of the INA.

Circuits and methods are provided that generate a reference signal in a digital loop for controlling a controller in an analog loop. An analog loop circuit receives a reference signal, determines a first error based the reference signal and a sensing signal in multiple sensing signals, and regulates regulate a system output signal of the system based on the first error. A digital loop circuit converts the system output signal into a digital system output signal, determines a second error between the digital system output signal and a digital reference signal received from a device coupled to the system, determines a control signal using the second error, and converts the control signal into the reference signal.