754 results about "Digital circuitry" patented technology

The invention relates to the technical field of circuit design, in particular to a digital circuit simulation design method and system. The method comprises the following steps: identifying a design demand document, performing deep semantic analysis and demand constraint mining, and constructing a demand specification constraint parameter set; performing demand complexity evaluation and multi-level division according to the demand specification constraint parameter set, and constructing a basic circuit architecture design blueprint; circuit routing path planning is carried out according to the basic circuit architecture design blueprint, and a standardized circuit topology network is constructed; performing electric signal propagation simulation on the standardized circuit topology network, and performing global circuit adaptability adjustment to obtain a circuit topology design scheme; and carrying out an extreme condition simulation test based on the circuit topology design scheme, and carrying out comprehensive performance evaluation to obtain a circuit performance evaluation report. By deeply understanding the user demand intention, the circuit layout matched with the user demand is designed, and the overall circuit performance is improved.

The invention provides an artificial intelligence-based interface circuit design method, which comprises the following steps of: S1, acquiring an RTL code for describing a logic structure of a digital circuit, and generating a digital circuit layout according to the RTL code by utilizing a preset neural network model; s2, acquiring a preset process library and design parameters of the analog circuit, and generating an analog circuit layout by using a preset neural network model according to the process library and the design parameters of the analog circuit; and S3, fusing the digital circuit layout and the analog circuit layout by using a preset neural network model to obtain the layout of the interface circuit.

The invention discloses a cluster model acceleration method and device based on an FPGA, and relates to the technical field of model acceleration, and the method comprises the steps: converting a cluster simulation model into a digital circuit structure file, and burning the digital circuit structure file into an FPGA board card; splitting the digital circuit structure file into a plurality of independent calculation modules according to functions; packaging the calculation module into a plurality of IP cores based on the requirements of different individuals in the cluster; in response to input data received in the DDR of the FPGA board card, the hardware state machine triggers all the IP cores to execute corresponding tasks in parallel, and the calculation process of each IP core is controlled by taking a main clock of the FPGA board card as a reference; and each IP core writes the task processing result into a DDR (Double Data Rate) of the FPGA board card, and reads the DDR to obtain a simulation result of the cluster simulation model. The technical problems that an existing model acceleration method is poor in real-time performance and high in economic cost in a large-scale cluster simulation scene are solved, and therefore in the large-scale cluster simulation scene, high real-time performance of simulation can be guaranteed, and the economic cost can be effectively reduced.

The various implementations described herein include techniques and apparatuses for multi-channel biopotential signal acquisition, biopotential signal pre-processing, and adaptive signal conditioning. In one aspect, an analog frontend circuit includes an instrumentation amplifier (INA) and an analog-to-digital circuit (ADC) in a forward signal path. A digital circuit receives input from the ADC. An adaptive baseline tracking and compensation circuit tracks and compensates moving motion artifact driven changes. A power line interference (PLI) detection and compensation circuit tracks a desired number of PLI harmonics, and magnitude, phase and frequency for the PLI harmonics in real time. A digital-to-analog converter (DAC) circuit combines output of the adaptive baseline tracking and compensation circuit and the PLI detection and compensation circuit to output an analog output. A passive filter receives the analog output and drives an analog compensation signal at an input of the INA.

The invention relates to the field of digital circuit experiment teaching, in particular to a digital circuit experiment platform and method applying a multi-modal large model and a medium, and the method comprises the steps: inputting experiment task description, analyzing and extracting structured semantic information, and forming task representation; retrieving a circuit function block from the electronic component knowledge base, constructing a context enhancement cue word, guiding a multi-modal large language model to generate a Verilog HDL code, and outputting the Verilog HDL code after grammar check and function verification; a Yosys tool is used for carrying out logic synthesis on the codes to generate a standard JSON netlist, and then the standard JSON netlist is converted into an SVG-format circuit diagram through a Netlistsvg tool; and an electronic component knowledge base updating mechanism is constructed to realize knowledge cyclic evolution and adaptive enhancement, so that the intelligent level and practical training efficiency of circuit experiment teaching are remarkably improved.

The invention discloses a synchronization unit verification method and device of a digital circuit, equipment and a medium, and relates to the technical field of computers, and the method comprises the steps: embedding an assertion statement rule and an assertion coverage rate evaluation rule in a synchronization unit; the assertion statement rule is used for monitoring the operation state and signal characteristics of the synchronization unit in the data synchronization process, the assertion statement rule is implemented in a parameterization mode to adapt to the function requirements of different circuit units, and the assertion coverage rate evaluation rule is used for counting the execution condition of the assertion statement rule; executing front-end simulation verification of the synchronization unit by utilizing the plurality of test cases, and judging whether a violation condition which is not consistent with the assertion statement rule exists in a case execution result or not: if not, calculating an execution coverage rate of the assertion statement rule based on an assertion coverage rate evaluation rule; and evaluating whether the synchronization unit passes the front-end simulation verification according to the execution coverage rate. According to the method, the possibility of omission of problems due to incomplete verification is reduced, and the execution coverage rate is improved.

The invention provides a digital-analog hybrid simulation method and device.The method comprises the steps that a simulation modeling file is generated according to design information of an analog circuit of a chip, and the simulation modeling file comprises a digital netlist, device library configuration, device mapping configuration, simulation control parameters, simulation signal variables and digital-analog interface conversion rules; and performing digital circuit simulation according to the design information of the digital circuit of the chip and the simulation modeling file, and generating a digital-analog hybrid simulation result of the chip. According to the method provided by the invention, the compatibility between digital-analog hybrid simulation tools can be improved.

The invention provides an automatic frequency locking circuit based on a time-to-voltage converter and a phase-locked loop, and relates to the technical field of phase-locked loops, a first frequency-halving unit and a second frequency-halving unit respectively carry out frequency-halving processing on a reference signal and a frequency division signal of a current comparison period to obtain a first square wave signal and a second square wave signal; the first square wave signal and the second square wave signal are transmitted to the time-to-voltage converter; the time voltage converter comprises a phase generation unit, a first charge pump and a second charge pump, the phase generation unit generates an enable signal according to the first square wave signal and the second square wave signal, and the first charge pump and the second charge pump respond to control of the enable signal and collect single pulse signals from the first square wave signal and the second square wave signal respectively so as to supply power to the input end of the comparator; the comparator compares power supply voltages of the two input ends to achieve frequency comparison of the reference signal and the frequency division signal. And selection in a plurality of phase signals is not needed, and required digital circuit modules are reduced, so that the delay of the reference signal and the frequency division signal in the conversion process is reduced.

The invention provides a test vector construction method, which is used for constructing a test vector set required by a to-be-tested digital circuit, and comprises the following steps: S1, obtaining the to-be-tested digital circuit and a to-be-tested fault list corresponding to the to-be-tested digital circuit, the to-be-tested fault list comprising a plurality of circuit faults; s2, multiple rounds of simplification operation are executed until the number of circuit faults which can be detected by all the obtained test vectors is larger than or equal to a preset threshold value, all the test vectors obtained by each round of simplification operation are stored in a variable-capacity vector pool, the capacity of the vector pool corresponding to each round is a preset multiple of the capacity of the vector pool corresponding to the previous round, and the test vectors are stored in the variable-capacity vector pool; wherein each round of simplification operation comprises a static simplification stage and a dynamic simplification stage, the static simplification stage repeatedly fills a vector pool and reduces the number of test vectors in the vector pool, and the dynamic simplification stage fills a part of the uncertain items in the test vectors with the uncertain items obtained in the static simplification stage as 0 or 1.

The invention belongs to the technical field of semiconductor design automation, and provides a digital circuit wiring method and related equipment. The method comprises the steps that wiring grid parameters of all wiring layers in a digital circuit to be wired are acquired, and grid lines of a wiring grid are used for restraining a wiring track; on the basis of the wiring grid parameters, the digital circuit is divided into a plurality of wiring subareas, and the area size of each wiring layer in each wiring subarea is different; traversing each signal path, and determining an access point for performing wiring indexing on each signal path; based on the access points of the signal paths in the wiring partitions, wiring the signal paths in the wiring partitions in parallel through wiring threads respectively configured for the wiring partitions; and combining the wirings of the signal paths in the wiring partitions to obtain a complete wiring of the digital circuit. According to the technical scheme provided by the invention, the wiring efficiency of the digital circuit can be improved.

A method includes: receiving a circuit design including circuit stages; deriving initial logic conditions for nets in a fanout cone from an input port in accordance with a primordial event; initializing a priority queue of logic transition events with the primordial event; determining a trigger event from the priority queue, the trigger event having a timestamp equal to or earlier than all others in the priority queue and representing a logic transition at an input pin of a current circuit stage; simulating an arc of the circuit design from the input pin of the current circuit stage to an input pin of a fanout circuit stage to generate a propagated event; computing a propagated event timestamp based on: the trigger event timestamp; and a delay associated with the arc; enqueuing the propagated event on the priority queue; and generating a static analysis report based on the propagated event timestamp.

An acceleration sensor circuit is disclosed. The acceleration sensor circuit includes a package; an accelerometer to generate acceleration data samples during a peak tracking window; a sample register, to store the acceleration data samples; an acceleration calculation digital circuit, to calculate an acceleration magnitude sample based on the stored acceleration data samples; a peak register, to store a current peak acceleration value; a sample compare circuit, to compare the acceleration magnitude sample to the current peak acceleration value, where the peak register is configured to replace the current peak acceleration value with the acceleration magnitude sample in response to the sample compare circuit determining that the acceleration magnitude sample is greater than the current peak acceleration value; and a memory, configured to store the current peak acceleration value, and to transmit the current peak acceleration value to an external circuit in response to an end of the peak tracking window.

The invention discloses a digital circuit optimization method and system based on logic clustering. The method comprises the following steps: S1, counting fan-out information of all registers in a circuit netlist; s2, according to the fan-out information of the registers, screening out the registers of which the fan-out quantity is greater than a first preset threshold value and the logic series is greater than a second preset threshold value and which are located on the critical path, and generating a candidate register list; s3, obtaining register fan-out first-level combinatorial logic information; s4, performing clustering operation on the logic units based on the first-level combinational logic information, and dividing physically adjacent logic units into the same cluster according to the physical position relationship of the logic units; s5, associating the clustered logic units together and adjusting the connection relation of the logic units; s6, carrying out equivalence check; and S7, rearranging and wiring the circuit according to the modified netlist. The physical distance of a time sequence path can be effectively reduced, the time sequence performance of the circuit is optimized, and the method is suitable for large-scale integrated circuit design.

The invention discloses a digital circuit design method and device, equipment and a medium, and relates to the technical field of digital circuits, and the method comprises the steps: determining a target type of a to-be-designed digital circuit, and collecting a first training set corresponding to the target type; each training sample in the first training set comprises an input feature item used for designing a target type of historical digital circuit and the actual result quality of the historical digital circuit, and the input feature item comprises a high-level language source code and an HLS constraint parameter; constructing an initial prediction model based on the multi-layer perceptron mixed structure, training the initial prediction model by using the first training set, and searching and optimizing the model architecture based on the network structure to obtain a target prediction model; and predicting the actual result quality corresponding to each parameter combination in a target design space of a to-be-designed digital circuit by using the model, and designing the digital circuit by using the parameter combination of which the quality meets the Pareto frontier. And predicting an accurate actual quality result by utilizing a prediction model without intermediate representation so as to carry out digital circuit design.

The invention discloses a motor control digital circuit and a driving system, and the circuit comprises a first delay time sequence module which transmits a secondary delay pulse to an acceleration and deceleration synchronization module based on a synchronization signal and delay time; the acceleration and deceleration synchronization module obtains path input after receiving the secondary delay pulse, and selects acceleration and deceleration path write-in and acceleration and deceleration position write-in sent to the acceleration and deceleration module; the stepping direction selection module receives the stepping and direction signals of the acceleration and deceleration module and the stepping and direction signals of the distance compensation module, and outputs stepping control and direction control of the motor according to the stepping direction selection signals; and the absolute position module outputs an absolute position based on stepping control and direction control of the motor. A synchronous control function and an absolute position function are added into an existing acceleration and deceleration function, so that a user can freely switch among three modes of acceleration and deceleration, synchronous acceleration and deceleration and distance compensation, an original complex algorithm is realized through a digital circuit, and the working efficiency and the integration degree are improved.

The invention discloses a low-power-consumption dynamic voltage control method and a low-power-consumption dynamic voltage control circuit, the low-power-consumption dynamic voltage control circuit comprises an analog circuit module and a digital circuit module which are arranged in a top module unit of a chip, and the analog circuit module comprises an OSC clock generation circuit which is used for generating a clock required by the digital circuit module. And the digital circuit module digit comprises a low-power-consumption dynamic voltage control circuit. According to the invention, the function of high-dynamic real-time adjustment of the voltage control code with extremely low power consumption is realized through pre-opening and pre-closing of the clock.

The invention belongs to the technical field of semiconductor design automation, and provides a digital circuit engineering correction method and related equipment. The method comprises the following steps: after wiring of a digital circuit is completed, performing static time sequence analysis based on actual circuit resistance-capacitance parasitic parameters of a time sequence path in the digital circuit to obtain global time sequence information of the time sequence path, and screening out an abnormal time sequence path containing an abnormal logic unit from the digital circuit based on the global time sequence information; performing logic unit change on the abnormal time sequence path containing the abnormal logic unit, and performing wiring change on the digital circuit after the logic unit change; and if the wiring violation does not exist in the digital circuit, returning to execute the step of performing the static time sequence analysis based on the actual circuit resistance-capacitance parasitic parameter of each time sequence path in the digital circuit until the abnormal time sequence path does not exist in the digital circuit. According to the technical scheme provided by the invention, the correction efficiency of the digital circuit engineering can be improved.

A display driver and a display device including the same are disclosed. The display driver includes a voltage adjustment part that receives a driving voltage from a power supply and outputs a first voltage and a second voltage; a frame memory that receives the first voltage and stores pixel data of input images; a digital circuit part that is driven by receiving the second voltage and includes a memory, a plurality of functional blocks, and a power controller; and a control part that generates a control signal for controlling the driving voltage in response to a signal input from the digital circuit part.

The various implementations described herein include techniques and apparatuses for multi-channel biopotential signal acquisition, biopotential signal pre-processing, and adaptive signal conditioning. In one aspect, an analog frontend circuit includes an instrumentation amplifier (INA) and an analog-to-digital circuit (ADC) in a forward signal path. A digital circuit receives input from the ADC. An adaptive baseline tracking and compensation circuit tracks and compensates moving motion artifact driven changes. A power line interference (PLI) detection and compensation circuit tracks a desired number of PLI harmonics, and magnitude, phase and frequency for the PLI harmonics in real time. A digital-to-analog converter (DAC) circuit combines output of the adaptive baseline tracking and compensation circuit and the PLI detection and compensation circuit to output an analog output. A passive filter receives the analog output and drives an analog compensation signal at an input of the INA.

Circuits and methods are provided that generate a reference signal in a digital loop for controlling a controller in an analog loop. An analog loop circuit receives a reference signal, determines a first error based the reference signal and a sensing signal in multiple sensing signals, and regulates regulate a system output signal of the system based on the first error. A digital loop circuit converts the system output signal into a digital system output signal, determines a second error between the digital system output signal and a digital reference signal received from a device coupled to the system, determines a control signal using the second error, and converts the control signal into the reference signal.

The invention discloses a clock processing method and device, electronic equipment, a storage medium and a program product, and relates to the technical field of communication, and the method comprises the steps: building a cross-domain clock based on a main clock in a digital circuit; setting a first delay constraint for the cross-domain clock based on a preset delay threshold; the Gray code path is determined in the time sequence path corresponding to the cross-domain clock, and the first delay constraint is adjusted based on the clock frequency of the cross-domain clock to obtain the second delay constraint, so that the problems that the requirements of different types of time sequence paths on path constraints are often different, and if the constraints are not distinguished when the time sequence paths are designed, the time sequence paths cannot be designed are solved. The technical problem that the power consumption of the digital circuit is increased due to the fact that a design tool may add more buffers on a path or enhance the driving capability of the buffers is solved, and the technical effect of reducing the power consumption of the digital circuit to a certain extent on the premise of ensuring the time sequence requirement of the cross-clock domain is achieved.

The present disclosure relates to a computing-in-memory chip architecture, a packaging method for a computing-in-memory chip, and an apparatus. The computing-in-memory chip architecture includes: one or more first chips each integrated with one or more arrays of computing-in-memory cells of the computing-in-memory chip that are used to compute the received data; a second chip integrated with a peripheral analog circuit IP core and a digital circuit IP core of the computing-in-memory chip; an interposer between the one or more first chips and the second chip; and an interface module configured to communicatively couple the second chip to each first chip via the interposer, where the interface module includes one or more sub-interface modules on each first chip and aligned with each other, and where the interposer includes a first portion aligned with the one or more sub-interface modules on each first chip, and a second portion configured to arrange a communication path between the second chip and each first chip.

A computing-in-memory system, a packaging method for a computing-in-memory system, and an apparatus are provided. The computing-in-memory system includes: one or more first sub-chips integrated on a first side of a computing-in-memory chip, each of the one or more first sub-chips including one or more arrays of computing-in-memory cells of the computing-in-memory system, where the one or more arrays of computing-in-memory cells are configured to perform computations on received data; a second sub-chip integrated on a second side, opposite to the first side, of the computing-in-memory chip, the second sub-chip including a peripheral analog circuit IP core and a digital circuit IP core of the computing-in-memory chip; and an interface module configured to communicatively couple the second sub-chip to each of the one or more first sub-chips.

The invention relates to a knitting machine and particularly relates to a controller for a yarn changer. The controller comprises a controller skeleton arranged on an outer plate of a yarn changer main body, a transfer bar, a digital circuit and a drive mechanism for driving the transfer bar to carry out linear motion, wherein the transfer bar is connected with the controller skeleton in a sliding manner; the transfer bar drives a yarn clamping and shearing device of the yarn changer to complete yarn selecting and yarn guiding actions while carrying out linear motion; the digital circuit and the drive mechanism are arranged on the controller skeleton separately; and the digital circuit is electrically connected with a drive mechanism. External drive is not needed, and the drive mechanism can be controlled to drive the transfer bar to carry out linear motion by virtue of the digital circuit, so that the transfer bar drives the yarn clamping and shearing device to complete the yarn selecting and yarn guiding actions, and independent control on yarn selecting and yarn guiding of the yarn changer is achieved; and the controller is small in impact vibration, high in applicability, stable in working, simple in structure and beneficial to improvement of the production stability of the knitting machine.

The invention provides an assertion-based clock reset verification method, device and equipment and a storage medium, relates to the technical field of signal verification, is applied to a digital circuit, and comprises the following steps: obtaining an input signal generated by an excitation source; the input signal comprises at least one of a clock signal and a reset signal; determining an assertion execution sequence based on the input signal and a preset assertion priority; performing signal verification on the input signal based on a preset assertion statement according to the assertion execution sequence; wherein the assertion statements comprise a clock signal frequency assertion statement, a clock signal duty ratio assertion statement, a clock signal jitter assertion statement, a reset signal validity assertion statement and a reset signal release assertion statement. In the mode, the requirement of a modern complex digital circuit on efficient and accurate verification of the clock signal and the reset signal is met.

A computing-in-memory system, a packaging method for a computing-in-memory system, and an apparatus are provided. The computing-in-memory system includes: one or more first chips that each include one or more arrays of computing-in-memory cells that are configured to perform computations on received data; a second chip that includes a peripheral analog circuit IP core and a digital circuit IP core; an interposer positioned between the one or more first chips and the second chip; and an interface module configured to communicatively couple the second chip to each first chip via the interposer. The interface module includes one or more sub-interface modules on each first chip, where the sub-interface modules are aligned with each other. The interposer includes a first portion aligned with the sub-interface modules on the one or more first chips and a second portion configured to arrange a communication path between the second chip and each first chip.

The invention discloses a data processing method and device, equipment, a storage medium and a product, the method is applied to integrated circuit electronic design automation software, and the method comprises the following steps: obtaining a digital circuit design file; analyzing the digital circuit design file to generate a corresponding netlist data structure; responding to an object query request sent by a user, accessing the netlist data structure, and searching a data item matched with a target query object specified by the user in the netlist data structure; based on the data item matched with the target query object specified by the user and found in the netlist data structure, the object query result is generated, the netlist data structure is adopted as a data processing basis for object query, hierarchical recursive traversal does not need to be carried out, branch relations among multi-way tree nodes do not need to be processed, and the data query efficiency is improved. And the query efficiency is obviously improved.

The invention discloses a digital circuit dependency analysis method, which comprises the following steps of: by analyzing the equality of a Boolean differential circuit, converting a dependency judgment problem of D on S into a problem of judging whether the Boolean differential circuit is constantly 0 or not; when whether the Boolean differential circuit is constantly 0 cannot be judged through X value simulation, logic negation is performed on the Boolean differential circuit, so that a dependency judgment problem is formally converted into a satisfiability problem, SAT solving is performed on the problem, whether D depends on S or not is judged according to a solving result, and if not, the Boolean differential circuit is judged to be zero. If the Boolean differential circuit is constrained, the satisfiability problem of the Boolean differential circuit is reconstructed, and the constrained Boolean differential circuit is subjected to SAT solution to further determine the dependency. According to the method, the digital circuit dependency analysis efficiency and accuracy are remarkably improved, the method is suitable for combinational logic circuit scenes of any scale and any complexity, the application range and efficiency of engineering application are greatly improved, and the method has remarkable industrial application value and popularization prospects.

According to an embodiment, a biopotential measurement system includes an analog front-end and digital circuits. The analog front-end circuit includes a sensing electrode, a forward amplifier, and a feedback amplifier with an integration capacitor. A feature is the attenuation circuit between the forward and feedback amplifiers, which provides an attenuation factor determining the integration capacitor's value for achieving the desired high-pass corner frequency. With configurable attenuation factors, the system can process different biopotential signals. Multiple analog front-end circuits can be used to process different signals simultaneously. The digital circuit includes a processor for signal processing, dynamic adjustment of attenuation factors, and anomaly detection. Additional components like switched capacitors, pseudo-resistors, and multiplexers can enhance the system's functionality. The design allows flexible, multi-parameter physiological monitoring with adjustable frequency responses and gain settings.

The embodiment of the invention is suitable for the technical field of digital circuits, and provides a circuit analysis method and device, electronic equipment and a computer program product, and the method comprises the steps: obtaining description information of a to-be-analyzed circuit in different description modes; the description information in different description modes at least comprises a function abstract corresponding to a text description mode, a circuit diagram corresponding to a graphic description mode and a hardware description language corresponding to a programming language description mode; performing feature fusion on the single-mode features obtained based on the description information to generate fusion features of the circuit to be analyzed; inputting the fusion features into an analysis model, and generating an analysis result corresponding to the circuit to be analyzed; the analysis result corresponding to the analysis circuit comprises a correlation circuit corresponding to the to-be-analyzed circuit and / or a prediction index corresponding to the to-be-analyzed circuit. According to the method provided by the embodiment of the invention, the circuit to be analyzed can be analyzed according to the characteristics under various description information, so that the analysis accuracy of the circuit is improved.