279 results about "Digital circuitry" patented technology

The invention provides a test vector construction method, which is used for constructing a test vector set required by a to-be-tested digital circuit, and comprises the following steps: S1, obtaining the to-be-tested digital circuit and a to-be-tested fault list corresponding to the to-be-tested digital circuit, the to-be-tested fault list comprising a plurality of circuit faults; s2, multiple rounds of simplification operation are executed until the number of circuit faults which can be detected by all the obtained test vectors is larger than or equal to a preset threshold value, all the test vectors obtained by each round of simplification operation are stored in a variable-capacity vector pool, the capacity of the vector pool corresponding to each round is a preset multiple of the capacity of the vector pool corresponding to the previous round, and the test vectors are stored in the variable-capacity vector pool; wherein each round of simplification operation comprises a static simplification stage and a dynamic simplification stage, the static simplification stage repeatedly fills a vector pool and reduces the number of test vectors in the vector pool, and the dynamic simplification stage fills a part of the uncertain items in the test vectors with the uncertain items obtained in the static simplification stage as 0 or 1.

The invention discloses a digital circuit design method and device, equipment and a medium, and relates to the technical field of digital circuits, and the method comprises the steps: determining a target type of a to-be-designed digital circuit, and collecting a first training set corresponding to the target type; each training sample in the first training set comprises an input feature item used for designing a target type of historical digital circuit and the actual result quality of the historical digital circuit, and the input feature item comprises a high-level language source code and an HLS constraint parameter; constructing an initial prediction model based on the multi-layer perceptron mixed structure, training the initial prediction model by using the first training set, and searching and optimizing the model architecture based on the network structure to obtain a target prediction model; and predicting the actual result quality corresponding to each parameter combination in a target design space of a to-be-designed digital circuit by using the model, and designing the digital circuit by using the parameter combination of which the quality meets the Pareto frontier. And predicting an accurate actual quality result by utilizing a prediction model without intermediate representation so as to carry out digital circuit design.

The invention relates to a knitting machine and particularly relates to a controller for a yarn changer. The controller comprises a controller skeleton arranged on an outer plate of a yarn changer main body, a transfer bar, a digital circuit and a drive mechanism for driving the transfer bar to carry out linear motion, wherein the transfer bar is connected with the controller skeleton in a sliding manner; the transfer bar drives a yarn clamping and shearing device of the yarn changer to complete yarn selecting and yarn guiding actions while carrying out linear motion; the digital circuit and the drive mechanism are arranged on the controller skeleton separately; and the digital circuit is electrically connected with a drive mechanism. External drive is not needed, and the drive mechanism can be controlled to drive the transfer bar to carry out linear motion by virtue of the digital circuit, so that the transfer bar drives the yarn clamping and shearing device to complete the yarn selecting and yarn guiding actions, and independent control on yarn selecting and yarn guiding of the yarn changer is achieved; and the controller is small in impact vibration, high in applicability, stable in working, simple in structure and beneficial to improvement of the production stability of the knitting machine.

The invention discloses a digital circuit dependency analysis method, which comprises the following steps of: by analyzing the equality of a Boolean differential circuit, converting a dependency judgment problem of D on S into a problem of judging whether the Boolean differential circuit is constantly 0 or not; when whether the Boolean differential circuit is constantly 0 cannot be judged through X value simulation, logic negation is performed on the Boolean differential circuit, so that a dependency judgment problem is formally converted into a satisfiability problem, SAT solving is performed on the problem, whether D depends on S or not is judged according to a solving result, and if not, the Boolean differential circuit is judged to be zero. If the Boolean differential circuit is constrained, the satisfiability problem of the Boolean differential circuit is reconstructed, and the constrained Boolean differential circuit is subjected to SAT solution to further determine the dependency. According to the method, the digital circuit dependency analysis efficiency and accuracy are remarkably improved, the method is suitable for combinational logic circuit scenes of any scale and any complexity, the application range and efficiency of engineering application are greatly improved, and the method has remarkable industrial application value and popularization prospects.

According to an embodiment, a biopotential measurement system includes an analog front-end and digital circuits. The analog front-end circuit includes a sensing electrode, a forward amplifier, and a feedback amplifier with an integration capacitor. A feature is the attenuation circuit between the forward and feedback amplifiers, which provides an attenuation factor determining the integration capacitor's value for achieving the desired high-pass corner frequency. With configurable attenuation factors, the system can process different biopotential signals. Multiple analog front-end circuits can be used to process different signals simultaneously. The digital circuit includes a processor for signal processing, dynamic adjustment of attenuation factors, and anomaly detection. Additional components like switched capacitors, pseudo-resistors, and multiplexers can enhance the system's functionality. The design allows flexible, multi-parameter physiological monitoring with adjustable frequency responses and gain settings.

The invention discloses an all-digital PVT sensor based on a ring oscillator, and relates to the field of PVT sensors, the all-digital PVT sensor comprises a process sensing circuit, a voltage sensing circuit and a temperature sensing circuit, the process sensing circuit comprises a process detection ring oscillator, the voltage sensing circuit comprises a voltage detection ring oscillator, and the temperature sensing circuit comprises a temperature detection ring oscillator. The temperature sensing circuit comprises a temperature sensitive ring oscillator; under the control of an enable signal, the process detection ring oscillator, the voltage detection ring oscillator and the temperature-sensitive ring oscillator start oscillation, and the process corner, the temperature and the power supply voltage of the detected chip are determined based on the oscillation frequencies of the process detection ring oscillator, the voltage detection ring oscillator and the temperature-sensitive ring oscillator. The PVT sensor is completely realized based on a digital circuit, an additional analog module does not need to be introduced, the area overhead is greatly reduced, and the PVT sensor has remarkable area advantage and structural simplicity while the high-precision detection capability is maintained.

Injection molding machine (10), comprising: a mold closing / clamping motor (160) that moves a mold closing / clamping unit (100) to perform mold closing / clamping of a mold unit (800); a drive unit (721) that supplies power to the form-closing / clamping motor (160); a changeover switch (730) provided in a wire (722) connecting the mold closing / clamping motor (160) and the drive unit (721), which is capable of switching between supplying and stopping the current from the drive unit (721) to the mold closing / clamping motor (160), and which is capable of switching between not activating a brake of the mold closing / clamping motor (160) and activating the brake; and a digital circuit (711) connected to the changeover switch (730) and controlling the changeover switch (730), wherein the digital circuit (711) controls the changeover switch (730) based on the detection of a trigger signal to stop the mold closing / clamping motor (160) in order to perform the feed stop and activation of the brake, the digital circuit (711) controls the feed stop of the switch (730) and the activation of the brake after waiting for a waiting period that is set from the time at which the trigger signal is detected, and The waiting time is set to be equal to or longer than the time in which pressure relief is completed from a state in which the forming unit (800) is pressed by the forming closing / clamping unit (100).

The invention belongs to the technical field of digital circuits, and discloses a ubiquitous metering-oriented adaptive AC / DC wide-range electric energy metering system and method, and the system comprises a PGA, an ADC, a waveform extreme point judgment module, a PGA multiple calculation module and a two-dimensional AC / DC recognition module. Quantized burrs are inhibited; the PGA gain is dynamically adjusted based on the effective bit width occupancy rate, so that the signal amplitude is adaptively matched with the optimal range of the ADC; the frequency and amplitude features are combined to construct two-dimensional recognition logic, and alternating current and direct current signals are accurately distinguished; and a cooperative feedback mechanism of gain adjustment and AC / DC identification is established, and differential power calculation is realized. The method solves the problems that a traditional scheme is rigid in gain configuration, low in extreme value extraction precision, high in alternating current and direct current misjudgment rate and poor in system collaboration, and has the advantages of being high in self-adaption, accurate in recognition, good in real-time performance and flexible in scene adaptation.

The integrated circuit includes a delay monitor that monitors a delay of the data signal from the digital circuitry by generating a pulse having a width determined by the delay. In some embodiments, a delay monitor is implemented as a digital circuit that includes a pulse generator and an event generator. The delay monitor receives a data signal and a clock signal for clocking the data signal. The pulse generator generates a pulse according to the received data signal and the clock signal, wherein a width of the pulse is determined by a delay of the data signal relative to the clock signal. The event generator generates events that are temporally distributed with respect to the clock signal. As a result, the delay may be estimated based on an overlap between the event and the pulse.

The utility model discloses an industrial control board based on STM32F103 singlechip, it includes main control chip, RS 485 level conversion circuit, digital I / O circuit and LED pilot lamp, and RS 485 circuit realizes efficient level conversion through three stage anti -interference framework magnetic pearl filtering, photo -coupler isolation, TVS protection, and digital I / O circuit adopts photo -coupler and isolation amplifier to enhance signal stability, and is equipped with LED pilot lamp feedback state, and the application effectively reduces the code rate less than 10 ‑7 , reduces signal dithering, and the temperature drift attenuation is only 2.1%, is suitable for industrial automation and intelligent manufacturing system, has simple structure, low in cost, stable performance and the advantages such as.

The application discloses a composite channel structure high electron mobility transistor and a preparation method thereof, and the transistor comprises a semi-insulating InP substrate, an undoped InAlAs buffer layer, an InP auxiliary channel, a first undoped In 0.22 Ga 0.78 As auxiliary channel, an undoped In 0.7 Ga 0.3 As main channel, a second undoped In 0.22 Ga 0.78 As auxiliary channel, an undoped InAlAs isolation layer, a delta-doping layer, an undoped InAlAs barrier layer, an n + InGaAs source cap layer, an n + InGaAs drain cap layer, a source electrode, a drain electrode, a passivation layer and a gate electrode. The application can improve the breakdown voltage of the InP-based HEMT, maintain the output characteristics and cutoff frequency of the high In-component channel, improve the stability of transistor uniformity and repeatability, and meet the application requirements of the InP-based electronic device in the low-power low-noise and digital circuit field.

The invention relates to a signal probability calculation method for reducing correlation errors of digital circuit signals, which comprises the following steps of: acquiring a circuit netlist file, and analyzing and extracting circuit topological structure information; constructing a directed acyclic graph of a circuit structure according to the circuit topological structure information, performing hierarchical division on the circuit structure, and searching fan-out nodes; calculating an initial signal probability result of each node of each level by utilizing a directed acyclic graph and combining a signal probability calculation basic formula; calculating a signal probability result of each node when different signal probabilities are set at the fan-out node, and performing weighted calculation to obtain a weighted signal probability result of each node; calculating an initial correction signal probability result of each node of each level; counting an initial signal probability result, a weighted signal probability result and an initial correction signal probability result, and calculating a final signal probability result of each node of the circuit in combination with an inference rule and a statistical result. According to the method, the accurate signal probability result of each unit of the circuit can be calculated.

The invention discloses a method and device for improving the reuse rate of a hardening module of a digital circuit and optimizing the time sequence, power consumption and area, and the method comprises the following steps: determining the instantiation times of the hardening module to be optimized, and calculating and determining the bit width w of a coding input signal; creating a new module, removing all instantiated parameters and constant value input ports, and adding a coding input port; creating a temporary variable in the new module; establishing a mapping relation in the new module; instantiating the original module internally by using the temporary variable; all original instances are re-instantiated using a new module, and the encoded value is assigned to the encoding input port. The optimization method provided by the invention is simple in steps, and not only can perform coding optimization on input parameters and constant values on the boundary of the hardened module by adopting a minimum bit width binary coding mode according to the multiplexing times of the hardened module on the premise of ensuring the logic equivalence of a digital circuit, but also can perform coding optimization on the input parameters and constant values on the boundary of the hardened module. And the time sequence, the power consumption and the area in the hardening module can be optimized to the greatest extent.

A driving assembly management system, a fault detection method, and an electric power-assisted bicycle. The driving assembly management system comprises: an Internet-of-things device, multiple digital assemblies, and a bus; each digital assembly comprises: a driving assembly and a digital circuit connected to the driving assembly; the digital circuit comprises: an assembly signal processing circuit, a first processor, and a first memory; an input end of the assembly signal processing circuit is connected to a signal acquisition end of the driving assembly; the first processor is further connected to the assembly signal processing circuit; the first memory is connected to the first processor; and the Internet-of-things device is communicatively connected to the first processor in the multiple digital assemblies, so as to perform fault detection according to working state data and identification information of the multiple digital assemblies.

An embodiment method of forming a layout plan of an integrated circuit (IC) device includes obtaining a placement of a plurality of digital circuit cells in a region of a layout plan; obtaining an initial placement of one or more thermal sensing resistor cells in a subset of a plurality of metallization layers and a subset of a plurality of via layers of the layout plan; obtaining a routing plan based on a clock tree synthesis and the initial placement of the one or more thermal sensing resistor cells; performing a thermal analysis based on the placement of the plurality of digital circuit cells and the routing plan to identify one or more areas of interest in the region of the layout plan; and obtaining a refined placement of the one or more thermal sensing resistor cells respectively over the one or more areas of interest.

According to various embodiments of the present invention, a regression analysis-based circuit characteristic optimization device for digital circuit design may: receive, from the outside, information about a digital circuit to be designed, and arbitrarily set a characteristic value for at least one transistor included in the digital circuit; generate a circuit characteristic regression model by mathematically modeling the characteristic of a path included in the digital circuit on the basis of the characteristic value of the transistor included in the digital circuit; obtain an initial coefficient of the circuit characteristic regression model by applying the arbitrarily set characteristic value thereto; and obtain the improved characteristic value for the at least one transistor included in the digital circuit on the basis of the circuit characteristic regression model into which the initial coefficient has been incorporated.

The application discloses an aging-aware precision reconfigurable logic synthesis method and system, and belongs to the technical field of integrated circuit EDA. The application aims to solve the problems of limited optimization space, introduced error from the beginning and lack of aging modeling in the existing aging-aware synthesis. The application constructs an aging standard cell library, iteratively applies constant replacement to the original circuit to generate multiple approximate candidate circuits, and then constructs a precision reconfigurable circuit composed of reconfigurable modules, which dynamically switches between accurate mode and approximate mode. Through aging-aware timing modeling, a power function model of gate delay with running time is established, and the aging continuity during mode switching is processed. The accurate mode life and the approximate mode remaining life are predicted, and the circuit with the highest score is automatically selected according to the score function. The application can improve the circuit life by about 9.5 times with an additional area overhead of about 3.72% under the premise of meeting the error constraint, which significantly enhances the long-term reliability of digital circuits.

The application is a QUBO problem solving method based on analog computing circuit, belonging to the field of analog computing and integrated circuit.The method combines the mathematical mapping of QUBO problem with the physical evolution process of analog computing circuit, maps the quadratic term matrix in QUBO problem into the product of resistance value in programmable resistance memory array and output current of current source module, maps the linear coefficient vector into threshold voltage of each row comparator, and takes the output voltage of each row comparator on feedback loop as the output of corresponding logic of state variable to be solved in QUBO problem, and relies on the natural evolution process of voltage in the circuit to realize the solution of QUBO problem in one step.The application does not depend on external digital circuit to provide clock, but updates in continuous time, has the advantages of fast speed, less peripheral circuit and low power consumption, and is suitable for the application scene of QUBO problem which is sensitive to power consumption and requires high solving speed.

This invention discloses an integrated navigation transmitter assembly based on digital multi-beam technology, belonging to the field of phased array technology. It includes a lower panel, a transmitter terminal, an up-converter, a power amplifier, a receiver-resistance filter, and a upper panel. This invention adopts an integrated design, combining the transmitter terminal, up-converter, power amplifier, and receiver-resistance filter into a single assembly, resulting in a compact structure and convenient installation and maintenance. It employs a decentralized design, distributing signal generation functions to each transmitter assembly, achieving beam delay, phase, and amplitude control in the digital domain. Compared to traditional analog TR assemblies, this provides higher control precision and more flexible beam pointing. Furthermore, this invention utilizes modular shielding technology, placing digital circuits, analog circuits, and high-power equipment in independent metal shielding cavities, significantly reducing signal leakage and solving the problem of electromagnetic interference between assemblies in large-scale array deployments. This invention has good versatility, allowing adjustment of the transmitted signal waveform and frequency as needed.

The invention relates to the field of digital circuit design, and provides a method for optimizing noise influence of a synchronous switch in an IBIS model. When a traditional IBIS model measures pull-up / pull-down characteristics, it is assumed that a power supply and ground potential are constant, voltage fluctuation actually caused by a synchronous switch is ignored, and the simulation precision of a high-speed interface is reduced. By collecting current response data of a pull-up circuit and a pull-down circuit of the buffer under different power supply / ground fluctuations, pull-up and pull-down power supply modulation coefficients are calculated respectively, and the influence of power supply voltage disturbance on output current is represented. In the simulation stage, the output current in the IBIS model is dynamically modulated according to the power supply and ground potential change caused by the real-time SSN, so that the simulation is closer to the real chip behavior. The method does not need to modify a model structure, is compatible with an existing process, remarkably improves the accuracy of high-speed signal integrity analysis, is suitable for design verification of DDR, PCIe and other high-density parallel interfaces, and effectively supports the system-level power supply and signal co-simulation requirements.

The present application relates to the technical field of digital circuit control, and particularly relates to a contact state monitoring and control method of a direct current contactor. The method comprises the following steps: monitoring the contact state of the direct current contactor and collecting the driving code signal of the direct current contactor, and extracting the characteristic code after filtering; performing spiral hierarchical identification on the characteristic code, analyzing the hierarchical information to distinguish the driving instruction, and obtaining the characteristic code identification result; distributing the characteristic code identification result to the corresponding driving circuit; outputting the rated driving voltage to the corresponding direct current contactor coil according to the characteristic code identification result, driving the coil to attract the armature, and closing the contact of the direct current contactor. The present application realizes fine management and control and abnormal processing of the direct current contactor by combining filtering and spiral hierarchical coding identification, and improves the instruction execution accuracy and the control whole-process stability.

The application belongs to the technical field of low power consumption, and particularly relates to a low power consumption design method and device with adaptive voltage regulation. The method comprises the following steps: 1) simulating a key path of an analog-digital circuit, wherein the key path refers to a path with the maximum delay in the digital circuit; 2) generating a test clock signal and a sampling clock signal, and inputting the generated test clock signal into the key path; 3) detecting the output signal of the key path by using the sampling clock signal with the same sampling time and / or different sampling times, and controlling and adjusting the power supply voltage of the digital circuit according to the detection result, so as to determine the minimum power consumption voltage for ensuring the normal operation of the digital circuit. The application uses the key path to represent a complex load, and has simple structure and wide application range. The power supply voltage of the circuit is controlled and adjusted according to the voltage detection result, so that the control precision and the adjustment efficiency are improved, the minimum voltage for ensuring the normal operation of the circuit is determined, and energy saving is achieved.

The invention belongs to the technical field of control circuits, and particularly relates to a threshold current control circuit for a PSI5 interface. According to the circuit, the positive input end of an operational amplifier is connected with the drain electrode of an NMOS tube M1 and one end of a resistor R2, the negative input end of the operational amplifier is connected with one end of a resistor R1, and the output end of the operational amplifier is connected with the grid electrode of the NMOS tube M1; the source electrode of the NMOS tube M1 is connected with the drain electrode of the NMOS tube M2, the grid electrode of the NMOS tube M2 and one end of the resistor R4, and the source electrode of the NMOS tube M2 is grounded; the other end of the resistor R4 is connected with one end of a capacitor C1 and a grid electrode of the NMOS tube M3, and the other end of the capacitor C1 is grounded; the drain electrode of the NMOS tube M3 is connected with one end of the resistor R3, and the source electrode of the NMOS tube M3 is grounded; the other ends of the resistors R1, R2 and R3 are connected with a power supply; according to the invention, the threshold current control of the PSI5 interface is realized without depending on the feedback control of a digital circuit.

The invention discloses an all-digital fractional frequency division phase-locked loop based on high-level synthesis and an implementation method thereof, and the phase-locked loop comprises a time-to-digital converter which is implemented based on a register transmission stage and is used for outputting a phase error signal according to an externally input reference clock signal and a feedback clock signal input by a feedback frequency divider; the digital loop filter is realized based on high-level integration and is used for outputting a frequency control word according to the phase error signal; the numerical control oscillator is realized based on the IP core and is used for outputting a digital sine wave signal according to the frequency control word; and the feedback frequency divider is realized based on high-level integration and is used for outputting a feedback clock signal according to the digital sine wave signal. According to the all-digital phase-locked loop, the modules in the all-digital phase-locked loop are strategically divided, high-level synthesis and register transfer level design are strategically combined, the all-digital phase-locked loop which is high in performance and efficiency and can be stably locked is achieved, and the all-digital phase-locked loop can be widely applied to the technical field of digital circuit design.

Systems and methods are disclosed that monitor for supply noise from a power source using a voltage noise monitor (VNM). For instance, the VNM may include voltage sense circuitry comprising a controllable resistor that is controlled using threshold information. The resistance of the controllable resistor may be changed based on closing and / or opening one or more switches associated with step resistors using the bits from the threshold information. Furthermore, the VNM may include digital circuitry that comprises a hold finite state machine and a sticky hold counter. Using the digital circuitry, the VNM may be configured to hold a noise detection event for a plurality of clock cycles. In addition, the VNM may perform a calibration process based on setting two voltages for the power source to obtain two codes, and determining a transfer function based on the two voltages and the two codes.

The invention discloses an electric leakage optimization method of a digital chip and electronic equipment, and belongs to the technical field of design and manufacturing of integrated circuits, and the electric leakage optimization method of the digital chip comprises the steps: obtaining initial threshold voltage types of all optimizable standard units in a digital circuit and an optimizable threshold voltage type list, obtaining an initial constraint violation report of the digital circuit; the threshold voltage type of each optimizable standard unit is optimized into the highest threshold voltage type in the optimizable threshold voltage list of the optimizable standard unit; and according to the constraint violation report of the optimized digital circuit, taking the initial threshold voltage type of the optimizable standard unit as a constraint, and carrying out threshold voltage type sequential rollback on the optimizable standard unit related to the violation until the constraint violation report of the digital circuit has no newly added violation compared with the initial constraint violation report. Through the electric leakage optimization method of the digital chip disclosed by the invention, the problem of electric leakage optimization judgment benchmark in chip design can be solved.

The application provides a gyro vibration displacement detection device and method, which comprises generation of high-frequency bipolar square wave, modulation of gyro vibration displacement, amplification of signals and demodulation of gyro vibration displacement signals, and is implemented through corresponding circuit modules. The application modulates the gyro vibration displacement signals to a carrier frequency higher than the gyro resonance frequency, avoids the influence of circuit noise and environmental noise on the gyro displacement detection precision and the crosstalk problem of the driving signal through the parasitic capacitance, and avoids the defects of complex circuit, high cost and the like caused by the high-frequency sine wave as the carrier, has the characteristics of low implementation circuit price, less digital circuit resource occupation, simple carrier generation circuit, no need of filter for extracting the gyro vibration displacement, and is suitable for high-performance Coriolis vibration gyro and other vibration body high-precision vibration displacement detection.

The invention discloses a low-cost gallium nitride power tube current detection and protection device, which comprises a voltage conversion module, a current detection and amplification circuit, an overcurrent comparison module, a fault latch circuit and an MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) switching circuit, when gallium nitride power current is too large, the current is subjected to detection, amplification, comparison and fault latch, and the MOSFET switching circuit is turned off, so that the gallium nitride power tube is protected. According to the scheme, a digital circuit is not depended on, the adopted devices are simple and low in cost, the whole device is not prone to electromagnetic interference and high in reliability, and the requirement for high-voltage protection of the drain electrode can be met.

The application discloses a timing constraint checking method and device and electronic equipment, and belongs to the technical field of computer data. The method comprises the following steps: acquiring structural information used for representing a connection relationship of a digital circuit and constraint information used for representing a timing constraint rule; acquiring at least one unconstrained path from the structural information based on the constraint information; performing feature extraction on the unconstrained path to obtain path feature information; and obtaining timing anomaly information corresponding to the path feature information based on the path feature information. According to the application, the unconstrained path is automatically identified based on the structural information and the constraint information, and the feature extraction is further performed on the unconstrained path to obtain the timing anomaly information, so that a complete automatic link from original data (i.e. the structural information) to a diagnosis result (i.e. the timing anomaly information) is formed. The operation is simple, the timing anomaly information of the unconstrained path is quickly obtained, and the repair rate for the unconstrained path in the subsequent process is improved.