32results about "Counting chain pulse counters" patented technology

A high linearity phase interpolator (PI) is disclosed. A phase value parameter indicative of a desired phase difference between an output signal and an input clock signal edge may be provided by control logic. A first capacitor may be charged for a first period of time with a first current that is proportional to the phase value parameter to produce a first voltage on the capacitor that is proportional to the phase value parameter. The first capacitor may be further charged for a second period of time with a second current that has a constant value to form a voltage ramp offset by the first voltage. A reference voltage may be compared to the voltage ramp during the second period of time. The output signal may be asserted at a time when the voltage ramp equals the reference voltage.

The application discloses a frequency divider and a frequency division system, and relates to the field of signal processing.The frequency divider comprises an input port, an all-pass filter, a first adder and a second adder.The input port is connected with the input end of the all-pass filter, the input end of the first adder and the input end of the second adder.The output end of the all-pass filter is connected with the input end of the first adder and the input end of the second adder.The all-pass filter filters an original signal input by the input port based on preset filter coefficients to obtain a filtered first signal.The output end of the first adder is connected with a high-pass output port of the frequency divider, and the output end of the second adder is connected with a low-pass output port of the frequency divider.The first adder is used for adding a negative value of the first signal to the original signal to obtain a high-pass signal of the frequency divider.The second adder is used for adding the first signal to the original signal to obtain a low-pass signal of the frequency divider.The application provides a frequency divider based on an all-pass filter, which effectively reduces the occupied computing resources of the frequency divider.

A circuit for transmitting an n-bit phase value between circuits includes a system clock input, an n-bit phase value generator coupled to the system clock input that generates a phase value output and an edge output indicating that the phase output value is valid, a latched clock delay circuit having an input coupled to the system clock input, an input coupled to the edge output, a variable phase delay circuit coupled to the phase value output, a delay adder having a first input coupled to the phase value output, a second input coupled to a delay offset signal, and an output coupled to a control input of the variable phase delay circuit, and a phase flip-flop having a data input coupled to an output of the variable phase delay circuit, a clock input coupled to a latched clock output of the variable output clock delay circuit, and a phase out output.

A method for creating and transmitting an encoded data stream comprises receiving a data stream that includes a number M of same-rate data streams x1, x2, . . . , xM, where each data stream in the M same-rate data streams has an ordered number of bits with each bit having a period of Tsym and a clock pulse signal that includes a plurality of pulses where a time duration of each pulse in the plurality of pulses corresponds to Tsym / M. A number M of pulse signals is generated, and an encoded data stream is created by multiplying a value of one bit of each data stream in the ordered number M of data streams by a value of a corresponding of a pulse signal in the ordered number M of orthogonal pulse signals to provide M results, and summing the M results. Once summed, the encoded data stream can be transmitted.

The application provides a programmable frequency divider, a phase-locked loop circuit, a chip and an electronic device, and the programmable frequency divider comprises: a frequency division module, which comprises n frequency division unit cascades, each frequency division unit is controlled by shielding based on a respective reset signal and is controlled by frequency division based on a respective frequency division control bit and a mode input signal, so as to perform frequency division operation on a respective input clock, wherein n is a natural number greater than 1; a control module, which is connected with the frequency division control end and the reset end of each frequency division unit in the frequency division module, and is used for providing a corresponding frequency division control bit and a corresponding reset signal to each frequency division unit; and an output sampling module, which is connected with the mode output end of the second frequency division unit in the frequency division module, and samples the mode output signal of the second frequency division unit based on the input clock of the first frequency division unit to obtain a final frequency division clock. The application solves the problem that the existing programmable frequency divider cannot realize a wide frequency division range.

A digital frequency divider for a voltage supply circuit of a controller is disclosed. The digital frequency divider has a counting unit which has a clock input for a clock signal, a reset input for a reset signal, and a plurality of outputs for division signals. The counting unit is designed to generate the division signals as a division of the clock signal by a power of 2. The digital frequency divider further has a first coupling circuit for coupling the division signals to form a coupling signal, wherein the coupling signal has a logical HIGH only if all coupled division signals have a logical HIGH; and a second coupling circuit which is designed to enter the coupling signal into the reset input of the counting unit.

The utility model relates to the technical field of electronic circuits, and discloses a frequency dividing circuit which comprises n RS D triggers and n initial state setting modules. The Q end of the first D trigger is connected with the D end of the second D trigger, the D triggers are sequentially connected end to end until the Q end of the nth D trigger is connected with the D end of the first D trigger, and the CLK ends of all the D triggers are connected with the same external clock; the R end and the S end of the kth D trigger are connected with the kth initial state setting module, and k is larger than or equal to 1 and smaller than or equal to n; initial values are set for the R end and the S end of the kth D trigger through a kth initial state setting module; the Q1-Qn ends of the first D trigger to the nth D trigger are used as the output of the frequency dividing circuit, the frequency dividing function of a multi-phase clock can be accurately realized by adopting the RS D triggers which are connected end to end, and the duty ratio of the output clock signal of the frequency dividing circuit can be flexibly adjusted by reasonably setting the initial state through the initial state setting module.

A clock signal frequency divider according to one aspect of the present disclosure includes: an output signal generation circuit configured to generate, from pulses of a received input clock signal, an output clock signal including a repetition of a periodic pattern signal in which a pulse of a mask pulse number is masked among consecutive pulses of a periodic pulse number, the periodic pattern signal including a marker portion including at least one unmasked pulse at a start portion of the periodic pattern signal; and an output circuit configured to output the output clock signal, wherein the output signal generation circuit generates the periodic pattern signal in such a way that a pattern of a timing of the at least one unmasked pulse of the marker portion does not appear in a portion other than a portion corresponding to the marker portion in the output clock signal.

The present application provides a pulse width fraction adjustment operator, comprising: a pulse width fraction adjuster, a state controller, an integer frequency divider and a pulse width operator connected together; input signals include a frequency divided clock signal, a reference clock signal, integer frequency division values N1, N2 and a fraction frequency division value F; output signals include comparison results UP and DW signals. It can help phase-locked loop to realize fraction frequency division, theoretically without fraction spurious problem, and at the same time, the phase-locked loop loop bandwidth can be close to or even exceed the resolution frequency of the phase-locked loop.

A digital frequency divider, a voltage supply and a method for operating a monitoring circuit disclose a digital frequency divider (10) for a controller (600) voltage supply circuit (500). The digital frequency divider (10) comprises a counting unit (100) having a clock input (110) for a clock signal (50), a reset input (120) for a reset signal, and a plurality of outputs (130) for a frequency divider signal (Qn). The counter unit (100) is designed to generate a frequency divider signal (Qn) which is divided by power of 2 as a clock signal (50). The digital frequency divider (10) further comprises a first coupling circuit (200) for coupling the frequency divider signal (Qn) into a coupling signal (250), and a second coupling circuit (300) designed to input the coupling signal (250) to the reset input (120) of the counting unit (100), in which only when all the coupled frequency divider signals (Qn) have a logic high, the first coupling circuit (200) and the second coupling circuit (300) are coupled into the reset input (120) of the counting unit (100). The coupling signal (250) has a logic high.

An electronic circuit (200) is provided that is a high-speed CMOS logic circuit for frequency division of an input signal. The electronic circuit comprises a ring oscillator (201). The ring oscillator (201) comprises a plurality of gated inverters. At least one of the gated inverters (290) is configured to receive an oscillation signal (281) and a control signal at two complementary inputs. The electronic circuit (200) is configured to be partially gated such that the division ratio is selectable. A very high-speed multi-mode clock divider is achieved by clock partial gating, open-loop clock buffering, and avoiding slow combinatorial logic in the data path.

An electronic device comprising: a voltage stabilizing circuit configured to output a stabilized voltage based on a reference voltage and a feedback voltage; and an oscillator configured to generate an output frequency signal based on a reference frequency signal and the stabilized voltage output from the voltage stabilizing circuit, wherein the voltage stabilizing circuit comprises: a feedback loop configured to output the stabilized voltage based on a difference between the reference voltage and the feedback voltage; a first capacitor; a pre-charge circuit connected to the feedback loop and configured to charge the first capacitor with a second voltage based on a first voltage; a first switch configured to connect the pre-charge circuit with the first capacitor; and a second switch configured to connect the first capacitor with the feedback loop.

The application provides a pulse collection circuit and a controller for flow metering. The pulse collection circuit comprises a power supply circuit, an anti-interference circuit and a metering circuit, the power supply circuit is connected with the metering circuit and the anti-interference circuit respectively, and the anti-interference circuit is connected with the metering circuit. The anti-interference circuit is used for receiving a pulse signal collected by a flow meter and sending the pulse signal to the metering circuit, wherein the pulse signal comprises an active pulse signal and a passive pulse signal. The metering circuit is used for counting flow according to the pulse signal, and the power supply circuit is used for providing a bias voltage for the pulse signal input to the metering circuit and the anti-interference circuit. According to the application, the active pulse signal and the passive pulse signal collected by the flow meter can be received by the same pulse collection circuit, and then flow metering is performed according to the collected active pulse signal or passive pulse signal, so that the user can use more conveniently.

The invention provides a programmable frequency divider circuit. The programmable frequency divider circuit comprises a first-path frequency division clock signal generation unit, a second-path frequency division clock signal generation unit and a target clock signal generation unit, the first path frequency division clock signal generation unit and the second path frequency division clock signal generation unit share a first counter; the first-path frequency division clock signal generation unit is used for sampling the first counter to obtain a first-path frequency division clock signal; the second-path frequency division clock signal generation unit is used for sampling the first counter, performing reset operation on the second counter according to a sampling result, and generating a second-path frequency division clock signal; and the target clock signal generation unit is used for generating a target clock signal according to the first path of frequency division clock signal and the second path of frequency division clock signal, fixed 50% duty ratio output can be realized by utilizing two counters, a duty ratio adjusting circuit without increasing the area and a redundant feedback adjusting loop are not needed, and the power consumption and the design cost are reduced.

The invention relates to a clock frequency divider and a clock frequency dividing method using the same. Disclosed are a clock divider capable of keeping an output clock duty constant regardless of a change time point of a division value, and a clock division method using the same. A clock divider according to an embodiment of the present invention comprises: a counter for counting an input clock and generating a counter output based on a count of a first counter expiration value corresponding to a division value of the clock; an output clock generator which generates an output clock divided by the input clock according to the counter output of the counter; and a state machine that, when the divided frequency value is changed, updates the counter using a second counter expiration value corresponding to the changed divided frequency value according to whether the first counter expiration value expires.

The application discloses a clock phase separation method, a clock phase separation circuit and a multi-phase switching circuit. A high-frequency clock signal is output according to the comparison result of a first slope signal and a reference voltage, wherein the first slope signal is reset according to the high-frequency clock signal and a standard clock signal; the high-frequency clock signal is frequency-divided to generate a 2nd to (n+1)th phase clock signal; and the size of the reference voltage or the slope of the first slope signal is adjusted according to the (n+1)th phase clock signal and the standard clock signal, so that in a stable state, the absolute value of the phase difference between the (n+1)th phase clock signal and the standard clock signal is less than a preset value, wherein n is an integer greater than or equal to 2. The circuit structure of the clock phase separation circuit is simple, and when the size of the reference voltage is adjusted according to the (n+1)th phase clock signal and the standard clock signal, when n is an integer greater than or equal to 3, the phase difference consistency of the standard clock signal and the 2nd to n-th phase clock signals is good, and the phase separation precision is high.

In many embodiments of the invention, a clock generation circuit includes a numerically controlled oscillator to receive a frequency control word and generate a fractional time signal, a variable delay circuit including a buffer driving a variable switch-capacitor network, the variable delay circuit configured to receive the fractional time signal and generate a delayed clock signal with a time delay that is linear with total capacitance at a load using probabilistic delay assignment, and a probabilistic delay assignment circuit to select between a first delay setting including delay line only and a second delay setting including a sample clock period delay plus delay line, wherein the probabilistic delay assignment circuit assigns probabilities pl = ml / L and p2 = (L-ml) / L for selecting the first and second delay settings, where ml represents a fractional portion of a desired delay and L represents a ratio between sample clock period and unit delay.

The application provides a data acquisition method, a control device and a multi-sensor system. The method comprises the following steps: in the i-th pulse period, when the first sensor outputs a first pulse signal, dividing the first pulse signal based on the acquisition frequency corresponding to the second sensor to generate a second pulse signal; when a preset time length is reached, triggering the second sensor to enter a data acquisition stage based on the second pulse signal; in the i+1-th pulse period, acquiring a plurality of first data generated by the first sensor and second data generated by the second sensor; wherein the first generation time and the second generation time are synchronized to construct calibration data for calibrating device parameters of the first sensor and the second sensor. The above method can align the generation time of the data acquired by different sensors.

The invention discloses a calibration control method of a low-power-consumption counter, which comprises the following steps of: aiming at a first timer on an MCU (Microprogrammed Control Unit), using a crystal oscillator as a clock source, and carrying out frequency division to dozens of KHz to more than one hundred KHz as much as possible through a frequency divider; a low-speed oscillator in the MCU is used for a second timer on the MCU, and the duration of the second timer is set to be integer multiples of the duration of the first timer; the first timer and the second timer are started at the same time during initialization, and the value of the counter in the second timer is immediately read and recorded in a variable N1; the first timer firstly generates interruption, reads a value of a counter in the second timer and records the value into a variable N2, and then stops the second timer. According to the scheme, the timing precision of the ECU low-power-consumption counter can be improved on the basis of the existing clock source and the timer under the condition that the cost of raw materials is not increased (a low-speed external crystal oscillator does not need to be added).

The utility model provides a variable modulus counter, including reset circuit, counting circuit, keying circuit, comparison circuit, conversion circuit, decoding circuit and display circuit, the reset circuit is connected on counting circuit, through the reset circuit realizes the zero clearing operation of counting circuit, counting circuit is used for counting input pulse signal, the decoding circuit is used for decoding the input pulse signal, and the display circuit is used for displaying the output pulse signal. The key circuit, the counting circuit and the counting comparison circuit are connected, the counting modulus of the counter is adjusted through the key circuit, the output end of the counting circuit is connected with the comparison circuit, an output signal of the counter and a signal input by a key are compared through the comparison circuit, and the output end of the counting circuit is further connected with a conversion circuit. The counting circuit is composed of the reset circuit, the counting circuit, the key circuit, the comparison circuit, the conversion circuit, the decoding circuit and the display circuit, and flexible adjustment of counting modulus can be achieved through cooperative work of the reset circuit, the counting circuit, the key circuit, the comparison circuit, the conversion circuit, the decoding circuit and the display circuit.

The application provides a frequency division circuit, a frequency divider, a radio frequency circuit and an electronic device. The frequency division circuit comprises first to 2nth sub-modules, each of which comprises a frequency division unit and a phase generation unit. In the same sub-module, a first output end is connected with a fourth input end. In each of two adjacent sub-modules, a second output end of a sub-module located at a front side in a first direction is connected with a first input end of a sub-module located at a rear side. When k≤n, a second input end of a kth sub-module is connected with a first output end of a (k+n)th sub-module. When k>n, the second input end of the kth sub-module is connected with a first output end of a (k-n)th sub-module. When k>n-2, a fifth output end of the kth sub-module is connected with a first output end of a (k-n+2)th sub-module. When k≤n-2, the fifth output end of the kth sub-module is connected with a first output end of a (k+n+2)th sub-module.

A digital frequency divider (10) for a power supply circuit (500) of a controller (600) is disclosed. The digital frequency divider (10) comprises a counter unit (100) having a clock input (110) for a clock signal (50), a reset input (120) for a reset signal, and a plurality of outputs (130) for divider signals (Qn). The counter unit (100) is configured to generate the divider signals (Qn) as a division of the clock signal (50) by a power of 2. The digital frequency divider (10) further comprises a first coupling circuit (200) for coupling the divider signals (Qn) to a coupling signal (250), wherein the coupling signal (250) exhibits a logic HIGH only when all coupled divider signals (Qn) exhibit a logic HIGH. and a second coupling circuit (300) configured to input the coupling signal (250) into the reset input (120) of the counting unit (100).

In many embodiments of the invention, a clock generation circuit includes a numerically controlled oscillator to receive a frequency control word and generate a fractional time signal, a variable delay circuit including a buffer driving a variable switch-capacitor network, the variable delay circuit configured to receive the fractional time signal and generate a delayed clock signal with a time delay that is linear with total capacitance at a load using probabilistic delay assignment, and a probabilistic delay assignment circuit to select between a first delay setting including delay line only and a second delay setting including a sample clock period delay plus delay line, wherein the probabilistic delay assignment circuit assigns probabilities p1=m1 / L and p2=(L−m1) / L for selecting the first and second delay settings, where m1 represents a fractional portion of a desired delay and L represents a ratio between sample clock period and unit delay.

The invention provides a programmable frequency divider and an electronic device. The programmable frequency divider comprises an M / M + 1 prescaler which is used for dynamically switching between a first frequency division mode with a frequency division ratio of M and a second frequency division mode with a frequency division ratio of M + 1 according to a first control signal; when the M / M + 1 prescaler is in a first frequency division mode, an input clock of a voltage-controlled oscillator is subjected to frequency division according to a frequency division ratio M, and an output clock is obtained; when the M / M + 1 prescaler is in a second frequency division mode, the input clock of the voltage-controlled oscillator is subjected to frequency division according to the frequency division ratio of M + 1, and an output clock is obtained; and the 2 frequency divider is used for carrying out 2 frequency division on the output clock output by the M / M + 1 prescaler, outputting a final clock signal, and feeding back the first control signal to the M / M + 1 prescaler according to the final clock signal and a second control signal. Through the design, the multi-modulus frequency divider with the continuously programmable frequency dividing ratio and the output duty ratio of about 50% is realized.

The application relates to a method, device, equipment and storage medium for configuring an asynchronous clock divider. The method comprises the following steps: configuring a frequency division coefficient of the asynchronous clock divider, calculating a first check code of the frequency division coefficient, judging whether the frequency division coefficient is consistent with a current frequency division coefficient of the asynchronous clock divider, if not, generating a request signal for changing the frequency division coefficient of the asynchronous clock divider, and sending the frequency division coefficient and the first check code to the asynchronous clock divider, controlling the asynchronous clock divider to perform a check operation on the first check code, and if the check passes, updating the current frequency division coefficient of the asynchronous clock divider according to the frequency division coefficient. The application simplifies the configuration process of the asynchronous clock divider, can realize automatic configuration of the frequency division coefficient, can ensure that the frequency division coefficient can be correctly transmitted to the asynchronous clock divider, and improves the reliability and robustness of a chip clock system.

Embodiments of the present disclosure relate to fractional divider calibration with dual digitally controlled delay circuits. Systems and methods for calibrating a fractional divider are described. A system can include a divider and a circuit. The divider can divide an input clock signal to generate an integer output divider (IOD) signal. The circuit can include a first digitally controlled delay (DCD) circuit configured to delay the IOD signal to generate a first delayed IOD signal. The circuit can also include a second DCD circuit configured to delay the first delayed IOD signal to generate a second delayed IOD signal. The circuit can also include an edge sampler configured to compare an edge of the second delayed IOD signal to an edge of the input clock signal. The circuit can also include a controller configured to calibrate the first DCD circuit based on a result of the comparison of the edge of the second delayed IOD signal to the edge of the input clock signal.

Systems and methods for calibrating a fractional divider are described. A system can include a divider and a circuit. The divider can divide an input clock signal to generate an integer output divider (IOD) signal. The circuit can include a first digital control delay (DCD) circuit configured to delay the IOD signal to generate a first delayed IOD signal. The circuit can further include a second DCD circuit configured to delay the first delayed IOD signal to generate a second delayed IOD signal. The circuit can further include an edge sampler configured to compare an edge of the second delayed IOD signal with an edge of the input clock signal. The circuit can further include a controller configured to calibrate the first DCD circuit based on a result of the comparison between the edge of the second delayed IOD signal with the edge of the input clock signal.

This application relates to the field of integrated circuit technology and discloses a 1.5 divider based on a phase interpolator with an output duty cycle of 50%, comprising: a 1.5 divider, a phase interpolator, and a duty cycle adjustment module connected in sequence. The 1.5 divider outputs a pair of divided signals with duty cycles of 1 / 3 and 2 / 3 respectively, and a division ratio of 1.5, based on a pair of positive and negative clock signals. The average duty cycle of the pair of divided signals is 1 / 2. The phase interpolator slows down the signal edges of the pair of divided signals and outputs an interpolated signal to the duty cycle adjustment module. The phase of the interpolated signal is the average phase of the pair of divided signals. The duty cycle adjustment module finely adjusts the duty cycle of the interpolated signal to 1 / 2.

A digital frequency divider (10) for a power supply circuit (500) of a controller (600) is disclosed. The digital frequency divider (10) comprises a counter unit (100) having a clock input (110) for a clock signal (50), a reset input (120) for a reset signal, and a plurality of outputs (130) for divider signals (Qn). The counter unit (100) is configured to generate the divider signals (Qn) as a division of the clock signal (50) by a power of 2. The digital frequency divider (10) further comprises a first coupling circuit (200) for coupling the divider signals (Qn) to a coupling signal (250), wherein the coupling signal (250) has a logic HIGH only when all coupled divider signals (Qn) have a logic HIGH, and a second coupling circuit (300) configured to input the coupling signal (250) into the reset input (120) of the counting unit (100).

A clock divider and a clock division method using the same for maintaining a constant output clock duty regardless of a divide value change timing are provided. The clock divider includes a counter configured to count an input clock to generate a counter output based on a count of a first counter expiration value corresponding to a divide value of the clock, an output clock generator configured to generate an output clock divided from the input clock according to the counter output of the counter, and a state machine configured to update the counter to a second counter expiration value corresponding to a changed divide value depending on whether the first counter expiration value has expired based on the divide value being changed.