62results about "Counting chain pulse counters" patented technology

The invention discloses a fault detection method, a chip, a storage medium and an electronic device, and relates to the technical field of computers, and the method comprises the steps: carrying out the edge detection of a pulse signal received from a fault counting pin of a processor, and when the pulse signal is detected to be at a first edge of a first level, carrying out the detection; and the number of the received pulse signals at the first level is accumulated, so that the fault occurrence frequency can be accurately counted. And then, generating an interrupt signal based on the first edge, and sending the cumulative number of the interrupt signal and the pulse signal to the controller unit, so that the controller unit triggers an interrupt program in time and stores the cumulative number in real time, thereby not only quickly finishing fault processing when a fault is detected, but also storing the cumulative number of the fault in real time, and improving the fault processing efficiency. The fault detection accuracy and the fault processing efficiency are improved, and the technical problem that the fault detection accuracy is low is solved.

A high linearity phase interpolator (PI) is disclosed. A phase value parameter indicative of a desired phase difference between an output signal and an input clock signal edge may be provided by control logic. A first capacitor may be charged for a first period of time with a first current that is proportional to the phase value parameter to produce a first voltage on the capacitor that is proportional to the phase value parameter. The first capacitor may be further charged for a second period of time with a second current that has a constant value to form a voltage ramp offset by the first voltage. A reference voltage may be compared to the voltage ramp during the second period of time. The output signal may be asserted at a time when the voltage ramp equals the reference voltage.

The invention provides a control word digital adjustment circuit and a retimer based on a decimal N frequency division phase-locked loop. The control word digital adjustment circuit comprises a digital low-pass filtering module and a control word adjustment module, wherein the digital low-pass filtering module is used for filtering high-frequency jitter and part of low-frequency jitter in an initial control word so as to generate a filtering control word; the control word adjusting module is used for adjusting the filtering control word based on a writing pointer and a reading pointer of a first-in first-out buffer in the retimer so as to generate an adjusting control word; the adjustment control word is used for replacing the initial control word to serve as input of a transmitter fractional N frequency division phase-locked loop in the re-timer. According to the invention, the problem of frequency deviation jitter of RX Clock and TX Clock easily caused by wrong reading numerical value of an asynchronous interface of the FCW in the existing scheme can be effectively solved.

The application belongs to the technical field of integrated circuits, and particularly relates to a UART decimal correction circuit and a correction method. The UART decimal correction circuit comprises a frequency division coefficient preloading circuit, an integer frequency division up counter, a decimal correction down counter, and a decimal correction algorithm circuit. The decimal correction algorithm circuit is used for inputting a count value cnt_i[9:0] and a count value cnt_f[3:0], determining a decimal correction sampling point through a shift, negation and comparison mode, and outputting a pulse signal reload to the integer frequency division up counter, the decimal correction down counter and a D flip-flop. When the pulse signal reload is valid, it is determined whether the integer frequency division up counter needs to be added by 1 and whether the decimal correction down counter needs to be subtracted by 1. The D flip-flop is used. The application determines the decimal correction sampling point through the shift, negation and comparison algorithm, so that a more accurate baud rate is realized with less logic.

The application discloses a frequency divider and a frequency division system, and relates to the field of signal processing.The frequency divider comprises an input port, an all-pass filter, a first adder and a second adder.The input port is connected with the input end of the all-pass filter, the input end of the first adder and the input end of the second adder.The output end of the all-pass filter is connected with the input end of the first adder and the input end of the second adder.The all-pass filter filters an original signal input by the input port based on preset filter coefficients to obtain a filtered first signal.The output end of the first adder is connected with a high-pass output port of the frequency divider, and the output end of the second adder is connected with a low-pass output port of the frequency divider.The first adder is used for adding a negative value of the first signal to the original signal to obtain a high-pass signal of the frequency divider.The second adder is used for adding the first signal to the original signal to obtain a low-pass signal of the frequency divider.The application provides a frequency divider based on an all-pass filter, which effectively reduces the occupied computing resources of the frequency divider.

The present application discloses a communication circuit. The communication circuit includes: a clock input; and a clock divider configured to generate an output clock signal having a fundamental frequency substantially equal to the fundamental frequency of an input clock signal received at the clock input divided by a factor (2 N +1) / 2 N , wherein the clock divider is configured to generate 2 based at least in part on the input clock signal N +1 pre-aligned phase-shifted clock signal; based at least in part on 2 N +1 pre-aligned phase-shifted clock signal to generate 2 N A specific phase-shifted clock signal, where 2 N The phase of a specific phase-shifted clock signal is basically 360 / 2 N degree of separation; and based at least in part on 2 N a specific phase-shifted clock signal to generate an output clock signal; and a mixer configured to receive the output clock signal.

A circuit for transmitting an n-bit phase value between circuits includes a system clock input, an n-bit phase value generator coupled to the system clock input that generates a phase value output and an edge output indicating that the phase output value is valid, a latched clock delay circuit having an input coupled to the system clock input, an input coupled to the edge output, a variable phase delay circuit coupled to the phase value output, a delay adder having a first input coupled to the phase value output, a second input coupled to a delay offset signal, and an output coupled to a control input of the variable phase delay circuit, and a phase flip-flop having a data input coupled to an output of the variable phase delay circuit, a clock input coupled to a latched clock output of the variable output clock delay circuit, and a phase out output.

To output a stable waveform to a device which operates at frequencies lower than a clock.SOLUTION: The frequency adjustment device includes: a counter section 2 of a binary counter for counting a clock signal CLK; and a waveform output section 3 for outputting a waveform in accordance with an output from the counter section 2 and returning a cycle-delayed value to the counter section 2. By performing frequency division with an addition value FIN[7:0], a frequency-division circuit outputs a pulse output PLSOUT having a frequency lower than the clock signal CLK, and a fluctuation-prevention circuit prevents cycle fluctuation caused by a carry generated when counting is completed.SELECTED DRAWING: Figure 1

A method for creating and transmitting an encoded data stream comprises receiving a data stream that includes a number M of same-rate data streams x1, x2, . . . , xM, where each data stream in the M same-rate data streams has an ordered number of bits with each bit having a period of Tsym and a clock pulse signal that includes a plurality of pulses where a time duration of each pulse in the plurality of pulses corresponds to Tsym / M. A number M of pulse signals is generated, and an encoded data stream is created by multiplying a value of one bit of each data stream in the ordered number M of data streams by a value of a corresponding of a pulse signal in the ordered number M of orthogonal pulse signals to provide M results, and summing the M results. Once summed, the encoded data stream can be transmitted.

The application provides a clock divider circuit, a phase synchronization method thereof and an electronic device. The clock divider circuit comprises: an electronic oscillator configured to generate a root clock signal of a first frequency; and a plurality of clock dividers connected to the electronic oscillator respectively, wherein the root clock signal is input into the plurality of clock dividers respectively, and the plurality of clock dividers are configured to generate a plurality of variable frequency clock signals of different frequencies according to the root clock signal of the first frequency and a preset variable frequency coefficient. In this scheme, the modification of the frequency division coefficient of one clock divider does not affect the clock signals of other clock dividers, and the phase synchronization between the clock signals can be maintained after frequency division, and the phase relationship is not lost due to the variable frequency process.

The application provides a programmable frequency divider, a phase-locked loop circuit, a chip and an electronic device, and the programmable frequency divider comprises: a frequency division module, which comprises n frequency division unit cascades, each frequency division unit is controlled by shielding based on a respective reset signal and is controlled by frequency division based on a respective frequency division control bit and a mode input signal, so as to perform frequency division operation on a respective input clock, wherein n is a natural number greater than 1; a control module, which is connected with the frequency division control end and the reset end of each frequency division unit in the frequency division module, and is used for providing a corresponding frequency division control bit and a corresponding reset signal to each frequency division unit; and an output sampling module, which is connected with the mode output end of the second frequency division unit in the frequency division module, and samples the mode output signal of the second frequency division unit based on the input clock of the first frequency division unit to obtain a final frequency division clock. The application solves the problem that the existing programmable frequency divider cannot realize a wide frequency division range.

The disclosure provides a multi-mode frequency division circuit including a frequency division factor processor, a frequency divider, and a logic operator. The frequency division factor processor receives the frequency division factor, decomposes the frequency division factor to obtain a first sub-frequency division factor and a second sub-frequency division factor, and outputs the first sub-frequency division factor or the second sub-frequency division factor according to a frequency division clock signal. The divider performs frequency division on the clock signal based on the first sub-frequency division factor or the second sub-frequency division factor to generate the frequency division clock signal. The logic operator sequentially samples the frequency division clock signal according to the rising edge and falling edge of the clock signal to generate a first signal and a second signal, and the logic operator generates an output clock signal according to the first signal, the second signal, and an indication signal.

A digital frequency divider for a voltage supply circuit of a controller is disclosed. The digital frequency divider has a counting unit which has a clock input for a clock signal, a reset input for a reset signal, and a plurality of outputs for division signals. The counting unit is designed to generate the division signals as a division of the clock signal by a power of 2. The digital frequency divider further has a first coupling circuit for coupling the division signals to form a coupling signal, wherein the coupling signal has a logical HIGH only if all coupled division signals have a logical HIGH; and a second coupling circuit which is designed to enter the coupling signal into the reset input of the counting unit.

The utility model relates to the technical field of electronic circuits, and discloses a frequency dividing circuit which comprises n RS D triggers and n initial state setting modules. The Q end of the first D trigger is connected with the D end of the second D trigger, the D triggers are sequentially connected end to end until the Q end of the nth D trigger is connected with the D end of the first D trigger, and the CLK ends of all the D triggers are connected with the same external clock; the R end and the S end of the kth D trigger are connected with the kth initial state setting module, and k is larger than or equal to 1 and smaller than or equal to n; initial values are set for the R end and the S end of the kth D trigger through a kth initial state setting module; the Q1-Qn ends of the first D trigger to the nth D trigger are used as the output of the frequency dividing circuit, the frequency dividing function of a multi-phase clock can be accurately realized by adopting the RS D triggers which are connected end to end, and the duty ratio of the output clock signal of the frequency dividing circuit can be flexibly adjusted by reasonably setting the initial state through the initial state setting module.

A clock signal frequency divider according to one aspect of the present disclosure includes: an output signal generation circuit configured to generate, from pulses of a received input clock signal, an output clock signal including a repetition of a periodic pattern signal in which a pulse of a mask pulse number is masked among consecutive pulses of a periodic pulse number, the periodic pattern signal including a marker portion including at least one unmasked pulse at a start portion of the periodic pattern signal; and an output circuit configured to output the output clock signal, wherein the output signal generation circuit generates the periodic pattern signal in such a way that a pattern of a timing of the at least one unmasked pulse of the marker portion does not appear in a portion other than a portion corresponding to the marker portion in the output clock signal.

The present application provides a pulse width fraction adjustment operator, comprising: a pulse width fraction adjuster, a state controller, an integer frequency divider and a pulse width operator connected together; input signals include a frequency divided clock signal, a reference clock signal, integer frequency division values N1, N2 and a fraction frequency division value F; output signals include comparison results UP and DW signals. It can help phase-locked loop to realize fraction frequency division, theoretically without fraction spurious problem, and at the same time, the phase-locked loop loop bandwidth can be close to or even exceed the resolution frequency of the phase-locked loop.

A digital frequency divider, a voltage supply and a method for operating a monitoring circuit disclose a digital frequency divider (10) for a controller (600) voltage supply circuit (500). The digital frequency divider (10) comprises a counting unit (100) having a clock input (110) for a clock signal (50), a reset input (120) for a reset signal, and a plurality of outputs (130) for a frequency divider signal (Qn). The counter unit (100) is designed to generate a frequency divider signal (Qn) which is divided by power of 2 as a clock signal (50). The digital frequency divider (10) further comprises a first coupling circuit (200) for coupling the frequency divider signal (Qn) into a coupling signal (250), and a second coupling circuit (300) designed to input the coupling signal (250) to the reset input (120) of the counting unit (100), in which only when all the coupled frequency divider signals (Qn) have a logic high, the first coupling circuit (200) and the second coupling circuit (300) are coupled into the reset input (120) of the counting unit (100). The coupling signal (250) has a logic high.

An electronic circuit (200) is provided that is a high-speed CMOS logic circuit for frequency division of an input signal. The electronic circuit comprises a ring oscillator (201). The ring oscillator (201) comprises a plurality of gated inverters. At least one of the gated inverters (290) is configured to receive an oscillation signal (281) and a control signal at two complementary inputs. The electronic circuit (200) is configured to be partially gated such that the division ratio is selectable. A very high-speed multi-mode clock divider is achieved by clock partial gating, open-loop clock buffering, and avoiding slow combinatorial logic in the data path.

The present invention discloses a fractional multi-mode frequency divider circuit based on space-time averaging and phase interpolation technology, comprising: a third-order noise shaping modulation module, a dynamic element matching and phase selection module, a phase switching frequency divider module, and a pipelined phase interpolation module; the third-order noise shaping modulation module is used to perform time averaging on the input frequency division ratio to generate an instantaneous frequency division ratio; the dynamic element matching and phase selection module is used to perform spatial averaging on the instantaneous frequency division ratio and generate a frequency divider control word and a phase interpolator control word; the phase switching frequency divider module is used to generate a clock signal corresponding to the frequency division ratio based on the frequency divider control word; and the pipelined phase interpolation module is used to perform phase interpolation on the clock signal to generate a final clock signal with an accurate phase. The embodiments of the present invention utilize the mutual cooperation of the various modules to achieve the integration of space-time averaging technology and phase interpolation technology, thereby improving the limitations of space-time averaging technology.

An electronic device comprising: a voltage stabilizing circuit configured to output a stabilized voltage based on a reference voltage and a feedback voltage; and an oscillator configured to generate an output frequency signal based on a reference frequency signal and the stabilized voltage output from the voltage stabilizing circuit, wherein the voltage stabilizing circuit comprises: a feedback loop configured to output the stabilized voltage based on a difference between the reference voltage and the feedback voltage; a first capacitor; a pre-charge circuit connected to the feedback loop and configured to charge the first capacitor with a second voltage based on a first voltage; a first switch configured to connect the pre-charge circuit with the first capacitor; and a second switch configured to connect the first capacitor with the feedback loop.

The application provides a pulse collection circuit and a controller for flow metering. The pulse collection circuit comprises a power supply circuit, an anti-interference circuit and a metering circuit, the power supply circuit is connected with the metering circuit and the anti-interference circuit respectively, and the anti-interference circuit is connected with the metering circuit. The anti-interference circuit is used for receiving a pulse signal collected by a flow meter and sending the pulse signal to the metering circuit, wherein the pulse signal comprises an active pulse signal and a passive pulse signal. The metering circuit is used for counting flow according to the pulse signal, and the power supply circuit is used for providing a bias voltage for the pulse signal input to the metering circuit and the anti-interference circuit. According to the application, the active pulse signal and the passive pulse signal collected by the flow meter can be received by the same pulse collection circuit, and then flow metering is performed according to the collected active pulse signal or passive pulse signal, so that the user can use more conveniently.

The present application relates to the technical field of frequency divider integrated circuit, in particular to a 2-7 prescaler with 50% duty cycle, which comprises a 2 / 3 frequency division unit with frequency division ratio expansion bit, an additional 2 frequency division logic module, an additional expansion transmission path module and an odd integer duty cycle correction logic module. The present application firstly performs 2 / 3 operation in the 2 / 3 frequency division unit according to the frequency division ratio, and then inputs the output signal into the additional 2 frequency division logic. When the frequency division ratio is greater than 3, the additional expansion transmission path module works. When the frequency division ratio is odd, the duty cycle correction module corrects the duty cycle of the input signal. Compared with the prior art, the present application has the advantages of simple circuit structure, wide frequency division ratio coverage, low noise contribution and output duty cycle close to 50%, and can be applied to multi-mode programmable frequency divider.

The invention provides a programmable frequency divider circuit. The programmable frequency divider circuit comprises a first-path frequency division clock signal generation unit, a second-path frequency division clock signal generation unit and a target clock signal generation unit, the first path frequency division clock signal generation unit and the second path frequency division clock signal generation unit share a first counter; the first-path frequency division clock signal generation unit is used for sampling the first counter to obtain a first-path frequency division clock signal; the second-path frequency division clock signal generation unit is used for sampling the first counter, performing reset operation on the second counter according to a sampling result, and generating a second-path frequency division clock signal; and the target clock signal generation unit is used for generating a target clock signal according to the first path of frequency division clock signal and the second path of frequency division clock signal, fixed 50% duty ratio output can be realized by utilizing two counters, a duty ratio adjusting circuit without increasing the area and a redundant feedback adjusting loop are not needed, and the power consumption and the design cost are reduced.

Aspects relate to a divide by 3 prescaler for an integrated circuit. An apparatus includes a first logic block configured to generate a first input pulse at a rising edge of a clock signal, and a second logic block configured to generate a second input pulse after the first input pulse that ends at a falling edge of the clock signal. The falling edge is for a clock cycle subsequent to the rising edge. A third logic block is coupled to the first input pulse and the second input pulse and configured to generate a divide by 3 clock output.

A computational pixel imaging device can include multiple digitizing counters per pixel that can be used to execute simultaneous signal-processing threads on acquired image data. The imaging device can also include infinite dynamic range sensing and perform signal down- sampling.

The invention provides a programmable frequency divider, a phase-locked loop circuit, a chip and electronic equipment thereof, and the programmable frequency divider comprises a frequency division module which comprises n cascaded frequency division units, each stage of frequency division unit performs shielding control based on a respective reset signal, and performs frequency division control based on a respective frequency division control bit and a mode input signal, n is a natural number greater than 1, and n is an integer greater than 1; the control module is connected with the frequency division control end and the reset end of each frequency division unit in the frequency division module, and is used for providing corresponding frequency division control bits and corresponding reset signals for each frequency division unit; and the output sampling module is connected with a mode output end of a second-stage frequency division unit in the frequency division module, and samples a mode output signal of the second-stage frequency division unit based on an input clock of the first-stage frequency division unit to obtain a final frequency division clock. According to the programmable frequency divider, the problem that an existing programmable frequency divider cannot realize a wide frequency division range is solved.

The invention relates to a clock frequency divider and a clock frequency dividing method using the same. Disclosed are a clock divider capable of keeping an output clock duty constant regardless of a change time point of a division value, and a clock division method using the same. A clock divider according to an embodiment of the present invention comprises: a counter for counting an input clock and generating a counter output based on a count of a first counter expiration value corresponding to a division value of the clock; an output clock generator which generates an output clock divided by the input clock according to the counter output of the counter; and a state machine that, when the divided frequency value is changed, updates the counter using a second counter expiration value corresponding to the changed divided frequency value according to whether the first counter expiration value expires.

The application discloses a clock phase separation method, a clock phase separation circuit and a multi-phase switching circuit. A high-frequency clock signal is output according to the comparison result of a first slope signal and a reference voltage, wherein the first slope signal is reset according to the high-frequency clock signal and a standard clock signal; the high-frequency clock signal is frequency-divided to generate a 2nd to (n+1)th phase clock signal; and the size of the reference voltage or the slope of the first slope signal is adjusted according to the (n+1)th phase clock signal and the standard clock signal, so that in a stable state, the absolute value of the phase difference between the (n+1)th phase clock signal and the standard clock signal is less than a preset value, wherein n is an integer greater than or equal to 2. The circuit structure of the clock phase separation circuit is simple, and when the size of the reference voltage is adjusted according to the (n+1)th phase clock signal and the standard clock signal, when n is an integer greater than or equal to 3, the phase difference consistency of the standard clock signal and the 2nd to n-th phase clock signals is good, and the phase separation precision is high.

In many embodiments of the invention, a clock generation circuit includes a numerically controlled oscillator to receive a frequency control word and generate a fractional time signal, a variable delay circuit including a buffer driving a variable switch-capacitor network, the variable delay circuit configured to receive the fractional time signal and generate a delayed clock signal with a time delay that is linear with total capacitance at a load using probabilistic delay assignment, and a probabilistic delay assignment circuit to select between a first delay setting including delay line only and a second delay setting including a sample clock period delay plus delay line, wherein the probabilistic delay assignment circuit assigns probabilities pl = ml / L and p2 = (L-ml) / L for selecting the first and second delay settings, where ml represents a fractional portion of a desired delay and L represents a ratio between sample clock period and unit delay.