1100results about "Counting chain pulse counters" patented technology

A digital wavetable audio synthesizer is described. The synthesizer can generate up to 32 high-quality audio digital signals or voices, including delay-based effects, at either a 44.1 KHz sample rate or at sample rates compatible with a prior art wavetable synthesizer. The synthesizer includes an address generator which has several modes of addressing wavetable data. The address generator's addressing rate controls the pitch of the synthesizer's output signal. The synthesizer performs a 10-bit interpolation, using the wavetable data addressed by the address generator, to interpolate additional data samples. When the address generator loops through a block of data, the signal path interpolates between the data at the end and start addresses of the block of data to prevent discontinuities in the generated signal. A synthesizer volume generator, which has several modes of controlling the volume, adds envelope, right offset, left offset, and effects volume to the data. The data can be placed in one of sixteen fixed stereo pan positions, or left and right offsets can be programmed to place the data anywhere in the stereo field. The left and right offset values can also be programmed to control the overall volume. Zipper noise is prevented by controlling the volume increment. A synthesizer LFO generator can add LFO variation to: (i) the wavetable data addressing rate, for creating a vibrato effect; and (ii) a voice's volume, for creating a tremolo effect. Generated data to be output from the synthesizer is stored in left and right accumulators. However, when creating delay-based effects, data is stored in one of several effects accumulators. This data is then written to a wavetable. The difference between the wavetable write and read addresses for this data provides a delay for echo and reverb effects. LFO variations added to the read address create chorus and flange effects. The volume of the delay-based effects data can be attenuated to provide volume decay for an echo effect. After the delay-based effects processing, the data can be provided with left and right offset volume components which determine how much of the effect is heard and its stereo position. The data is then stored in the left and right accumulators.

Circuits and methods are provided for implementing programmable sub-integer N frequency dividers for use in, e.g., frequency synthesizer applications, providing glitch free outputs signals with minimal fractional spurs. Phase-rotating sub-integer N frequency dividers are programmable to provide multi-modulus division with a wide range of arbitrary sub-integer division ratios.

An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

A phase lock loop (PLL) for controlling a sampling clock or other clock, and a data sampling circuit, transceiver, or other device including such a PLL. The PLL includes a multi-range VCO, at least one fine control loop for controlling the VCO, and a coarse control loop for controlling the VCO by changing its frequency-voltage characteristic. The coarse control loop includes a frequency lock detector and voltage range monitoring logic. Typically, the frequency lock detector locks operation of the coarse control loop when the difference between the VCO output clock frequency and a reference frequency decreases to within a predetermined threshold, and the unlocked coarse control loop employs the voltage range monitoring logic to change the VCO frequency-voltage characteristic when the VCO's fine control voltage leaves a predetermined range. Other aspects are a transceiver (including at least two receiver interfaces and a transmitter interface) implementing a clocking scheme employing no more than three PLLs for clock generation, and a transceiver having a multi-layered receiver interface including digital circuitry and a single clock-generating PLL (an analog PLL for generating a multiphase clock to be shared by all layers of the receiver interface). Each receiver interface layer performs blind oversampling on a different received signal using the multiphase clock and the digital circuitry includes multilayered digital phase lock loop circuitry which receives the oversampled data.

A clock generator including a frequency multiplier, a phase lock circuit and a frequency divider. The frequency multiplier generates a frequency multiplied clock by multiplying the frequency of an input clock. The phase lock circuit detects a phase difference between the input clock and a frequency divided clock, and generates, by delaying the frequency multiplied clock by an amount corresponding to the phase difference, a phase-locked clock with its phase locked with the input clock. The frequency divider detects in every fixed cycle a particular pulse of the phase-locked clock, and generates the frequency divided clock by dividing the phase-locked clock with reference to the particular pulse of the phase-locked clock. In particular, the frequency divider detects the particular pulse immediately previous to a falling edge of the input clock. This can reduce the phase difference between the input clock and the phase-locked clock, and hence to solve a problem of a conventional clock generator in that a delay time of a digital delay line in a phase lock circuit must be lengthened with a reduction in the multiplication number of the frequency multiplied clock, which requires a greater number of delay elements because of a large occupying area of the delay elements and a decoder, thereby increasing the circuit scale and cost of a chip to reduce the multiplication number of the frequency multiplied clock.

In a double data rate (DDR) counter and counting method used in, for example, an analog-to-digital conversion in, for example, a CMOS image sensor and method, a first stage of the counter generates a least significant bit (LSB) of the value in the counter. The counter includes at least one second stage for generating another bit of the value in the counter. An input clock signal is applied to a data input of the first stage and a clock input of the second stage.

A signal generator circuit includes a controller adapted to generate a divide value in accordance with at least a first control signal, and a divider adapted to divide an output signal of the signal generator circuit by the divisor value. The controller is selectively operable in at least one of a plurality of modes in accordance with at least a second control signal. The controller is configured to calculate each of one or more new divide values so as to vary a frequency of the output signal in accordance with at least one of the first and second control signals. The controller is configured to switch between operational modes and / or switch between divide values, the switching between operational modes and / or divide values being performed in such a manner so as to substantially eliminate discontinuities in the frequency of the output signal.

A clock generation system for generating a first-, a second-, and a third-reference frequency clocks having respective frequencies having predetermined ratios to the reference frequency of a reference clock, using PL circuits in such a way that the clocks have sufficient S / N ratios in spite of the S / N ratio limitation by the noise floor. A first reference frequency clock is supplied to a first PLL circuit to generate an intermediate-frequency clock having an intermediate frequency having a predetermined ratio to the reference clock. The intermediate-frequency clock is supplied to a second and a third PLL circuits to generate a second and a third reference frequency clocks having frequencies respectively having a second and a third ratios to the intermediate frequency, respectively.

A direct digital frequency synthesizer having a multi-modulus divider, a numerically controlled oscillator and a programmable delay generator. The multi-modulus divider receives an input clock having an input pulse frequency fosc and outputs some integer fraction of those pulses at an instantaneous frequency fVp that is some integer fraction (1 / P) of the input frequency. The multi-modulus divider selects between at least two ratios of P (1 / P or 1 / P+1) in response to a signal from the numerically controlled oscillator. The numerically controlled oscillator receives a value which is the accumulator increment (i.e. the number of divided pulse edges) required before an overflow occurs that causes the multi-modulus divider to change divider ratios in response to receiving an overflow signal. The numerically controlled oscillator also outputs both the overflow signal and a delay signal to the delay generator that further controls the frequency of the multi-modulus divider output signal (Vp) to provide an output signal (VD) with an fout that has improved phase and timing jitter performance over prior art direct digital frequency synthesizer architectures.

An on-chip clock multiplier for outputting a fast clock that is approximately a predetermined multiple n of a slow clock. The multiplier utilizing a high-speed oscillator to generate a high-frequency base signal. A lower frequency signal is generated using the high-frequency base signal as a function of the output of a rollover counter that counts from a seed value to a terminal value. A saturation counter is used to determine whether no more than n pulses of the lower frequency signal occur within a single cycle of the slow clock. If not, the lower frequency signal is iteratively slowed by changing the seed value until no more than n pulses of the lower frequency signal occur within a single cycle of the slow clock. When this iteration is done, the fast clock having a frequency that is approximately n times the frequency of the slow clock is output.

A power supply is provided. The power supply is comprised of a first power module, a second power module, and a controller. The first power module is capable of delivering a first preselected amount of power. The second power module is capable of delivering a second preselected amount of power. The first and second power modules are coupled together to be capable of delivering an aggregate amount of power related to the first and second preselected amounts of power. The controller is adapted to selectively enable the first and second power modules to make power available in one of the first preselected amount, the second preselected amount, and the aggregate amount.

A distributed charge pump system uses a delay element and frequency dividers to generate out of phase pump clock signals that drive different charge pumps, to offset peak current clock edges for each charge pump and thereby reduce overall peak power. Clock signal division and phase offset may be extended to multiple levels for further smoothing of the pump clock signal transitions. A dual frequency divider may be used which receives the clock signal and its complement, and generates two divided signals that are 90° out of phase. In an illustrative embodiment the clock generator comprises a variable-frequency clock source, and a voltage regulator senses an output voltage of the charge pumps, generates a reference voltage based on a currently selected frequency of the variable-frequency clock source, and temporarily disables the charge pumps (by turning off local pump clocks) when the output voltage is greater than the reference voltage.

An injection-locked frequency divider (ILFD) can go beyond simple frequency division by an even number. In one embodiment, another differential pair of transistors is added to convert the injection signal into differential currents, which are mixed in the original transistor pair such as that of the conventional ILFD shown above. In another, a double-balanced ILFD structure includes multiple ILFD's which are independently tunable to allow phase differences other than quadrature.

A method of encrypting a data unit, the method comprising the steps of dividing the data unit into a series of data blocks, and for each data block, applying a block cipher function to a data block counter value to generate an encrypted block counter value, performing a logical operation to combine the encrypted block counter with the data block, and applying a block cipher function to the combined data.

A voltage level shifter formed by single-typed transistors comprises two input terminals, two power supply terminals, a plurality of thin-film transistors, and an output terminal. Another voltage level shifter formed by single-typed transistors comprises two input terminals, an output terminal, two power supply terminals, two input units, a first thin-film transistor, a disable unit, a feedback unit, and a second thin-film transistor. The voltage level shifters are formed by single-typed TFTs. When integrating the voltage level shifters into a substrate of a TFT display, the manufacturing processes are simplified. Besides, power is saved.

A shift register includes a plurality of stages connected to one another to sequentially generate output signals. Each of the stages has a plurality of output terminals, and each of the output terminals is connected to at least two gate lines and outputs a first output voltage alternately to the at least two gate lines to turn on thin film transistors.

A clock synchronization system and method avoids output clock jitter at high frequencies and also achieves a smooth phase transition at the boundary of the coarse and fine delays. The system may use a single coarse delay line configured to generate two intermediate clocks from the input reference clock and having a fixed phase difference therebetween. The coarse delay line may have a hierarchical or a non-hierarchical structure. A phase mixer receives these two intermediate clocks and generates the final output clock having a phase between the phases of the intermediate clocks. The coarse shifting in the delay line at high clock frequencies does not affect the phase relationship between the intermediate clocks fed into the phase mixer. The output clock from the phase mixer is time synchronized with the input reference clock and does not exhibit any jitter or noise even at high clock frequency inputs. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

A spread-period clock generator (SPC) counts basic clock pulses (XK) to generate output pulses (EQ) with varying periods, and has means (controlled by signal QS) for switching between a first mode, in which counting is carried out in response to the leading edges of the basic clock pulses (CK), and a second mode, in which counting is carried out in response to the trailing edges of the basic clock pulses (CK). Accordingly, if mode switching (signal QS) is carried out during a counting operation, the counting period is altered by a portion of a basic clock period (CK). Thus, the number of different periods of the output pulses can be increased without increasing the basic clock frequency (input WC, signal LK, CK).

Present-day single or multiple fractional phase-locked loop frequency synthesizers are not phase coherent for they use a digital accumulator modulo a number P with a variable increment K, whose state is a function of the history of the change in values that have been imposed on the increment. This lack of phase coherence rules out the use of these synthesizers in certain fields such as that of Doppler radars. A novel type of single or multiple fractional phase-locked loop frequency synthesizer that is coherent in phase is proposed herein. This type of synthesizer comprises one or more counters with an increment of one, having their rate set by the reference oscillator of the synthesizer and being used in phase memories to enable changes in the increment or increments following a change in the fractional division ratio at instants that are synchronous with the reference oscillator.

A digital wavetable audio synthesizer is described. A synthesizer volume generator, which has several modes of controlling the volume, adds envelope, right offset, left offset, and effects volume to the data. The data can be placed in one of sixteen fixed stereo pan positions, or left and right offsets can be programmed to place the data anywhere in the stereo field. The left and right offset values can also be programmed to control the overall volume. Zipper noise is prevented by controlling the volume increment. A synthesizer LFO generator can ad LFO variation to: (i) the wavetable data addressing rate, for creating a vibrato effect; and (ii) a voice's volume, for creating a tremolo effect. Generated data to be output from the synthesizer is stored in left and right accumulators. However, when creating delay-based effects, data is stored in one of several effects accumulators. This data is then written to a wavetable. The difference between the wavetable write and read addresses for this data provides a delay for echo and reverb effects. LFO variations added to the read address create a chorus and flange effects. The volume of the delay-based effects data can be attenuated to provide volume decay for an echo effect. After the delay-based effects processing, the data can be provided with left and right offset volume components which determine how much of the effect is heard and its stereo position. The data is then stored in the left and right accumulators.

Clock signals are supplied, with a phase shift of 1 / n cycles between adjacent clock signals. A data acquisition unit acquires serial data at a timing of each of the clock signals. A phase detection unit detects the phase of the transition edge of the serial data using n bits of data. An effective bit number determination unit determines the effective bit number, which is the number of bits to be acquired, based upon the phase of the transition edge of the serial data in the current data-bit acquisition step and the phase of the transition edge of the serial data in the previous data-bit acquisition step. A data-bit output unit outputs the effective bit number of the bits of data acquired at a timing of each clock signal having a predetermined phase relation with the transition edge of the serial data.

The provided fractional frequency divider includes a divider controlling unit for generating a divider selection signal in response to a dual-edge triggering of an input signal and a frequency dividing unit coupled to the divider controlling unit for dividing the frequency of the input signal by one of an integer and a fractional dividers in response to the dual-edge triggering and the divider selection signal to generate the output signal of the fractional frequency divider. An operation of the frequency dividing unit is not suppressed when the integer divider is employed, the operation of the frequency dividing unit is not suppressed for a period of the input signal and is suppressed for half of that period, and this cycle is kept on recurring when the fractional divider is employed. The fractional-n PLL having the fractional frequency divider is also provided.

Disclosed is a high-efficiency phase shift modulation method suitable for use in a traditional DC / AC single-phase full-bridge inverter. In this method, phase-shifted signal timing is used to modulate a duty cycle so that a power transistor is operated in a zero voltage switching state. As such, noises and switching loss of a switching device when turned on or off, may be reduced and thus efficiency of the inverter may be promoted. With this high-efficiency phase shift modulation method, at least the following advantages may be achieved: lower switching stresses, lower switching losses and thus increased conversion efficiency, lower electromagnetic interferences (EMIs) and no additional circuit required and thus easier realization of a controller for the inverter.

A divider is disclosed herein. The divider includes a sequence of divide stages programmably coupled to provide a variety of divide ratios. The divider also includes one or more multiplexers to feedback the output of a divide stage to the input of a divide stage earlier in the sequence of divide stages. The divider may also include duty cycle correction circuitry and self correction logic to correct abnormal logic states. The divide stages can operate in synchronism with each other. Multiplexer functionality, self correction circuitry functionality, and divide stage functionality may be implemented in a combination latch circuit.

Some embodiments of the invention provide a configurable integrated circuit (“IC”). The configurable IC includes a set of configurable logic circuits for configurably performing a set of functions. The configurable IC also includes a set of configurable routing circuits for routing signals to and from the configurable circuits. During several operational cycles of the configurable IC, a set of data registers are defined by the configurable routing circuits. These data registers may be used wherever a flip-flop can be used.