63 results about "Transition edge" patented technology

The invention relates to the technical field of semiconductor device preparation, and discloses a semiconductor annealing method and system and a storage medium, and the method comprises the steps: dividing a wafer structure into a central region, a transition region and an edge region, and calculating the central transition cooperative gain and the transition edge cooperative gain between the regions; the infrared pyrometers in all the areas are independently calibrated; sequentially setting PID control parameters of the central area, the transition area and the edge area based on the calibration result; and performing cooperative heating control on the wafer based on the set PID parameters until the annealing treatment is completed. According to the invention, the real-time following of the temperature of each region of the wafer is realized through master-slave cooperative gain control, the temperature uniformity among the regions of the wafer in the annealing process is improved, the problem of temperature lag or overheating of the edge region in the annealing treatment process is effectively solved, and the performance consistency of the semiconductor annealing process is ensured.

The invention discloses a time interval error jitter extraction method based on Hilbert transform, and relates to the field of high-speed data signal processing, and the method comprises the steps: firstly carrying out the statistics through a level histogram after a detected data signal is obtained, and determining a corresponding level judgment reference; secondly, performing Hilbert transform on the tested data signal to obtain time information of a jump edge of the tested data signal; an accurate code element rate of a measured data signal is extracted by adopting a coarse frequency estimation and fine frequency estimation method, and high-precision constant frequency clock recovery is carried out; according to the Hilbert transform-based time interval error jitter extraction method provided by the invention, a basis is provided for high-precision time interval error jitter, and jitter measurement is accurately carried out on a measured data signal.

The invention discloses a clock data recovery device, which is characterized in that a differential conversion module converts a serial signal into a single-bit signal, a delay module processes the single-bit signal to obtain a delay data signal, a sampling module performs sampling to obtain target sampling data, a jump edge detection module performs XOR operation on the target sampling data, and a clock data recovery module performs clock data recovery. The method comprises the following steps: obtaining current data hopping phase information, storing a mapping relation between a sampling phase and an ideal data hopping phase sequence by a storage module, determining the ideal data hopping phase sequence corresponding to the current sampling phase by a phase adjustment module, and adjusting the current data hopping phase information, a sampling phase deviation result is searched in the phase adjustment table based on the adjusted data hopping phase information, the current sampling phase is adjusted based on the search result, the optimal sampling phase is obtained, and a data clock recovery module carries out data and clock recovery on target sampling data based on the optimal sampling phase. Therefore, the clock to be recovered can be quickly locked, and the clock locking efficiency is improved.

The invention relates to the technical field of semiconductor integrated circuits, and discloses a bandwidth mismatch calibration system and method of a time-interleaved architecture ADC (Analog to Digital Converter). The system comprises N sub-ADCs, N bandwidth adjustment units and a controller. Firstly, a unified calibration signal is input into all sub-ADCs, and each sub-ADC samples the transition edge of the signal. The controller detects and determines a transition point error of each sub-ADC at the transition edge based on the sampling output of each sub-ADC. The controller calculates bandwidth adjustment code words for the corresponding sub-ADCs based on the difference between the error and a preset target value. The code word is used for driving the bandwidth adjusting unit to adjust the bandwidth of the corresponding sub-ADC, so that the bandwidths of all the sub-ADCs tend to be consistent through closed-loop feedback, and automatic and accurate calibration of bandwidth mismatch is realized.

The invention relates to the technical field of computer graphics, computational geometry and CAE (computer aided engineering) simulation, and discloses a fillet surface identification method, device and equipment based on a geometric model and a medium, the method comprises the following steps: carrying out virtual geometric processing on edges of all surfaces in the geometric model to obtain transition edges on an identification surface; determining the identification surface conforming to the surface fillet features as a transition surface; two connecting surfaces connected with the transition surface are selected, the two connecting surfaces are connected with the two ends of the transition edge respectively, the two connecting surfaces conforming to supporting surface features are determined to be a first supporting surface and a second supporting surface respectively, and the supporting surface features are unique features of the two supporting surfaces in fillet surface transition connection; and determining that a transition surface enabling the first supporting surface and the second supporting surface to be in smooth transition is a fillet surface. According to the fillet surface recognition method, the fillet surface in the geometric model can be quickly recognized only through the information of the edge, the recognition process is greatly accelerated, and the recognition is highly accurate.

The invention discloses a data transmission method for an optical computing chip and an upper computer, and the method comprises the steps: setting the frequency and initial level state of a serial clock signal by the upper computer during data transmission; the upper computer sends a serial clock signal to the optical computing chip by using a clock line; at the first jump edge of the serial clock signal, the sending end sends data in parallel through the plurality of data lines; at a second jump edge of the serial clock signal, the receiving end samples the data on the data line; the interval between the first jump edge and the second jump edge is a sampling interval, the sampling interval is N / 2 cycles, and N is a positive integer; wherein the jump edge is a position where the serial clock signal jumps from a high level to a low level or jumps from the low level to the high level. According to the invention, the transmission bandwidth of the existing serial interface protocol can be increased, and the data transmission efficiency of the optical computing chip and the upper computer is improved.

The invention relates to an efficient bridging device and a data recovery method. The bridging device comprises a protocol conversion engine; a read-write channel arbitration unit; a HyperBus read time sequence control unit; an edge detection unit is used for carrying out edge detection on an RWDS signal of the HyperBus by adopting a three-time oversampling technology, and outputting the RWDS signal to a data shaping unit by taking a next sampling point of a jump edge as a data effective bit; and a cross-clock domain synchronization unit. The data recovery method comprises the steps of oversampling, edge positioning, data extraction and dynamic shaping. According to the bridge and data recovery scheme, the traditional delay calibration step is omitted; the RWDS signal jitter tolerance is greater than or equal to 0.4 UI, and the bit error rate at-40 DEG C to 125 DEG C is less than or equal to 10 <-12 >; as a DDR alternative scheme, the standby power consumption is less than or equal to 50mW, and the cache extension delay is less than or equal to 100ns.

Cooling compression plate (1) for maintaining an intercellular space (2) in a directly cooled accumulator (3) during cell swelling, comprising at least: - a first exterior wall section (4); - a second exterior wall section (5); and - an intermediate section (6) which extends from a first transition edge (7) with the first outer wall section (4) and a second transition edge (8) with the second outer wall section (5) in a spring space (9) formed between the outer wall sections (4,5); wherein the cooling compression plate (1) is a single piece, and wherein at least one of the outer wall sections (4,5) forms at least one cooling channel (11) with an adjacent cell (12) in an assembled state, and wherein a spring effect can be provided between the first outer wall section (4) and the second outer wall section (5) by means of the intermediate section (6), characterized in that the cooling channel is formed in an outer side of the respective outer wall section, which is a side facing away from the spring chamber.

The application discloses a BMC PHY device with built-in dynamic TTL level jump edge control and improved EMI, and relates to the field of digital IC design.The BMC PHY device with built-in dynamic TTL level jump edge control and improved EMI comprises a current mirror power supply module, which is used for controlling whether 8 currents are powered by a current mirror, and the current size of the 8 currents is different by one time, so that 256 power supply currents are obtained; and then 256 different output voltages with rising slopes are obtained; and the current mirror grounding module is used for controlling whether the 8 currents are grounded by a current mirror, and the current size of the 8 currents is different by one time, so that 256 grounding currents are obtained. Compared with the prior art, the application has the beneficial effect that the application is based on the purpose of optimizing the chip-level EMI output by changing the slope, and the chip-level EMI output is greatly optimized by combining a digital communication channel (CC line) of a BMC PHY chip, a built-in high-precision current mirror network and a frequency jitter algorithm in different working modes.

The present invention provides a communication method for a single-line cascade circuit, a single-line cascade circuit and a display system. The method comprises: encoding a first data packet output by a main control unit in a BMC encoding mode, such that a transition edge will be generated at each joint between adjacent data bits of the first data packet; upon receiving an ith data packet, an ith driving unit detecting transition edges in non-preamble bit fields in the ith data packet; and when an initial transition edge in the ith data packet is detected, the ith driving unit outputting an (i+1)th data packet to an (i+1)th driving unit. In this way, it is ensured that the driving units transmitting signals can receive complete data packets, so as to achieve clock synchronization between adjacent driving units, thus eliminating the problems such as data catchup or data overwrite caused by asynchronous communication during cross-driving unit communication, and effectively increasing the success rate of communication in single-line cascade circuits.

An impedance measurement circuit includes a voltage controlled oscillator (VCO) configured to generate an oscillation signal according to a power voltage present on a power rail. The impedance measurement circuit includes an edge sampler coupled to the VCO and configured to generate a first signal sampling the oscillation signal based on a first transition edge of a first sampling clock signal. The impedance measurement circuit includes an accumulator coupled to the edge sampler and configured to accumulate the first signal for generating a second signal based on a third transition edge of a second sampling clock signal. The impedance measurement circuit includes a transition detector configured to generate the second sampling clock signal based on detecting a second transition edge of the first sampling clock signal.

The utility model provides a light instrument support with an arc-shaped transition edge, which comprises a support main body, the support main body is a strip-shaped plate body, the upper surface of the plate body is provided with an L-shaped notch, the lower surface of the plate body is provided with two notches, and the two notches positioned on the lower surface are respectively a first notch and a second notch. The first notch is a rounded rectangular notch, the second notch is a notch of a trapezoid structure, and the forming position of the first notch is opposite to the forming position of the L-shaped notch; reinforcing seats are installed on the back face of the plate body and arranged at the two ends of the plate body and the ends of the L-shaped notches respectively, each reinforcing seat comprises an arch-shaped bottom plate, the two ends of each arch-shaped bottom plate are fixed to the back face of the plate body respectively, the upper surface of each arch-shaped bottom plate is a plane, a supporting column is fixed to the upper surface of each arch-shaped bottom plate, and a rubber sealing layer is arranged on one side of each supporting column. The thickness of the sealing layer is gradually increased from top to bottom, and the top ends of the supporting columns are higher than the end of the plate body.

The invention discloses a signal receiving method, a signal receiving device and a communication system. The signal receiving method comprises the steps that a command feedback signal is received, and the command feedback signal comprises a start bit and an information bit behind the start bit; generating a detection signal based on the command feedback signal, the detection signal comprising a plurality of detection windows opened after an end position of the start bit, the plurality of detection windows being in one-to-one correspondence with a plurality of jump edges of the information bit, the position of the (n + 1) th detection window is determined according to the jump edge detected in the nth detection window, and n is a positive integer. According to the technical scheme, the position of the (n + 1) th detection window is determined through the jump edge detected in the nth detection window, so that the offset of the detection window and the jump edge can be reduced, the offset of the detection window cannot be accumulated, and the data receiving success rate is greatly improved.

The present invention provides a Manchester decoding method for cross-time domain communication with correctable errors, including: a decoding unit, a data storage unit, an error detection unit and a CRC check unit; the decoding unit samples the serially-incoming Manchester code, and decodes it using the level edge and detection time method, and after decoding, sends a flag bit and data to the storage unit for storage; the error detection unit detects the frame header data stored in the storage data unit, and sends the flag bit to the decoding unit when the data is inconsistent, and performs decoding adjustment. Compared with detecting a single level or level jump edge, the method of the present application combines the level edge and detection time method, effectively solves the problem of cross-time domain clock data width compression, can quickly correct errors when powering on, find the correct start bit for decoding, and realizes rapid error correction when powering on; and through the dual judgment of the frame header and CRC, the correctness of the decoded binary code is guaranteed.

The display panel comprises a substrate main body and frame sealing glue, the substrate main body comprises a first substrate and a second substrate which are oppositely arranged, and the substrate main body is provided with a first substrate edge, a second substrate edge and a third substrate edge which are adjacent in sequence; the frame sealing glue is connected between the first substrate and the second substrate in a sealed mode and is provided with a first glue frame edge, a second glue frame edge and a third glue frame edge which are sequentially adjacent, a third transition edge is connected between the first glue frame edge and the second glue frame edge, and a fourth transition edge is connected between the second glue frame edge and the third glue frame edge. The distance between the edge of the first rubber frame and the edge of the first substrate is larger than the distance between the edge of the third rubber frame and the edge of the third substrate, the curvature radius of the third transition edge is R1, the curvature radius of the fourth transition edge is R2, and R1 is smaller than R2. Therefore, the high-temperature and high-humidity reliability and the anti-falling performance of the display panel can be improved, and the quality of the display panel is improved.

The invention discloses a synchronization method for servo communication and motor control of an EtherCAT bus, and the method comprises the steps: building a mapping relation between an auxiliary timer and a control period of a PWM signal generator, and mapping a physical synchronization signal Sync0 of the EtherCAT bus into an external trigger source of an input capture unit; when an effective jump edge of a physical synchronization signal Sync0 is detected in response, an input capture unit is used for locking a current instantaneous count value of an auxiliary timer into a capture register in real time under the condition that software interruption intervention is not carried out, and a reference timestamp is formed; the method comprises the steps of reading a reference timestamp in an interrupt service of a servo control period, calculating a phase offset based on a target phase relationship between the reference timestamp and a physical synchronization signal Sync0, and dynamically modulating a reloading value of a PWM signal generator in a next control period according to the phase offset.

The present application relates to the technical field of computer graphics, computational geometry and CAE simulation, and discloses a fillet surface recognition method and device based on a geometric model, equipment and a medium, the method comprises the following steps: performing virtual geometry processing on all edges of the surfaces in the geometric model to obtain transition edges on the recognition surface; determining the recognition surface meeting the fillet surface feature as a transition surface; selecting two connecting surfaces connected with the transition surface, and the two connecting surfaces are connected with two ends of the transition edge respectively, determining that the two connecting surfaces meeting the support surface feature are a first support surface and a second support surface respectively, and the support surface feature is a feature specific to the two support surfaces connected with the fillet surface; and determining that the transition surface making the first support surface and the second support surface smoothly transition is a fillet surface. The fillet surface recognition method can quickly recognize the fillet surface in the geometric model only through the edge information, greatly speeds up the recognition process, and is highly accurate in recognition.

This invention discloses a method and system for calculating the number of revolutions in a BLDC motor based on dynamic time window verification, belonging to the field of motor control technology. The method includes: acquiring Hall sensor signals from the BLDC motor and performing edge detection and debouncing processing to generate Hall transition edges; obtaining the current period by measuring the time interval between adjacent valid Hall transition edges based on the system clock; calculating the lower and upper bounds of the dynamic time window based on the current period and a dynamic adjustment coefficient; and performing three-level pulse discrimination based on the relationship between the arrival time of the Hall transition edge and the dynamic time window: triggering revolution count accumulation when the pulse is determined to be valid, blocking the pulse when it is determined to be a glitch pulse, and generating a compensation pulse and triggering revolution count accumulation when the pulse is determined to be lost. This invention solves the problems of insufficient anti-interference capability and lack of signal loss compensation mechanism in existing technologies under variable speed conditions and strong electromagnetic interference environments, significantly improving the accuracy and reliability of revolution count calculation.

The present invention discloses a signal demodulation circuit and a digital isolator. The signal demodulation circuit includes an amplification module and a clock detection module; the amplification module receives a first modulation signal, is used to amplify the first modulation signal, and outputs a second modulation signal; the clock detection module is connected to the amplification module, and is used to output a valid level signal according to the transition edge of the clock signal when the second modulation signal has a clock signal, and output an invalid level signal when the second modulation signal does not have the clock signal, thereby forming a demodulation signal, wherein the frequency of the clock signal is the same as the frequency of the carrier signal of the second modulation signal. The structure of the signal demodulation circuit provided by the present invention is relatively simple.

The utility model relates to a steel door leaf panel and cover edge integrated forming device which comprises a transition edge machining device and a cover edge machining device. The transition edge machining device comprises a first cutter upper die component and a first cutter lower die component. The cover edge machining device comprises a second cutter upper die component, a second cutter lower die component and a third cutter lower die component. A hammering head is arranged at the bottom of the lower die part II; a table top is arranged in the middle of the third cutter lower die component. The second cutter lower die component and the third cutter lower die component are connected in a sliding mode in the vertical direction. The device has the beneficial effects that the mounting positions of the lower die component I and the cutter lower die component III can be exchanged, so that the mounting efficiency and the interchangeability of the device are improved; the second cutter upper die component, the second cutter lower die component and the third cutter lower die component are applied to different machining stages and located in the cover edge machining device, and the deployment efficiency of the device is improved. The transition edge machining device and the cover edge machining device do not interfere with each other and can operate simultaneously, and the production efficiency is improved.

This invention relates to the field of waveguide gas laser technology, specifically to a method and device for preferentially controlling the electrode electric field to prioritize the lowest-order waveguide mode through coating, comprising the following steps: S1: determining the beam waist position of the laser resonator; S2: preparing an insulating coating on the surface of the waveguide laser electrode plate corresponding to the beam waist position; S3: performing a gradient transition edge treatment on the insulating coating; S4: constructing an impedance matching compensation network at the electrode feed end in the insulating coating region. This invention, by setting an insulating coating, achieves localized reduction of the electric field intensity in the beam waist region; simultaneously, by constructing an impedance matching compensation network, it accurately compensates for the capacitance effect introduced by the coating, and through dynamic monitoring and adjustment, ensures that the standing wave ratio and discharge voltage fluctuations are within a minimal range, guaranteeing effective coupling of RF power and uniform and stable discharge, thereby improving the overall efficiency and reliability of the device.

The present invention provides a detection circuit and a detection method for a MEMS resonator. The detection circuit includes: a MEMS resonator; a charge amplifier, whose output terminal outputs a resonance induction signal; a rectifier, configured to flip or cut off the negative value part in the resonance induction signal to obtain a rectified resonance induction signal; an integrator, configured to integrate the rectified resonance induction signal with a set integration time as a period; a sampling circuit, sampling the output of the integrator to obtain an integration sampling value; a comparator, obtaining a digital square wave signal; a counter, which is triggered by a predetermined transition edge of the digital square wave signal for counting, and the count value per unit time is denoted as N1; a processing unit, which calculates the natural resonance frequency F0 based on the count value N1 and the unit time, and calculates the quality factor Q based on the natural resonance frequency F0 and the integration sampling value. In this way, the resonance frequency and quality factor of the MEMS resonator can be measured quickly and accurately.

The present invention relates to the technical field of semiconductor device preparation, and discloses a semiconductor annealing method, system and storage medium, including: dividing the wafer into a central area, a transition area and an edge area according to the wafer structure, and calculating the central transition cooperative gain and the transition edge cooperative gain between the areas; independently calibrating the infrared pyrometers in each area; adjusting the PID control parameters of the central area, the transition area and the edge area in turn based on the calibration results; and performing cooperative heating control on the wafer based on the adjusted PID parameters until the annealing process is completed; the present invention realizes real-time tracking of the temperature of each area of ​​the wafer through master-slave cooperative gain control, thereby improving the temperature uniformity between the various areas of the wafer during the annealing process, effectively solving the problem of temperature lag or overheating of the edge area during the annealing process, and ensuring the performance consistency of the semiconductor annealing process.

The application discloses a kind of customer data processing method and system, it is related to data processing technical field.The method includes the state transition diagram of the power consumption event sequence of each regional power grid customer is constructed;Two-way state structure is constructed to state transition diagram, based on maximum transition probability path extraction atypical state sequence, and mark as regional task key frame state sequence;Collaborative state mapping matrix is constructed, and distributed state abnormal fragment with associated aggregation characteristics is identified;The time sequence coding of task key frame state sequence corresponding to the state abnormal fragment with associated aggregation characteristics in collaborative state mapping matrix is carried out, and structured feature set is generated;The clustering boundary of state node in state transition diagram and transition edge weight are revised based on structured feature set.

The present application relates to a signal demodulation method, apparatus, computer equipment, storage medium and product. The method comprises: receiving a target transmission signal; wherein the target transmission signal is a signal generated by a collision between a first transmission signal and a second transmission signal that do not completely overlap in the time domain during transmission based on a time slot ALOHA protocol, and the first transmission signal and the second transmission signal are signals encoded by a target coding method, and the target coding method is used to encode a level signal corresponding to a code element into two different level signals; determining candidate transition edges of the target transmission signal; selecting the first transition edge of the first transmission signal and the second transition edge of the second transmission signal from the candidate transition edges according to the code element period corresponding to the target coding method; and demodulating the target transmission signal according to the level change information of the target transmission signal at the first transition edge and the level change information at the second transition edge. The use of this method can improve resource utilization and signal transmission efficiency.

This invention relates to a testing method, system, computer device, and storage medium for electronic devices. The method includes: receiving user-defined test parameters through a graphical configuration platform; generating a structured test file based on the test parameters, the structured test file including a directed graph model consisting of nodes and transition edges to describe the test process, wherein the nodes indicate test states and / or test actions, and the transition edges indicate state triggering conditions; loading and interpreting the structured test file, generating standardized action instructions based on the interpretation results, converting the standardized action instructions into a control protocol for a specific physical test device, driving the electronic device to perform corresponding test actions according to the nodes of the structured test file, and transferring test states according to the transition edges defined in the directed graph model. This invention enables streamlined and automated testing of electronic devices.

This application provides example phase detectors, methods thereof, clock and data recovery circuits, and electronic devices. One example phase detector includes a data integrator, coupled to a sampling clock end and configured to integrate input data based on a signal at a sampling clock end, a data sampling comparator, configured to perform sampling comparison between output of the data integrator and a specified value, a transition edge integrator, coupled to the sampling clock end and configured to integrate on the input data based on the signal at the sampling clock end, a transition edge sampling comparator, configured to perform sampling comparison between output of the transition edge integrator and the specified value, and a logic processor, configured to perform logic processing on a comparison result of the data sampling comparator and a comparison result of the transition edge sampling comparator, and output a lead or lag processing result.

The invention relates to a high-precision time synchronization method between devices, which comprises the following steps that: a master node broadcasts own serial data code streams in a broadcast mode, and receives serial data code streams returned by slave nodes in a time-sharing manner; the master and slave nodes receive and measure the data message segment of the serial data code stream to obtain the master node sending starting time T1, the master node receiving time T4, the slave node sending starting time T3 and the slave node receiving time T2; a data jump edge of a serial data code stream clock phase measurement section is accurately measured by adopting a phase shifting function of a clock phase-locked loop, and the time measurement resolution is improved by compensating the receiving time T4 of a master node and the receiving time T2 of a slave node; calculating a time deviation value offset between the slave node and the master node according to the master-slave receiving and transmitting time; and adjusting the local clock of the slave node and the phase of the slave node according to the calculation result of the time offset, thereby realizing subnanosecond high-precision time synchronization between the slave node and the master node of the whole network.

The present invention relates to a clock taming and maintenance method, system, device and medium. The method comprises: obtaining a clock signal waveform of a clock generator; taking the transition edge of the pulse signal waveform as a reference, respectively measuring the time difference between a plurality of consecutive transition edges in the clock signal waveform and the transition edge of the pulse signal waveform; calculating the output frequency of the clock generator by the time difference of the transition edges; and adjusting the frequency of the clock generator by calculating the difference between the output frequency and the expected frequency, thereby outputting a tamed clock signal. The present invention does not require the introduction of an additional reference signal, can quickly obtain the time difference of the clock signal, and reduces the taming time of the clock generator, thereby being able to tame the frequency more quickly and improve the stability and accuracy of the clock output.

A communication method, apparatus and system, which can be applied to the technical field of communications, the method comprising: a reader-writer generates a first signal, the first signal being used for determining at least one of the following items: an initial position of a data signal, or a length of a chip in the data signal, the first signal being located before the data signal, and the first signal being adjacent to a first CP; wherein the first CP and the first chip have the same level, and the first chip is a chip adjacent to the first CP in the first signal; and the reader-writer sends the data signal to the equipment. According to the communication method provided by the invention, the influence of the CP on the detection accuracy of the jump edge in the indication signal can be reduced on the premise of ensuring relatively low power consumption of the A-IoT equipment, so that the error rate when a reader-writer transmits data to the A-IoT equipment is reduced.