244results about "Gated amplifiers" patented technology

Disclosed is a technology related to a low noise amplifier applied between an RF receiver and an RF switch. A phase difference matching circuit having the same phase difference as a positive gain amplifier is added to an output terminal of an attenuator of a low noise amplifier having a variable gain switching structure. In addition, a variable impedance circuit connected to an output terminal of the positive gain amplifier and an output terminal of a phase difference matching unit to finely adjust the phase difference of each output terminal may be further included.

An impedance matching network for a radio frequency (RF) transmission system can include first port for coupling to a first transistor differential pair. The network can further include a second port for coupling to a second transistor differential pair. The network can further include a matching network connected to the first port and the second port, the matching network comprised of a pair of coupled lines. Other aspects are described.

Circuits and methods include amplification circuitry coupled to a plurality of input signal paths and an output signal path and a unified signal path combining a feedback path couplable between a feedback node in the output signal path and the input signal path via a plurality of input switches and a passive gain path couplable between the feedback node in the output signal path and one or more input signal paths through the input switch. The circuit may include a first capacitor and a variable resistor coupled in series and a second capacitor coupled in series with a feedback path switch and a power supply rejection resistor. The passive gain path may further include a shunt switch coupled in series between a plurality of bypass switches to form a T-switch. A fast charging switch may be configurable to couple a second capacitor to a reference potential during a state change of the unified signal path.

A radio-frequency module includes one or more first electronic components disposed on one main surface and one or more second electronic components disposed on another main surface. The one or more first electronic components include at least one of a filter whose passband includes a first band, a switch connected to the filter, a power amplifier connected to the filter, and a switch connected to the filter. The one or more second electronic components include at least one of a filter whose passband includes a second band in which the frequency of a harmonic wave of a signal in the first band is included, a switch connected to the filter, a low-noise amplifier connected to the filter, and an inductor connected to a path that forms a connection between the first low-noise amplifier and an antenna connection terminal.

Disclosed in the present invention are a low-loss radio frequency transceiving front-end module and an electronic device. The radio frequency transceiving front-end module comprises at least one PA transmitting path, at least one LNA receiving path, at least one bypass receiving path, and / or at least one bypass transmitting path; the at least one PA transmitting path or the at least one LNA receiving path is directly connected to an ANT port of an antenna, and the PA transmitting path or the LNA receiving path comprises at least one switch connected in parallel to the ground; the remaining PA transmitting path or LNA receiving path is connected to the ANT port of the antenna by means of a radio frequency switch.

A radio frequency power amplifier includes a power amplification transistor and a gate bias circuit. The gate bias circuit includes a VHb terminal connected to a high voltage power supply for bias, a VLb terminal connected to a low voltage power supply for bias, an enable terminal that receives an enable signal, an enable transistor and a voltage dividing resistor that are connected in series and connected between the VHb terminal and the VLb terminal, a driver that outputs a voltage to a control terminal of the enable transistor, and a gate bias output terminal that outputs, as a gate bias voltage, a divided voltage generated by the voltage dividing resistor. When an OFF signal is received as the enable signal, the driver causes the enable transistor to operate in a first operating area that is not a cutoff region.

A high voltage driver is provided that includes a PMOS stack of transistors arranged in series between a power supply node and an output node. The high voltage driver also includes an NMOS stack of transistors arranged between the output node and ground.

A transistor device package includes a component assembly comprising an interconnect structure, a transistor die having a front surface including gate, drain, and source terminal on a first surface of the interconnect structure, and one or more passive electrical components electrically coupled to the gate, drain, and / or source terminal by the interconnect structure. A thermally conductive flange is attached to a back surface of the transistor die, which is opposite the front surface, by a conductive adhesive. Respective patterns of the conductive adhesive are provided on the first surface of the interconnect structure, and least one of the respective patterns of the conductive adhesive provides an input, output, or ground signal path for the transistor device package. Related fabrication methods are also discussed.

A communication device includes a power amplifier that generates power signals according to one or more operating bands of communication data, with the amplitude being driven and generated in output stages of the power amplifier. The final stage can include an output passive network that suppresses suppress an amplitude modulation-to-phase modulation (AM-PM) distortion. During a back-off power mode a bias of a capacitive unit of the output power network component can be adjusted to minimize an overall capacitance variation. A output passive network can further generate a flat-phase response between dual resonances of operation.

The present disclosure relates to power amplifier circuitry with temperature-controlled biasing and protective shutdown based on die temperature. A first amplifier die and second amplifier die each have their own power amplifiers and temperature-sensing elements. An amplifier controller die controls both power amplifier dice, generating a bias current that can be coupled to either power amplifier die to activate the power amplifier of one or the other die. The bias current magnitude is updated in response to decreased temperature-dependent voltage from the inactive die which is at an average temperature of both dice. A switch control logic also selects the temperature-dependent voltage of the temperature-sensing element of the active die to input to a comparator that outputs a thermal shutdown signal if the temperature of the active die approaches a damaging level, and the switch control logic controls opening of switches connected to the bias output terminal to prevent damage.

Methods and devices to mitigate the detrimental effects of highly capacitive output routes of multiple gain low noise amplifiers on the overall performance of the circuit are disclosed. The disclosed methods and devices implement the same inductive element across the output load in both the low gain and high gain operational modes. Furthermore, such devices implement switches to control the selection of different signal paths for the high gain and low gain mode. The implemented switches are also used to selectively adjust the isolation of the output stage of the LNA.

Low noise amplifier (LNA) architectures addressing the parasitic challenges in the circuit in order to meet the high gain and bandwidth requirement at higher frequencies are disclosed. The described LNAs include cascode transistors and implement a tunable inductor (Lgate) in series with the gate terminal of a transistor (M2) of the cascode transistors to improve the gain and bandwidth of the LNAs and achieve high gain wideband switching LNAs.

A power amplifier (100) includes an input end (RFIN), an output end (RFOUT), a first amplification circuit (PA1), a second amplification circuit (PA3), a bias circuit (BIAS3), a current detection circuit (110), and a first protection circuit (120). The first amplification circuit (PA1) includes a first signal input end (IN1) coupled to the input end (RFIN) and a first signal output end (OUT1). The bias circuit (BIAS3) outputs a bias current (IBIAS3) to the second amplification circuit (PA3). The current detection circuit (110) generates a digital control signal (VOCP) according to the bias current (IBIAS3). The first protection circuit (120) selectively reduces the radio frequency signal (RF) input to the first signal input end (IN1) according to the digital control signal (VOCP).

A radio frequency circuit including power amplifiers, a transformer having an input-side coil and an output-side coil, a bias circuit connected to the power amplifiers, an output terminal connected to one end of the output-side coil, an output terminal connected to another end of the output-side coil, a switch connected between the output terminal and a ground, a switch connected between the output terminal and a ground, a phase shift line having an input end connected to an output terminal of the power amplifier and an output end connected to one end of the input-side coil, and a phase shift line having an input end connected to an output terminal of the power amplifier and an output end connected to another end of the input-side coil.

An apparatus, including: a first amplifier including: a flipped voltage follower, and a source follower coupled in parallel with the flipped voltage follower; and a load coupled to an output of the first amplifier.

An amplifier circuit includes an input terminal; an output terminal; an FET 11 including a gate terminal g1, a drain terminal d1, and a source terminal s1; an FET 12 including a gate terminal g2, a drain terminal d2, and a source terminal s2; an FET 31 including a gate terminal g3, a drain terminal d3, and a source terminal s3; and LC parallel resonant circuits. The gate terminal g1 is connected to the input terminal, the drain terminal d1 is connected to the source terminal s2, the source terminal s1 is connected to the ground, the gate terminal g2 is connected to the drain terminal d3 and the LC parallel resonant circuit, the drain terminal d2 is connected to the output terminal and the LC parallel resonant circuit, the gate terminal g3 is connected to the source terminal s2, and the source terminal s3 is connected to the ground.

Disclosed is a semiconductor integrated circuit device including: a switching transistor; a terminal to receive a control signal from outside; and a control circuit that controls the switching transistor based on the control signal. The control circuit includes: a reference voltage source that generates a reference voltage from the DC voltage; a differential amplifier to receive the reference voltage and a voltage of the voltage output terminal, and output a voltage applied to a control terminal of the switching transistor; and a logic circuit that generates a signal to control an operation state of the differential amplifier based on the control signal. According to an output signal of the logic circuit, the differential amplifier controls the switching transistor to be on in response to the control signal being a first logic level, and to be off in response to the control signal being a second logic level.

Certain aspects of the present disclosure generally relate to an amplification circuit. The amplification circuit generally includes: a first amplification path (490) including a first amplification transistor (460) and coupled between an input node of the amplification circuit and an output node of the amplification circuit; and a second amplification path (492) comprising a second amplification transistor (486) and coupled between the input node and the output node, where the second amplification path (492) further comprises an attenuator (452, 482, 480) coupled between the input node of the amplification circuit and a control input of the second amplification transistor (486).

In an embodiment, a system includes: an analog-to-digital converter (ADC); a transmitter path; a receiver path including a first amplifier including: an output coupled to the ADC, and a first high-pass filter; and a controller coupled to the transmitter path and to the receiver path, where the controller is configured to: cause a corner frequency of the first high-pass filter to increase from a first value to a second value, simultaneously or after causing the corner frequency of the first high-pass filter to increase, cause the transmitter path to be enabled, and after a first signal begins transmission in the enabled transmitter path, and during transmission of the first signal in the enabled transmitter path, cause the corner frequency of the first high-pass filter to decrease from the second value to the first value.

According to embodiments, an electronic device is provided. The electronic device may include: a processor; a radio frequency (RF) transceiver; a radio frequency front end (RFFE) module connected to the RF transceiver; an antenna connected to the RFFE module; a battery configured to provide a first voltage; and a power supply circuit configured to supply a second voltage for a power amplifier (PA) on the basis of the first voltage. The RFFE module may include a control circuit for controlling the PA bias in the RFFE module and at least one switch in the RFFE module, and a switching circuit for the control circuit.

The invention relates to an output stage of a digital-to-analog converter. An example apparatus includes: a first transconductance amplifier (202); an amplifier (204), a first input of the amplifier (204) coupled to a first output of the first transconductance amplifier (202), a second input of the amplifier (204) coupled to a second output of the first transconductance amplifier (202); a resistor (206), a first terminal of the resistor (206) coupled to an output of the amplifier (204); and a second transconductance amplifier (208), a first input of the second transconductance amplifier (208) coupled to a second terminal of the resistor (206), a second input of the second transconductance amplifier (208) coupled to an output of the amplifier (204) and a first terminal of the resistor (206), a first output of the second transconductance amplifier (208) coupled to a first output of the first transconductance amplifier (202) and a first input of the amplifier (204), a second output of the second transconductance amplifier (208) is coupled to a second output of the first transconductance amplifier (202) and a second input of the amplifier (204).

An equalizer circuit in an envelope tracking (ET) integrated circuit (ETIC) is disclosed. The ETIC (26) is configured to generate an ET voltage based on a target voltage (VTGT) for amplifying a radio frequency (RF) signal(s). Since the ETIC has inherent impedance and group delay that can cause distortion in the ET voltage, an equalizer circuit (24) is provided in the ETIC to equalize the target voltage prior to generating the ET voltage. Specifically, the equalizer circuit generates an equalized target voltage to offset the inherent impedance and a modified target voltage to mitigate the group delay. Accordingly, the equalizer circuit can output a processed target voltage, which can include the equalized target voltage and / or the modified target voltage, for generating the ET voltage. As a result, it is possible to reduce distortion resulted from the inherent impedance and group delay, especially when the RF signal(s) is modulated in a wide modulation bandwidth.

In embodiments, an electronic device is provided. The electronic device includes a processor including processing circuitry, a radio frequency (RF) transceiver, a first power supply circuitry for providing a power amplifier with a first supply voltage, a second power supply circuitry for providing the power amplifier or another power amplifier with a second supply voltage, a first power path connected to the first power supply circuitry, a second power path connected to the second power supply circuitry, wherein a third supply voltage is provided through the third power path, a first switching circuitry configured to connect or not connect the third power path to the first power path, a second switching circuitry configured to connect or not connect the third power path to the second power path, and a radio frequency front end (RFFE) module, including the power amplifier, connected to the first power path and the second power path. The first switching circuitry is controlled to connect the first power path and the third power path while the first supply voltage is not provided to the power amplifier through the first power path. The second switching circuitry is controlled to connect the second power path and the third power path while the second supply voltage is not provided to the power amplifier through the second power path.

The disclosure relates to audio systems and methods with load impedance detection and current adjustment. An audio system (e.g., personal stage monitoring (PSM) receiver) may include an impedance detector that detects impedance of the connected load, and a current adjuster that provides an adjustable available current to the connected load based on the detected impedance. The current adjuster may be amplifier(s) (e.g., buffers) connected in parallel between an audio amplifier of the PSM receiver and the connected device. The current adjuster may adaptively adjust available current that may be provided / delivered to the connected device (e.g., when the connected device is a low-impedance load) and disable additional current made available to the connected device when the connected load is a high-impedance load. The impedance detector may be configured to measure the impedance of an unknown load in real time to facilitate the adaptive availability of the current by the current adjuster.

Radio frequency (RF) band switching in a power management integrated circuit (PMIC) is provided. Herein, the PMIC is configured to adapt a modulated voltage to amplify an RF signal for transmission in different RF bands. In embodiments disclosed herein, a band-switching circuit in the PMIC is configured to receive a band-switching indication to switch from a current RF band to a different RF band. Accordingly, the band-switching circuit can cause the PMIC to reload a corresponding set of parameters to thereby adapt the modulated voltage for the different RF band within a defined switching interval (e.g., < 5 µs). As a result, the PMIC can be flexibly configured to adapt the modulated voltage between multiple RF bands under ever stringent switching delay requirements.

This disclosure relates to amplifier circuitry for carrier aggregation. An electronic device may include a wireless circuit having a baseband processor, transceiver circuitry, a front-end module, and an antenna. The front-end module may include amplifier circuitry, such as a low-noise amplifier for amplifying received radio frequency signals. The amplifier circuitry is capable of operating in both non-carrier aggregation and carrier aggregation modes. The amplifier circuitry may include an input transformer coupled to multiple amplifier stages, such as a common-gate amplifier stage, a common-source common-gate amplifier stage, and a common-source amplifier stage. The common-gate amplifier stage may include a switch for selectively activating a set of cross-coupled capacitors to help maintain input impedance matching in both the non-carrier aggregation and carrier aggregation modes. The common-source amplifier stage may include an additional switch for activating and deactivating the common-source amplifier stage to help maintain gain in both the non-carrier aggregation and carrier aggregation modes.

Feedback methods and devices to reduce gain in RF amplifiers, more in particular LNAs, are disclosed. The described methods are based on providing feedback paths from the drain terminal of one of the LNA cascode transistors to the source terminal of the LNA input transistor, or from the gate terminal of the input transistor to the source terminal of the LNA input transistor. The disclosed methods can be combined with one another or with existing feedback methods to provide further flexibility and improved tradeoffs when designing LNAs for applications having different requirements.