43 results about "Gain stage" patented technology

According to an embodiment, a circuit is proposed for generating rate and quadrature demodulation signals, incorporating unidirectional hysteresis for negative edges. The circuit features a preliminary stage that amplifies the differential sinusoidal signal from gyroscopic proof mass oscillations; a gain stage for boosting this signal with adjustable hysteresis levels; an output stage delivering a full-swing square wave output; and a customizable offset component to deepen the drop in the non-inverting compared to the inverting signal for the third signal's falling edge.

The invention belongs to the technical field of digital-analog hybrid integrated circuits, and particularly relates to a high-precision low-power-consumption dynamic comparator circuit suitable for an SAR ADC (Synthetic Aperture Radar Analog to Digital Converter). The high-precision low-power-consumption dynamic comparator circuit is designed by adopting two-stage pre-amplification and a latch structure, a first-stage pre-amplification circuit A1 is a gain amplification stage, and a second-stage pre-amplification circuit A2 is a gain amplification stage; the effects of simplifying the circuit structure, reducing power consumption and eliminating kickback noise are achieved by adopting a dynamic operational amplifier of a cross-coupled load, the second-stage pre-amplification circuit A2 serves as an extra gain stage, an output signal from the first-stage pre-amplification circuit A1 can be quickly amplified by adopting a cross-coupled load structure, and the kickback noise is eliminated. The third-stage latch circuit A3 improves the speed of the comparator, the latch adopts a dynamic structure and is controlled by a dynamic clock, the latch does not work during resetting, and the static power consumption of the comparator is reduced.

According to an embodiment, a circuit is proposed for generating rate and quadrature demodulation signals, incorporating unidirectional hysteresis for negative edges. The circuit features a preliminary stage that amplifies the differential sinusoidal signal from gyroscopic proof mass oscillations; a gain stage for boosting this signal with adjustable hysteresis levels; an output stage delivering a full-swing square wave output; and a customizable offset component to deepen the drop in the non-inverting compared to the inverting signal for the third signal's falling edge.

A sensing circuit includes at least a first gain stage and a controller for controlling the operation of the first gain stage. The first gain stage includes an amplifier having at least one input and one output, and a feedback loop coupled between the input and the output of the amplifier. The feedback loop includes a first capacitor coupled between the input and the output of the amplifier, and a second capacitor having a first terminal coupled to the input of the amplifier through a first switch and a second terminal coupled to the output of the amplifier through a second switch. The second capacitor is configured to be coupled in parallel to the first capacitor during a first portion of a measurement cycle, and disconnected from the first capacitor during a second portion of the measurement cycle.

A multi-gain stage circuit is arranged to receive an input signal to generate an output signal, and includes a first gain stage, a second gain stage, a gain control circuit, and a calibration circuit. The second gain stage is connected in series with the first gain stage, and the second gain stage generates the output signal. The gain control circuit controls the first gain stage to have a first gain value such that the output signal is regarded as a product of a gain value of the second gain stage and an offset voltage of the second gain stage. The calibration circuit calculates the offset voltage of the second gain stage according to the output signal, and calibrates the second gain stage according to the offset voltage of the second gain stage calculated by the calibration circuit.

A charging case for a pair of wireless earphones, the charging case comprising: a housing having a peripheral wall that defines a shell and one or more audio openings formed through the peripheral wall; a frame insert coupled to the housing and extending into the shell, the frame insert having one or more insert walls that define first and second pockets sized and shaped to accept first and second wireless earphones, respectively; wherein the one or more insert walls cooperate with the housing peripheral wall to define a interior cavity within the charging case; a lid coupled to the housing and operable between a closed position in which the lid covers the first and second pockets and an open position in which the first and second pockets are exposed; a rechargeable battery disposed within the interior cavity; a speaker disposed within the interior cavity and aligned to emit sound through the one or more openings; and circuitry coupled to the battery and the speaker and configured to: initiate playing an audio asset on the speaker at a first gain level; while continuing to play the audio asset, increasing the gain level of the speaker from the first gain level to a final gain level by repeating a sequence of measuring a system load on the battery and increasing the gain level of the speaker until the measured system load reaches a threshold level; after the measured system load reaches the threshold level, setting the gain level of the speaker at the final gain level and continuing playing the audio asset with the gain set at the final gain level.

Circuit for maximizing the dynamic range in a digital-to-analog signal path (100; 200; 300; 400), comprising: a. an input for receiving an input signal (110; 201; 301; 401); b. a first gain stage (120; 210; 330; 445) coupled to the input, the first gain stage (120; 210; 330; 445) having a first gain setting; c. a second gain stage (140; 230; 370; 460) coupled to the first gain stage (120; 210; 330; 445), the second gain stage (140; 230; 370; 460) having a second gain setting, the second gain stage (140; 230; 370; 460) having an analog gain stage and the second gain setting having an analog gain setting; d. a controller (150; 250; 320; 420) for dynamically selecting the first gain setting to maximize the first gain setting without clipping the input signal and for selecting the second gain setting to achieve a desired signal path gain; and e. an output coupled to the second gain stage (140; 230; 370; 460) for transmitting an output signal (235) having the desired overall signal path gain.

A method, computer program product, and computing system for receiving a signal from each microphone of a plurality of microphones, thereby defining a plurality of signals. One or more inter-microphone gain-based augmentations can be performed on the plurality of signals, thereby defining one or more inter-microphone gain-augmented signals. Performing one or more inter-microphone gain-based augmentations on the plurality of signals can include applying a gain level from a plurality of gain levels to the signal from each microphone. Applying a gain level from a plurality of gain levels to the signal from each microphone can include applying a gain level from a predefined range of gain levels to the signal from each microphone. Applying a gain level from a plurality of gain levels to the signal from each microphone can include applying a random gain level from a predefined range of gain levels to the signal from each microphone.

Circuitry for processing an input signal from a sensor, the circuitry comprising: an input configured to receive the input signal; bias circuitry configured to apply a bias to the input signal to obtain a biased input signal; a gain stage configured to apply a gain to the biased input signal to obtain an amplified input signal; an analog-to-digital converter (ADC) configured to convert the amplified input signal to a digital output signal; wherein, during a calibration phase, the control circuitry is configured to: control the bias circuitry to apply a macro offset to the input signal, the macro offset to bring the amplified input signal within a dynamic range of the ADC; and determine a micro offset to be applied during a measurement phase of the sensor based on the macro offset and the digital output signal; and wherein during the measurement phase, the control circuitry is configured to control the bias circuitry to disable application of the macro offset and apply the micro offset to the input signal, the macro offset having a greater magnitude than the micro offset.

This A / D converter performs A / D conversion including folding integration. The A / D converter includes: a gain stage that generates an operation value based on an input value; and an A / D conversion circuit that outputs an operation value usable for the generation of a digital value by comparing the operation value generated by the gain stage and the conversion reference voltage. The gain stage generates a calculation value VO (M-1) by using the integration gain G (M-1) in the (M-1)-th integration operation during the M-th integration operation, and generates a calculation value VO (M) by using the integration gain G (M) in the M-th integration operation. The integral gain G (M-1) is greater than the integral gain G (M).

An electronic device includes an amplifier having an input terminal and an output terminal. The amplifier includes a gain stage and an output impedance matching network connected to the gain stage and to the output terminal. The output impedance matching network includes a plurality of metal-oxide-metal (MOM) capacitors connected in parallel to each other.

An amplifier includes a gain stage having a gain stage input and a gain stage output and an impedance matching circuit connected to the gain stage output, the impedance matching circuit including an input and an output. The amplifier also includes a coupling circuit connected to the input of the impedance matching circuit and a shorting circuit connected to the output of the impedance matching circuit. The coupling circuit provides a voltage to the shorting circuit that causes the shorting circuit create a short to ground through a reflecting capacitor which causes a reflection to be provided to the output of the impedance matching circuit and that is transmitted to the coupling circuit to increase the voltage provided to the shorting circuit by the coupling circuit.

The utility model provides a low-noise amplifier capable of selecting performance parameters. The low-noise amplifier mainly comprises four switch modules, an optimal noise input matching module, an optimal gain input matching module, an optimal noise inter-stage matching module, an optimal gain inter-stage matching module, an optimal gain output matching module and a two-stage 0.15-micron GaAs pHEMT stable bias circuit. A plurality of modules capable of independently adjusting noise and gain are designed in the input matching module, the inter-stage matching module and the output matching module, and the noise and gain modules are adjusted through different combinations of the switch modules, so that optimal noise and gain parameters are selected; the optimal gain performance or the optimal noise performance can be selected according to the actual application condition. According to the low-noise amplifier designed by the invention, a noise optimal output signal or a gain optimal output signal can be realized in a working frequency band, and a certain reference is provided for performance optimization of a radio frequency transceiver.

The application discloses a novel three-stage operational amplifier indirect frequency compensation circuit and belongs to the electronic circuit field. A , a second resistor R B , a first capacitor C C1 , a second capacitor C C2 , NMOS tubes MN1-MN8 and PMOS tubes MP1-PMOS tubes MP6; the NMOS tubes MN1-MN5 and the PMOS tubes MP1-PMOS tubes MP2 are a first gain stage of an operational amplifier; the NMOS tubes MN6-MN7 and the PMOS tubes MP3-PMOS tubes MP5 are a second gain stage of the operational amplifier; the NMOS tube MN8 and the PMOS tube MP6 are a third gain stage; the second resistor R B and the first capacitor C C1 , the first resistor R A and the second capacitor C C2 are an indirect frequency compensation network. The application can greatly improve the loop phase margin and the circuit transient stability under the condition of using a smaller compensation capacitor by generating a zero point located in the left half plane to offset a sub-pole in the operational amplifier loop.

The application relates to an operational amplifier and a chip, wherein: an input end of a gain stage circuit is used for inputting an input signal, and the gain stage circuit is used for amplifying the signal; an input end of an impedance isolation circuit is connected with an output end of the gain stage circuit; an input end of an intermediate stage circuit is connected with an output end of the impedance isolation circuit, and the intermediate stage circuit is used for performing level shifting on the input signal; and an input end of an output stage circuit is connected with an output end of the intermediate stage circuit, and the output stage circuit is used for outputting an operational amplifier signal. The impedance isolation circuit is used for isolating the impedance of the intermediate stage circuit and the output impedance of the gain stage circuit. The operational amplifier has high working reliability, and under the condition that the operational amplifier is overloaded, the high output impedance of the gain stage circuit is not affected by the intermediate stage circuit, so that the operational amplifier can maintain high gain.

An amplifier circuit may include a first gain stage configured to receive an input signal at the first gain stage input and apply a first gain to the input signal to generate a first gain stage output signal at the first gain stage output, a second gain stage configured to receive the first gain stage output signal at the second gain stage input and apply a second gain to the first gain stage output signal to generate a second gain stage output signal at the second gain stage output, a feedforward gain stage configured to receive the input signal at the feedforward gain stage input and apply a feedforward gain to the input signal to generate a feedforward gain stage output signal at the feedforward gain stage output, and a compensation network coupled between the first gain stage output and the feedforward gain stage output.

A controller area network (CAN) transceiver including a transmitter, a receiver, a wake-up receiver including an attenuator, a gain stage, a comparator, a pulse filter, and wake-up monitor logic. The gain stage includes an offset generation circuit, a common-gate amplifier, and first and second resistors. The first and second resistors are coupled between outputs of the attenuator to develop a common mode voltage. The offset generation circuit is referenced to the common mode voltage. The pulse filter can include start / stop logic, a transistor, a third resistor and a first capacitor coupled to one input of a second comparator, and a fourth resistor and a second capacitor coupled to another input of the second comparator.

The invention belongs to the field of optical communication chip design, and particularly discloses a noise elimination transimpedance amplifier and a noise elimination method. In the transimpedance amplifier, a gain stage is connected with a voltage follower; the feedback resistor is bridged between the input end of the gain stage and the output end of the voltage follower; the gain stage, the voltage follower and the feedback resistor form a parallel feedback transimpedance gain stage, and the combiner comprises two input ports which are respectively connected with the output end of the gain stage and the output end of the voltage follower; the parallel feedback transimpedance gain stage receives and amplifies an input current signal, two paths of in-phase voltage signals are output from an output port of the gain stage and an output port of the voltage follower, and the combiner is used for carrying out in-phase superposition on the two paths of in-phase voltage signals and then outputting the superposed signals, and meanwhile, noise introduced by the voltage follower is subjected to reverse-phase superposition and mutual offset. The transimpedance amplifier not only realizes amplification of the input signal, but also can suppress noise of the transimpedance amplifier, and can be applied to design of a high-sensitivity optical receiver.

According to the method for improving the capless LDO load regulation rate, an in-phase gain stage circuit composed of M15-M18 is additionally arranged in a POWER module of a capless LDO circuit structure composed of a CORE module and the POWER module, the output stage loop gain is improved, the load regulation rate is increased, meanwhile, the MP grid voltage range can be enlarged, the width-length ratio is reduced under the same loading capacity, and the area is reduced.

An apparatus includes a current sensing gain stage comprising a first leg and a second leg, wherein each leg comprises a plurality of transistors connected in series, a first track stage configured to receive a first current sensing signal, wherein the first track stage comprises a first bias transistor configured to provide a first range of headroom for the first leg of the current sensing gain stage, and a second track stage configured to receive a second current sensing signal, wherein the second track stage comprises a second bias transistor configured to provide a second range of headroom for the second leg of the current sensing gain stage.

An electronic device includes an amplifier having an input terminal and an output terminal. The amplifier includes a gain stage and an output impedance matching network connected to the gain stage and to the output terminal. The output impedance matching network includes a plurality of metal-oxide-metal (MOM) capacitors connected in parallel to each other.

The application discloses a kind of fast response three-ring LDO circuit structures, including operational amplifier circuit, current bias circuit, control voltage generation circuit, flip voltage follower.Flip voltage follower includes super source follower, push-pull output stage, fast negative feedback loop.The structure makes full use of the characteristics of push-pull output structure gate voltage common reduction, greatly improves the ability of pull current, while by increasing additional gain stage, the power supply noise rejection ratio at low frequency is improved.In addition, due to the adoption of super source follower structure, the node impedance is reduced by negative feedback, and the loop stability is effectively improved.

Circuit (154A) includes a digital-to-analog converter (302) and a gain stage (312). The gain stage includes an operational amplifier (322), a variable gain network (340), and a leakage current control circuit (330). The first input (324) of the operational amplifier (322) is coupled to the input (314) of the gain stage (312). The output (328) of the operational amplifier (322) is coupled to the output (318) of the gain stage (312). The first terminal (342) of the variable gain network (340) is coupled to the second input (326) of the operational amplifier (322). The second terminal (344) of the variable gain network (340) is coupled to the output (328) of the operational amplifier (322). The first terminal (334) of the leakage current control circuit (330) is coupled to the output (328) of the operational amplifier (322). The second terminal (336) of the leakage current control circuit (330) is coupled to the third terminal (346) of the variable gain network (340).

In at least one embodiment, a feedback amplifier is provided. The amplifier includes an input stage circuit (206) and a collector element (208). The input stage circuit (206) is configured to receive at least one input feedback signal having wide band frequency components that include high frequency components and low frequency components. The input stage circuit (206) includes a first gain stage (220), a filter, and a second gain stage (222). The first gain stage (220) amplifies the at least one input feedback signal to generate at least one amplified output signal. The filter filters the wide band frequency components on the at least one input feedback signal to generate at least one filtered feedback signal having a first low frequency component. The second gain stage (222) amplifies the at least one filtered feedback signal having the first low frequency component and to provide at least one gain output signal.

A low noise amplifier includes a first input port configured to receive a first input signal, a second input port configured to receive a second input signal, and a first amplifier stage including a first gain stage connected to the first input port and the second input port, and a first drive stage between the first gain stage and a first load circuit. The first gain stage includes a first-first gain block connected to the first input port, a first-second gain block connected to the second input port, and a first degeneration inductor between a ground terminal and a first common node of the first-first gain block and the first-second gain block. The amplifier includes a second amplifier stage including a second gain stage connected to the first input port and the second input port, and a second drive stage between the second gain stage and a second load.

An amplifier circuit comprises a multi-stage amplifier having a plurality of amplifiers cascaded between an input port Vin and an output port Vout to form a differential input stage and N subsequent gain stages, a capacitive load CL coupled to the output port Vout, and a compensation network coupled to the multi-stage amplifier and configured for positioning Pole-Zero pairs of each stage of the multi-stage amplifier below a unity gain frequency ωt of the multi-stage amplifier when compensated, with Zeros positioned lower than Poles so as to increase the unity gain frequency ωt.

Methods related to amplification of radio-frequency signals. In some embodiments, a method for amplifying a radio-frequency signal can include configuring a gain stage to be in a selected one of a plurality of gain settings, with at least some of the gain settings resulting in different phases for the radio-frequency signal. The method can further include adjusting the phase of the radio-frequency signal for the selected gain setting, such that the adjusted phase is part of desired phases adjusted from the different phases.

A comparator includes an input stage configured to receive a pair of input signals to generate at least one differential current signal. The comparator further includes an output stage configured to generate an output signal depending on the differential current signal. The output stage includes a current mirror and a node electrically connected to the current mirror. The current mirror includes a first transistor, a second and a third transistor, the second and the third transistors being connected in parallel. The comparator further comprises a gain stage including a first and a second inverter, wherein an output of the first inverter is input to the second inverter. An output of the second inverter is configured to control the third transistor to be in a floating or conducting state.

The present disclosure relates to a gray zone prevention circuit with indirect signal monitoring. For example, a gray zone prevention circuit includes a first gain stage circuit including a first input terminal and a first output terminal, the first gain stage circuit amplifying a feedback signal received at the first input terminal and generating an amplified signal at the first output terminal; a second gain stage circuit including a terminal coupled to the first output terminal for receiving the amplified signal and a second output terminal, wherein the second gain stage circuit is configured to generate a monitored signal based on the amplified signal; a feedback circuit coupled between the second output terminal and the first input terminal and configured to convert the monitored signal to the feedback signal; and a comparator circuit including a monitoring node coupled to the first output terminal for receiving the amplified signal, wherein the comparator circuit is configured to indirectly monitor the monitored signal via the amplified signal.

The application provides a control method of a two-phase three-order ring oscillator circuit, which comprises the following steps: a two-phase three-order ring oscillator circuit generates a square wave signal, wherein the square wave signal is determined by two voltages corresponding to first and second nodes on a gain stage circuit; and a clock signal CLK is obtained after the square wave signal is shaped, which is beneficial to generate a clock signal with higher precision, smaller temperature variation and higher frequency, and each gain stage adopts a differential structure input to provide good common mode rejection.