134 results about "Filter tuning" patented technology

A graphics system capable of super-sampling and performing real-time convolution. The graphics system may comprise a graphics processor, a sample buffer, and a sample-to-pixel calculation unit. The graphics processor receives graphics data and generates a plurality of samples for each of a plurality of frames. The sample buffer stores the samples. The sample-to-pixel calculation unit is operable to generate output pixels by filtering the rendered samples using a filter. A display device then receives and displays the output pixels. A user may observe the displayed image and adjust properties of the filter according to the user's personal visual preferences. A display-monitoring device may be configured to capture the displayed image. The graphics system may then analyze the captured image and, in response to the captured image, perform filter adjustments.

An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver. ESD protection is provided by a pad ring and ESD clamping structure that maintains signal integrity. Also provided are shunts at each pin to discharge ESD build up. The shunts utilize a gate boosting structure to provide sufficient small signal RF performance, and minimal parasitic loading.

Methods, systems and apparatus for filter design, analysis and adjustment are provided. Various embodiments may include, for example, methods, systems and apparatus for electric signal filter tuning. Embodiments may also include design techniques for planar electric signal (e.g., RF signals) filter tuning. In at least an embodiment of the present invention a technique for filter tuning is provided which may include parameter extraction, optimization and tuning recipes techniques that may require only a single permanent filter tuning. In at least another embodiment a system and method of filter design, analysis and adjustment according to the present invention includes use of tuning that may be set using a mechanical scribing tool or a laser trimming device. In at least one other embodiment, a filter tuning technique may be provided and include providing trimming tabs on a resonator edge that may be disconnected or trimmed for filter tuning.

An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit. A receiver front end provides programable attenuation and a programable gain low noise amplifier. LC filters integrated onto the substrate in conjunction with image reject mixers provide image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. Active filters utilize multi track spiral inductors with shields to increase circuit Q. The filters incorporate a gain stage that provides improved dynamic range through the use of cross coupled auxiliary differential pair CMOS amplifiers to cancel distortion in a main linearized differential pair amplifier. Frequency planning provides additional image rejection. Local oscillator signal generation methods on chip reduce distortion. A PLL generates needed out of band LO signals. Direct synthesis generates in band LO signals. PLL VCOs are centered automatically. A differential crystal oscillator provides a frequency reference. Differential signal transmission throughout the receiver is used. ESD protection is provided by a pad ring and ESD clamping structure. Shunts utilize a gate boosting at each pin to discharge ESD build up. An IF VGA utilizes distortion cancellation achieved with cross coupled differential pair amplifiers having their Vds dynamically modified in conjunction with current steering of the differential pairs sources.