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132 results about "Filter tuning" patented technology

Graphics system having a super-sampled sample buffer with generation of output pixels using selective adjustment of filtering for reduced artifacts

A computer graphics system that utilizes a super-sampled sample buffer and a programmable sample-to-pixel calculation unit for refreshing the display, wherein the graphics system may adjust filtering to reduce artifacts or implement display effects. In one embodiment, the graphics system may have a graphics processor, a super-sampled sample buffer, and a sample-to-pixel calculation unit. The graphics processor renders a plurality of samples and stores them into a sample buffer. The sample-to-pixel calculation unit reads the samples from the super-sampled sample buffer and filters or convolves the samples into respective output pixels which are then provided to refresh the display. The sample-to-pixel calculation unit may selectively adjust the filtering of stored samples to reduce artifacts, e.g., is operable to selectively adjust the filtering of stored samples in neighboring frames to reduce artifacts between the neighboring frames. The filter adjustment may be applied where the sample-to-pixel calculation unit generates output pixels at the same rate as the graphics processor rendering samples to the sample buffer, or at a different (e.g., higher) rate than the render rate. The sample-to-pixel calculation unit is operable to adjust filtering of stored samples to implement a display effect, such as panning, zooming, rotation, or moving scenes, among others. The sample-to-pixel calculation unit may also selectively adjust the filtering of stored samples on a fractional-pixel boundary.
Owner:ORACLE INT CORP

System and method for linearizing a CMOS differential pair

An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. LC filters integrated onto the substrate in conjunction with image reject mixers provide image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. Active filters utilize multi track spiral inductors with shields to increase circuit Q. The filters incorporate a gain stage that provides improved dynamic range through the use of cross coupled auxiliary differential pair CMOS amplifiers to cancel distortion in a main linearized differential pair amplifier. Frequency planning provides additional image rejection. Local oscillator signal generation methods on chip reduce distortion. A PLL generates needed out of band LO signals. Direct synthesis generates in band LO signals. PLL VCOs are centered automatically. A differential crystal oscillator provides a frequency reference. Differential signal transmission throughout the receiver is used. ESD protection is provided by a pad ring and ESD clamping structure. Shunts utilize a gate boosting at each pin to discharge ESD build up. An IF VGA utilizes distortion cancellation achieved with cross coupled differential pair amplifiers having their Vds dynamically modified in conjunction with current steering of the differential pairs sources.
Owner:AVAGO TECH INT SALES PTE LTD

Integrated spiral inductor

An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors with shields to increase circuit Q. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver. ESD protection is provided by a pad ring and ESD clamping structure that maintains signal integrity. Also provided are shunts at each pin to discharge ESD build up. The shunts utilize a gate boosting structure to provide sufficient small signal RF performance, and minimal parasitic loading.
Owner:AVAGO TECH INT SALES PTE LTD

System and method for ESD protection

An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver. ESD protection is provided by a pad ring and ESD clamping structure that maintains signal integrity. Also provided are shunts at each pin to discharge ESD build up. The shunts utilize a gate boosting structure to provide sufficient small signal RF performance, and minimal parasitic loading.
Owner:AVAGO TECH WIRELESS IP SINGAPORE PTE

Graphics system having a super-sampled sample buffer with generation of output pixels using selective adjustment of filtering for implementation of display effects

A computer graphics system that utilizes a super-sampled sample buffer and a programmable sample-to-pixel calculation unit for refreshing the display, wherein the graphics system may adjust filtering to reduce artifacts or implement display effects. In one embodiment, the graphics system may have a graphics processor, a super-sampled sample buffer, and a sample-to-pixel calculation unit. The graphics processor renders a plurality of samples and stores them into a sample buffer. The sample-to-pixel calculation unit reads the samples from the super-sampled sample buffer and filters or convolves the samples into respective output pixels which are then provided to refresh the display. The sample-to-pixel calculation unit may selectively adjust the filtering of stored samples to reduce artifacts, e.g., is operable to selectively adjust the filtering of stored samples in neighboring frames to reduce artifacts between the neighboring frames. The filter adjustment may be applied where the sample-to-pixel calculation unit generates output pixels at the same rate as the graphics processor rendering samples to the sample buffer, or at a different (e.g., higher) rate than the render rate. The sample-to-pixel calculation unit is operable to adjust filtering of stored samples to implement a display effect, such as panning, zooming, rotation, or moving scenes, among others. The sample-to-pixel calculation unit may also selectively adjust the filtering of stored samples on a fractional-pixel boundary.
Owner:ORACLE INT CORP

System and method for linearizing a CMOS differential pair

An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit. A receiver front end provides programable attenuation and a programable gain low noise amplifier. LC filters integrated onto the substrate in conjunction with image reject mixers provide image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. Active filters utilize multi track spiral inductors with shields to increase circuit Q. The filters incorporate a gain stage that provides improved dynamic range through the use of cross coupled auxiliary differential pair CMOS amplifiers to cancel distortion in a main linearized differential pair amplifier. Frequency planning provides additional image rejection. Local oscillator signal generation methods on chip reduce distortion. A PLL generates needed out of band LO signals. Direct synthesis generates in band LO signals. PLL VCOs are centered automatically. A differential crystal oscillator provides a frequency reference. Differential signal transmission throughout the receiver is used. ESD protection is provided by a pad ring and ESD clamping structure. Shunts utilize a gate boosting at each pin to discharge ESD build up. An IF VGA utilizes distortion cancellation achieved with cross coupled differential pair amplifiers having their Vds dynamically modified in conjunction with current steering of the differential pairs sources.
Owner:AVAGO TECH INT SALES PTE LTD

System and method for ESD protection

An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver. ESD protection is provided by a pad ring and ESD clamping structure that maintains signal integrity. Also provided are shunts at each pin to discharge ESD build up. The shunts utilize a gate boosting structure to provide sufficient small signal RF performance, and minimal parasitic loading.
Owner:AVAGO TECH INT SALES PTE LTD

System and method for ESD protection

An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver. ESD protection is provided by a pad ring and ESD clamping structure that maintains signal integrity. Also provided are shunts at each pin to discharge ESD build up. The shunts utilize a gate boosting structure to provide sufficient small signal RF performance, and minimal parasitic loading.
Owner:AVAGO TECH INT SALES PTE LTD

Demodulation and timing synchronization combined method for GFSK (Gauss Frequency Shift Key)

The invention relates to a demodulation and timing synchronization combined method for a GFSK (Gauss Frequency Shift Key). In the invention, an oversampling signal is used as an input of a demodulation and synchronization loop; after a phase of the sampling signal is adjusted by an interpolation filter, conjugate multiplication is carried out on the sampling signal by every two continuous sampling values to obtain a phase difference; and the phase difference is used as an input of timing error detection. With a difference between front and back phase values as a direction of error adjustment,a middle phase value of every three continuously calculated phase values is used as a size of the error adjustment. A timing error is fed back to the interpolation filter after passing through a loopfilter, and a new sampling value is adjusted again and again. By using the invention, the realization complicatedness of hardware is simplified and the use of a square error detection algorithm is avoided under an oversampling situation; and the demodulation and timing synchronization combined method for the GFSK, provided by the invention, has the advantages of small hardware cost and good timing detection performance.
Owner:浙江瑞讯微电子有限公司

Color filter tuning type window scanning optical spectrum imaging system and method

The invention relates to a tuning window-scanning spectral imaging system for a light filter and a tuning window-scanning spectral imaging method for the light filter, and belongs to the field of spectral imaging. The invention is to add a scanning system into a tuning static spectral imaging system for the light filter to make the tuning window-scanning spectral imaging system capable of performing dynamic window-scanning imaging. Moreover, the invention adopts a data acquisition processing system which is matched with the scanning system to make the tuning window-scanning spectral imaging system be capable of completing data processing in the mode of window scanning and output correct spectral cubical result. The invention has high utilization rate of light energy, high spectral resolution and flexible and adjustable service band of spectrums, has both the image signal-to-noise ratio and the spectrum signal-to-noise ratio easy to reach high level, can only be operated in interested wavebands, reduces the data quantity, increases the regulating range of the integral time, can improve the detection level of weak signals, and is suitable to be widely applied in the fields of agricultural production, resource exploration, environmental monitoring, disaster prevention and reduction, substance identification, public safety and the like.
Owner:BEIJING INSTITUTE OF TECHNOLOGYGY

Automatic tuning apparatus for filter and communication instrument

Purposes to offer an automatic tuning apparatus for filter which enables an accurate tuning to be attained and is small size and low power consumption and a communication instrument using the above. The automatic tuning apparatus for filter of the present invention has an input terminal; a reference signal generator, a filter having a control terminal through which a control signal for controlling its filter characteristic is inputted, an output terminal from which the signal inputted from the input terminal and passed through the filter is outputted; an amplitude detection part to which the output signal of the filter is inputted and which detects its amplitude; a phase comparator part detecting the phase difference between the signal before its passing through the filter and the signal after passing through the filter; and a control part in which, during the filter tuning, by letting the reference signal inputted to the filter and inputting successively a plural number of control signals to the control terminal of the filter, thereby a value of the control signal to be used during the normal operation time is determined based on respective amplitudes detected by the amplitude detection part and respective phase differences detected by the phase comparator part.
Owner:COLLABO INNOVATIONS INC

System and method for linearizing a CMOS differential pair

An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit. A receiver front end provides programable attenuation and a programable gain low noise amplifier. LC filters integrated onto the substrate in conjunction with image reject mixers provide image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. Active filters utilize multi track spiral inductors with shields to increase circuit Q. The filters incorporate a gain stage that provides improved dynamic range through the use of cross coupled auxiliary differential pair CMOS amplifiers to cancel distortion in a main linearized differential pair amplifier. Frequency planning provides additional image rejection. Local oscillator signal generation methods on chip reduce distortion. A PLL generates needed out of band LO signals. Direct synthesis generates in band LO signals. PLL VCOs are centered automatically. A differential crystal oscillator provides a frequency reference. Differential signal transmission throughout the receiver is used. ESD protection is provided by a pad ring and ESD clamping structure. Shunts utilize a gate boosting at each pin to discharge ESD build up. An IF VGA utilizes distortion cancellation achieved with cross coupled differential pair amplifiers having their Vds dynamically modified in conjunction with current steering of the differential pairs sources.
Owner:AVAGO TECH INT SALES PTE LTD
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