131 results about "Timing error" patented technology

The invention relates to the technical field of time synchronization, and discloses a hybrid time service method based on Beidou satellite navigation and a TSN, which comprises the following steps: acquiring network topology structure information and historical time service error data of each synchronization node in a target distributed system, and constructing a dynamic time delay state set for jitter identification; based on the dynamic time delay state set, a current global time reference is extracted through a time calibration algorithm, a time difference reference vector sequence is generated, and initial synchronization adjustment is carried out on the TSN main node; constructing an inter-node clock convergence function curve according to the slave node response stability, and judging whether the synchronous network is in a low jitter interval or not based on the time offset rate and the time drift trend change; in combination with the node time state after directional offset suppression, a multi-channel redundant time synchronization mechanism in a time window is applied, a weight adjustment coefficient is extracted, and an unbalanced calibration factor is introduced; and according to a regression correction result, evaluating a time service stability index in real time. The method has the advantage of improving the time service stability.

The invention relates to a retiming circuit applied to an ultra-high-speed and high-precision DAC (Digital-to-Analog Converter), which comprises an alignment module, a cross point adjusting module, a coding module, a phase detection module and a digital module, the coding module is connected with the alignment module, the phase detection module is connected with the cross point adjusting module and the coding module, and the digital module is connected with the phase detection module and the alignment module. According to the circuit structure provided by the invention, the sampling clock can be accurately aligned to the center of a data eye pattern, so that the delay difference between a clock tree and a data path caused by process deviation and the like is effectively reduced, the high-frequency spurious suppression performance is improved by eliminating nonlinear distortion caused by time sequence errors, the SFDR is greatly improved, and compared with a traditional scheme, the SNR is effectively improved.

Methods and apparatuses provide a mechanism to account for timing errors of a wireless device (12) in positioning measurements. In one example, a wireless device (12) performs reference-signal transmissions or measurements and sends information to a network node (20) that is involved in positioning of the wireless device (12). The information indicates associations of the reference-signal transmissions or measurements with respective timing groups of the wireless device (12). Each timing group represents a related set of transmission or reception timing errors within the wireless device (12). Based on the information, the network node (20) accounts for the different timing-group associations when performing positioning calculations that are based on the reference-signal transmissions or measurements performed by the wireless device (12).

A retimer and a retiming method may employ dual path clock forwarding to drive a transmit clock generator. An illustrative integrated retimer circuit includes a sampling element configured to generate a digital receive signal by sampling an analog receive signal in accordance with a sampled signal; a timing error estimator configured to generate a timing error signal indicative of an estimated timing error of the sampled signal relative to the analog received signal; a clock recovery circuit configured to derive a sampled signal from the estimated timing error and a reference clock in part by determining the frequency signal; a transmitter configured to retransmit the digital reception signal according to a transmission clock; and a transmit clock generator configured to derive a transmit clock. The transmit clock generator operates based on each of: a reference clock; a frequency signal; and a phase error of the transmit clock with respect to the sampled signal.

The invention discloses a data sampling timing error evaluation method based on an evaluation model, relates to the technical field of timing error evaluation, and solves the problem that timing error evaluation is not accurate enough. Wherein the sampling module realizes undistorted receiving and clock signal frequency output of a clock signal through a CMOS clock input circuit, a third-order digital phase-locked loop circuit and a DSP digital signal processing chip, and a Fourier phase difference algorithm removes harmonic interference to solve a phase difference between the clock signal and an ideal clock signal; the clock signal feature recognition unit adopts a convolutional neural network to carry out iterative training on a training set of the timing error evaluation module to obtain an error evaluation module, the error evaluation module and the time migration algorithm module realize accurate calculation of a timing error value, and the timing error value calculation accuracy is greatly improved.

Integrated circuit transceivers having digital timing recovery loops with phase interpolation may incorporate dynamic loop gains to compensate for nonlinearities of the phase interpolation. An illustrative receiver circuit includes: a phase interpolator, a sampling element, a timing error estimator, and a feedback circuit. The phase interpolator provides a sampling signal by applying a phase shift to a clock signal in response to a phase control signal. The sampling element produces a digital receive signal by sampling an analog receive signal in accordance with the sampling signal. The timing error estimator produces a timing error signal indicating an estimated timing error of the sampling signal relative to the analog receive signal. The feedback circuit derives the phase control signal from the timing error signal using a scaling element configured to scale the estimated timing error by a scale factor that depends on the phase control signal.

The invention discloses a short burst SOQPSK carrier synchronization method based on an RPT-Net network. The short burst SOQPSK carrier synchronization method comprises the following steps: preprocessing a signal, and merging time domain data of the signal and quartic data into input data; a multi-level residual convolutional network is adopted to extract cross-symbol local phase features, fine phase changes in SOQPSK signals are captured through layer-by-layer stacked convolution operation, the gradient degradation problem of a deep network is relieved in combination with a residual connection mechanism, and the local characterization capacity for phase jump and frequency offset disturbance is enhanced; through a phase perception position coding module, the time domain signal is converted into a complex number form, an instantaneous phase is extracted, orthogonal basis coding is constructed to represent phase change, and deep fusion with position coding is carried out; a Transform coding layer is introduced, a multi-head self-attention mechanism is utilized to capture a long-distance symbol dependency relationship, global phase consistency constraint is optimized, long-term influence of frequency offset on signals is captured, and time sequence error propagation is effectively inhibited.

Retimers and retiming methods may employ dual path clock forwarding to drive a transmit clock generator. One illustrative integrate retimer circuit includes: a sampling element configured to produce a digital receive signal by sampling an analog receive signal in accordance with a sampling signal; a timing error estimator configured to produce a timing error signal indicating an estimated timing error of the sampling signal relative to the analog receive signal; a clock recovery circuit configured to derive the sampling signal from the estimated timing error and a reference clock in part by determining a frequency signal; a transmitter configured to retransmit the digital receive signal in accordance with a transmit clock; and a transmit clock generator configured to derive the transmit clock. The transmit clock generator operates based on each of: the reference clock; the frequency signal; and a phase error of the transmit clock relative to the sampling signal.

A calibration circuit for correcting timing errors introduced by a DAC in a signal path of an ADC, the calibration circuit comprising: an input subtraction module configured to subtract an estimated error from an output of the ADC and provide a corrected output; a filter module configured to approximate an error transfer function corresponding to the DAC timing errors; a correlation module configured to correlate the corrected output with an output from the filter module to extract an error term; an integrator module configured to integrate the error term to provide an updated error coefficient; and a correction module configured to correlate the updated error coefficient with the output from the filter module to provide the estimated error to the input subtraction module.

A method and an apparatus v are provided. The method includes: configuring a frame structure and related parameters of a satellite based on a channel feature, a service feature, and a transmission / reception unit capability; determining a resource scheduling scheme based on configuration information of the frame structure and related parameters and historical resource scheduling information; and performing a timing error compensation on the resource scheduling scheme based on a timing advance obtained by time-frequency synchronization, and performing a data transmission / reception based on the resource scheduling scheme after the timing error compensation.

The invention discloses a burst frequency hopping communication system high-precision arrival time estimation method, device and medium, and relates to the field of burst communication system time synchronization, and the method comprises the following steps: a receiving end carries out multi-channel down-conversion and double symbol sampling on a frequency hopping signal, and carries out local sequence correlation processing; aligning related results according to the frequency hopping pattern and the delay difference, performing non-coherent accumulation, and recording frame header stamping time at a peak moment; performing linear fitting on a correlation peak result to calculate a timing error estimation value; querying and obtaining corresponding compensation time by using an offline established time compensation table to correct the timing error estimated value, and obtaining a timing error precise estimated value; and finally, compensating the precise estimation value to the frame header stamping time, and outputting high-precision arrival time. According to the invention, high-precision time synchronization is realized at a low sampling rate, and hardware overhead is effectively reduced.

The invention relates to the technical field of electronic timers, in particular to an environment self-adaption low-power-consumption management system and method for an electronic timer, and the system comprises an environment sensing array, a physical state evaluator, a dynamic power consumption strategy generator, a closed loop execution and calibration unit and a self-adaption compensator. According to the method, multi-dimensional environment parameters are dynamically collected, a coupling model representing the relation between frequency deviation and compensation power consumption is constructed, combined regulation and control parameters are generated through multi-target optimization by combining the residual electric quantity of equipment and a timing error accumulated value, hardware execution is driven, operation deviation is monitored in real time, and strategy self-adaptive iterative optimization is achieved through a feedback closed loop. According to the invention, the pain point that the precision and the power consumption of a traditional electronic timer are mutually restricted is effectively solved, and the equipment environment adaptive capability, the endurance time and the full life cycle operation stability are greatly improved.

The invention relates to a clock calibration method, computer equipment, a readable storage medium and a program product. Acquiring a sleep clock count value of the control chip; under the condition that the control chip is in the dormant state, the RC calibration circuit is charged through the control chip, and the dormant timer is triggered to carry out clock counting; if it is monitored that the first actual clock count value of the sleep timer reaches the sleep clock count value, charging of the RC calibration circuit is stopped, and the actual charging time of the RC calibration circuit is determined; performing clock calibration on the dormancy timer according to the actual charging time and the dormancy clock count value; calibration operation can be completed in the dormancy process of the control chip, multiple requirements of low power consumption, high precision and low cost are considered, and the problems of large dormancy timing error and inaccurate system wakeup caused by factors such as unstable clock source and environment change are avoided.

A location management function (LMF) of a network provides a timing error to a user equipment and / or a base station for positioning purposes. The LMF: receives an indication of an effective timing error for a downlink time difference of arrival (DL-TDOA) positioning technique, where the effective timing error is associated with a set of base stations configured to transmit positioning reference signals for DL-TDOA; and provides the effective timing error to a user equipment (UE) performing operations related to the DL-TDOA.

The invention discloses a wide-range high-precision steady-state and dynamic-state integrated rotating speed measuring system, and belongs to the technical field of rotating machinery metering. The system comprises a rotating speed measuring node (including an anti-interference sensor and an MCU microprocessor), an upper computer (including a time sequence coordination module and a data processing module) and a data output device, and adopts a continuous double-counting synchronous operation method to realize synchronous triggering of pulses and a time counter and period value inheritance. And a 40MHz temperature compensation crystal oscillator is matched to control the timing error within + / -1 clock period. The time sequence coordination module covers the ultra-wide range of 0.01-400000 r / min through a self-adaptive sampling mechanism (T = 0.01-25 s, K = 1-255), and the anti-interference sensor controls edge jitter within 2 microseconds. The dynamic sampling time of the system is less than or equal to 10ms, the steady-state relative error is less than or equal to 5 * 10 <-6 > (k = 2), the dynamic error is less than or equal to 1.5 * 10 <-4 >, the method is suitable for industrial automation, aero-engine testing and other scenes, the technical bottleneck is broken through, the rotating speed measurement precision and the dynamic response capability are improved, and an effective scheme is provided for precise monitoring of rotating machinery.

This invention discloses a low-cost, low-speed USB circuit control method. It collects bus transmission timing signals, port voltage fluctuation data, and peripheral access status information through an embedded USB fault diagnosis platform to construct a multi-dimensional operational dataset. Based on a differential timing coupling mapping model, it mines the nonlinear coupling relationship of timing signals. A low-speed bus power consumption balancing model regulates power distribution, and a hardware timing error correction algorithm compensates for timing deviations. A low-cost control module converts the corrected parameters into hardware drive signals to achieve data transmission and peripheral control. The fault diagnosis platform monitors operational feedback data in real time and dynamically adjusts model parameters and control strategies. This method eliminates the need for high-cost dedicated chips and solves the problems of accumulated timing deviations and uneven power distribution in traditional methods through multi-model collaboration and closed-loop control. It reduces hardware costs while improving circuit control accuracy, stability, and operational efficiency.

The disclosure relates to positioning techniques for user equipment in a network. A location management function (LMF) of a network is provided that provides timing errors for user equipment and / or base stations for positioning purposes. The LMF: receives an indication of an effective timing error for a downlink time difference of arrival (DL-TDOA) positioning technique, where the effective timing error is associated with a set of base stations configured to transmit positioning reference signals for DL-TDOA; and providing the valid timing error to a user equipment (UE) performing an operation related to the DL-TDOA.

The embodiment of the invention provides a frame synchronization method and device based on a WI FI system, and the method comprises the steps: carrying out the delay self-correlation of a short training sequence of a main channel and a secondary channel, carrying out the bandwidth detection of a current WI FI frame according to the delay self-correlation result of the main channel and the secondary channel, and when the bandwidth detection result of the current WI FI frame is greater than a specified bandwidth, carrying out the bandwidth synchronization of the current WI FI frame. And coarse synchronization is carried out according to a delay self-correlation result of the main channel and the secondary channel to obtain long training sequences of the main channel and the secondary channel, and a correlation peak is searched for a cross-correlation result of the long training sequences of the main channel and the secondary channel and a long training sequence of a local sequence to carry out fine synchronization so as to determine a symbol boundary of the current WIFI frame. According to the method and the device, the problems that only a main 20M channel is used, other channels are not used, and timing errors are deteriorated due to the length of the PPDU are solved, and the effects of improving the frame synchronization precision of the WI FI system and reducing the error code probability caused by the overlong length of the PPDU are achieved.

The present invention provides a communication signal timing error compensation method and device, which includes: processing a signal sent by a transmitter through upsampling, a shaping filter, a transmission channel, a matched filter, and downsampling in sequence to obtain time domain samples of the signal; convolving the filter coefficients of the shaping filter with the filter coefficients of the matched filter to obtain filter coefficients of the time domain samples, and extracting the effective filter coefficients of each time domain sample; constructing a matrix based on the effective filter coefficients of the time domain samples, extracting a submatrix from the matrix based on the number of delayed samples corresponding to each timing error, and calculating the timing compensation coefficient for each timing error based on the submatrix; querying the timing compensation coefficient corresponding to the actual timing error of the current signal, performing timing compensation on the current signal based on the timing compensation coefficient corresponding to the actual timing error, and obtaining a timing-compensated signal. The present invention has a simple structure and low computational complexity, effectively reducing computational complexity and storage space.

An apparatus including at least one processor; and at least one memory storing instructions that, when executed with the at least one processor, cause the apparatus to perform: sending, from the apparatus, a request for at least one of a reference signal comprising a transmitting timing error for use in estimating a position of a user equipment, or measurements which used a receiving timing error for use in estimating the position of the user equipment.

The present invention discloses a timing calibration device and method for a multi-channel group. The timing calibration device for a multi-channel group includes multiple channel inputs, at least one relay switch, at least one comparator, at least one first multiplexer, and a measuring time chip. The at least one comparator is connected to the at least one relay switch and to a reference voltage, or the reference voltage is replaced by a digital-to-analog converter. The at least one first multiplexer inputs signals from different channel groups and outputs a signal of a designated channel. The measuring time chip calculates the timing signal difference of each channel in the multiple channel inputs as a basis for timing signal delay. The present invention can achieve a timing waveform with consistent alignment on the channel terminal, complete accurate timing error calibration, avoid signal time difference, and use only a single circuit board, significantly reducing the cost of the circuit board.

The present invention discloses an aging and fluctuation-aware dynamic timing analysis method, which belongs to the field of integrated circuit design automation. This method is based on event-propagation dynamic timing analysis, and uses an event propagation algorithm to calculate the delay of a circuit per cycle under a specified input. The present invention modifies the traditional event propagation algorithm to support gate-level aging models and gate-level fluctuation models, so that the final dynamic delay is the delay distribution after aging rather than a deterministic value. The present invention can analyze the dynamic delay of a digital circuit after actual load degradation and the fluctuation of the dynamic delay, and thus can calculate the probability of circuit timing errors after aging, which can help designers accurately estimate the impact of aging and random process fluctuations on timing information and avoid performance loss due to over-design.

The integrated sensor has a clock which provides a clock signal having a clock frequency; a digital detector which detects a power grid signal and generates a reference digital signal indicative of the power grid signal and having a sample rate which is a function of the clock frequency; and a timing monitoring stage which receives the reference digital signal and a nominal signal indicative of a nominal timing of the reference digital signal. The timing monitoring stage also compares the reference digital signal with the nominal signal and, in response, provides an error signal indicative of a timing error between the reference digital signal and the nominal signal.

Methods and apparatuses provide a mechanism to account for timing errors of a wireless device in positioning measurements. In one example, a wireless device performs reference-signal transmissions or measurements and sends information to a network node that is involved in positioning of the wireless device. The information indicates associations of the reference-signal transmissions or measurements with respective timing groups of the wireless device. Each timing group represents a related set of transmission or reception timing errors within the wireless device. Based on the information, the network node accounts for the different timing-group associations when performing positioning calculations that are based on the reference-signal transmissions or measurements performed by the wireless device.

A node of a first TDMA network, such as a link 16 network, uses a first receiver to participate in the first network, while using a second receiver to detect and report a second TDMA network, which is not synchronized with the first network, by listening for a characteristic message from the second TDMA network. The timing error between the networks can be estimated from the received message timing. Upon detection, the node can join the second network and / or request updated timing information from the second network. In embodiments where timeslot-specific TRANSEC filters are required, the node selects a TRANSEC filter for a timeslot that is further in the future than an estimated timing error bound. The first and second networks can implement the same network protocol and architecture, differing only due to the timing offset between their network timing references, as would be the case for a split network.

The present application relates to the technical field of electronic timer, and especially to an environment adaptive low power consumption management system and method for electronic timer, the system comprising an environment perception array, a physical state evaluator, a dynamic power consumption strategy generator, a closed loop execution and calibration unit and an adaptive compensator; the present application dynamically collects multi-dimensional environment parameters, constructs a coupling model representing the relationship between frequency offset and compensation power consumption, combines the residual power of the device and the cumulative value of timing error, generates joint control parameters through multi-objective optimization, drives hardware execution and real-time monitors operation deviation, and realizes adaptive iterative optimization of strategy through feedback closed loop. The present application effectively solves the pain point of mutual restriction between precision and power consumption of traditional electronic timer, greatly improves the environment adaptive ability, endurance time and whole life cycle operation stability of the device.

The invention discloses a multi-channel equipment system time sequence control method and system based on MCU control, and belongs to the field of electronic system control, and the method comprises the steps: setting the output level of each output channel of multi-channel equipment; according to the output grade of each output channel, calculating the time required by each output channel from the beginning of establishment of output to the reaching of the output grade; determining an agreed time sequence interval between the output of each output channel of the multi-channel equipment and the output of an upper-level output channel; calculating an actual time sequence interval of output established by adjacent equipment before and after each output channel of the multi-path equipment; and controlling each output channel of each device to establish external output according to the actual time sequence interval time of the established output. According to the invention, the output time sequence control problem of the multi-path equipment is solved, and the output time sequence error of the multi-path equipment is reduced.

The application discloses a timing error estimation method for dual-polarization quantum key distribution, which comprises the following steps: multiplexing a plurality of pilots on the spectrum of a first polarization and a second polarization of a communication signal respectively, transmitting the multiplexed communication signal through an optical fiber channel, and obtaining a receiving signal; obtaining a plurality of pilots and their phase information according to the receiving signal; and determining a timing error value and a delay value according to the phase information. The signal transmitted by the sending end in the application contains pilots capable of determining the timing error value and the delay value, and the receiving end can determine the timing error value and the delay value according to the pilots contained in the receiving signal. Even if the application is applied to a quantum communication system with weak signals, the timing error value and the delay value can be accurately determined, so that timing error estimation can be performed. The application is widely applied to the technical field of quantum communication.

Aspects relate to mechanisms for implementing a frequency domain phase constraint at a decision feedback equalizer (DFE) of a wireless device. The DFE includes a feedforward filter (FFE) operating in a frequency domain. The FFE further includes an accumulator having a main-tap constraint configured to maintain a constant value of a main-tap of the DFE and a phase constraint module configured to maintain a constant phase of a frequency bin associated with the main-tap to produce a timing error used for timing recovery of a receiver of the wireless device.

This application discloses a detector signal reading circuit and detector signal processing method, which can solve the technical problem of position distortion and timing error in signal reading due to the parasitic effects of the detector. The detector signal reading circuit, which can be integrated into an application-specific integrated circuit (ASIC), includes: a detector module, a delay coding module, and a signal processing module. The detector module includes multiple detectors, and the delay coding module includes multiple signal transmission lines. The differential delay lengths of the multiple signal transmission lines are different and arranged according to the delay coding rule. The input ends of the signal transmission lines are connected to the output ends of the detectors in a one-to-one correspondence, and the signal processing module is connected to the output ends of the multiple signal transmission lines. The delay coding module is used to receive the current pulse signal output by the detector and transmit the current pulse signal to the signal processing module via the signal transmission line. The signal processing module is used to process the current pulse signal according to the delay coding rule to obtain detector information.