78 results about "Timing error" patented technology

The invention relates to a retiming circuit applied to an ultra-high-speed and high-precision DAC (Digital-to-Analog Converter), which comprises an alignment module, a cross point adjusting module, a coding module, a phase detection module and a digital module, the coding module is connected with the alignment module, the phase detection module is connected with the cross point adjusting module and the coding module, and the digital module is connected with the phase detection module and the alignment module. According to the circuit structure provided by the invention, the sampling clock can be accurately aligned to the center of a data eye pattern, so that the delay difference between a clock tree and a data path caused by process deviation and the like is effectively reduced, the high-frequency spurious suppression performance is improved by eliminating nonlinear distortion caused by time sequence errors, the SFDR is greatly improved, and compared with a traditional scheme, the SNR is effectively improved.

A method and an apparatus v are provided. The method includes: configuring a frame structure and related parameters of a satellite based on a channel feature, a service feature, and a transmission / reception unit capability; determining a resource scheduling scheme based on configuration information of the frame structure and related parameters and historical resource scheduling information; and performing a timing error compensation on the resource scheduling scheme based on a timing advance obtained by time-frequency synchronization, and performing a data transmission / reception based on the resource scheduling scheme after the timing error compensation.

The invention discloses a burst frequency hopping communication system high-precision arrival time estimation method, device and medium, and relates to the field of burst communication system time synchronization, and the method comprises the following steps: a receiving end carries out multi-channel down-conversion and double symbol sampling on a frequency hopping signal, and carries out local sequence correlation processing; aligning related results according to the frequency hopping pattern and the delay difference, performing non-coherent accumulation, and recording frame header stamping time at a peak moment; performing linear fitting on a correlation peak result to calculate a timing error estimation value; querying and obtaining corresponding compensation time by using an offline established time compensation table to correct the timing error estimated value, and obtaining a timing error precise estimated value; and finally, compensating the precise estimation value to the frame header stamping time, and outputting high-precision arrival time. According to the invention, high-precision time synchronization is realized at a low sampling rate, and hardware overhead is effectively reduced.

The invention relates to the technical field of electronic timers, in particular to an environment self-adaption low-power-consumption management system and method for an electronic timer, and the system comprises an environment sensing array, a physical state evaluator, a dynamic power consumption strategy generator, a closed loop execution and calibration unit and a self-adaption compensator. According to the method, multi-dimensional environment parameters are dynamically collected, a coupling model representing the relation between frequency deviation and compensation power consumption is constructed, combined regulation and control parameters are generated through multi-target optimization by combining the residual electric quantity of equipment and a timing error accumulated value, hardware execution is driven, operation deviation is monitored in real time, and strategy self-adaptive iterative optimization is achieved through a feedback closed loop. According to the invention, the pain point that the precision and the power consumption of a traditional electronic timer are mutually restricted is effectively solved, and the equipment environment adaptive capability, the endurance time and the full life cycle operation stability are greatly improved.

A location management function (LMF) of a network provides a timing error to a user equipment and / or a base station for positioning purposes. The LMF: receives an indication of an effective timing error for a downlink time difference of arrival (DL-TDOA) positioning technique, where the effective timing error is associated with a set of base stations configured to transmit positioning reference signals for DL-TDOA; and provides the effective timing error to a user equipment (UE) performing operations related to the DL-TDOA.

This invention discloses a low-cost, low-speed USB circuit control method. It collects bus transmission timing signals, port voltage fluctuation data, and peripheral access status information through an embedded USB fault diagnosis platform to construct a multi-dimensional operational dataset. Based on a differential timing coupling mapping model, it mines the nonlinear coupling relationship of timing signals. A low-speed bus power consumption balancing model regulates power distribution, and a hardware timing error correction algorithm compensates for timing deviations. A low-cost control module converts the corrected parameters into hardware drive signals to achieve data transmission and peripheral control. The fault diagnosis platform monitors operational feedback data in real time and dynamically adjusts model parameters and control strategies. This method eliminates the need for high-cost dedicated chips and solves the problems of accumulated timing deviations and uneven power distribution in traditional methods through multi-model collaboration and closed-loop control. It reduces hardware costs while improving circuit control accuracy, stability, and operational efficiency.

The disclosure relates to positioning techniques for user equipment in a network. A location management function (LMF) of a network is provided that provides timing errors for user equipment and / or base stations for positioning purposes. The LMF: receives an indication of an effective timing error for a downlink time difference of arrival (DL-TDOA) positioning technique, where the effective timing error is associated with a set of base stations configured to transmit positioning reference signals for DL-TDOA; and providing the valid timing error to a user equipment (UE) performing an operation related to the DL-TDOA.

The embodiment of the invention provides a frame synchronization method and device based on a WI FI system, and the method comprises the steps: carrying out the delay self-correlation of a short training sequence of a main channel and a secondary channel, carrying out the bandwidth detection of a current WI FI frame according to the delay self-correlation result of the main channel and the secondary channel, and when the bandwidth detection result of the current WI FI frame is greater than a specified bandwidth, carrying out the bandwidth synchronization of the current WI FI frame. And coarse synchronization is carried out according to a delay self-correlation result of the main channel and the secondary channel to obtain long training sequences of the main channel and the secondary channel, and a correlation peak is searched for a cross-correlation result of the long training sequences of the main channel and the secondary channel and a long training sequence of a local sequence to carry out fine synchronization so as to determine a symbol boundary of the current WIFI frame. According to the method and the device, the problems that only a main 20M channel is used, other channels are not used, and timing errors are deteriorated due to the length of the PPDU are solved, and the effects of improving the frame synchronization precision of the WI FI system and reducing the error code probability caused by the overlong length of the PPDU are achieved.

An apparatus including at least one processor; and at least one memory storing instructions that, when executed with the at least one processor, cause the apparatus to perform: sending, from the apparatus, a request for at least one of a reference signal comprising a transmitting timing error for use in estimating a position of a user equipment, or measurements which used a receiving timing error for use in estimating the position of the user equipment.

The integrated sensor has a clock which provides a clock signal having a clock frequency; a digital detector which detects a power grid signal and generates a reference digital signal indicative of the power grid signal and having a sample rate which is a function of the clock frequency; and a timing monitoring stage which receives the reference digital signal and a nominal signal indicative of a nominal timing of the reference digital signal. The timing monitoring stage also compares the reference digital signal with the nominal signal and, in response, provides an error signal indicative of a timing error between the reference digital signal and the nominal signal.

Methods and apparatuses provide a mechanism to account for timing errors of a wireless device in positioning measurements. In one example, a wireless device performs reference-signal transmissions or measurements and sends information to a network node that is involved in positioning of the wireless device. The information indicates associations of the reference-signal transmissions or measurements with respective timing groups of the wireless device. Each timing group represents a related set of transmission or reception timing errors within the wireless device. Based on the information, the network node accounts for the different timing-group associations when performing positioning calculations that are based on the reference-signal transmissions or measurements performed by the wireless device.

A node of a first TDMA network, such as a link 16 network, uses a first receiver to participate in the first network, while using a second receiver to detect and report a second TDMA network, which is not synchronized with the first network, by listening for a characteristic message from the second TDMA network. The timing error between the networks can be estimated from the received message timing. Upon detection, the node can join the second network and / or request updated timing information from the second network. In embodiments where timeslot-specific TRANSEC filters are required, the node selects a TRANSEC filter for a timeslot that is further in the future than an estimated timing error bound. The first and second networks can implement the same network protocol and architecture, differing only due to the timing offset between their network timing references, as would be the case for a split network.

The present application relates to the technical field of electronic timer, and especially to an environment adaptive low power consumption management system and method for electronic timer, the system comprising an environment perception array, a physical state evaluator, a dynamic power consumption strategy generator, a closed loop execution and calibration unit and an adaptive compensator; the present application dynamically collects multi-dimensional environment parameters, constructs a coupling model representing the relationship between frequency offset and compensation power consumption, combines the residual power of the device and the cumulative value of timing error, generates joint control parameters through multi-objective optimization, drives hardware execution and real-time monitors operation deviation, and realizes adaptive iterative optimization of strategy through feedback closed loop. The present application effectively solves the pain point of mutual restriction between precision and power consumption of traditional electronic timer, greatly improves the environment adaptive ability, endurance time and whole life cycle operation stability of the device.

The invention discloses a multi-channel equipment system time sequence control method and system based on MCU control, and belongs to the field of electronic system control, and the method comprises the steps: setting the output level of each output channel of multi-channel equipment; according to the output grade of each output channel, calculating the time required by each output channel from the beginning of establishment of output to the reaching of the output grade; determining an agreed time sequence interval between the output of each output channel of the multi-channel equipment and the output of an upper-level output channel; calculating an actual time sequence interval of output established by adjacent equipment before and after each output channel of the multi-path equipment; and controlling each output channel of each device to establish external output according to the actual time sequence interval time of the established output. According to the invention, the output time sequence control problem of the multi-path equipment is solved, and the output time sequence error of the multi-path equipment is reduced.

The embodiment of the application discloses a timing compensation device based on CAN protocol and electronic equipment, and relates to the field of signal processing. The timing compensation device comprises a fractional frequency division module, a filter, an edge detection module, a pulse synchronization module, a phase error calculation module, a baud rate counter and a synchronization identification module. The 2tq width pulse interference is filtered out through the optimized burr suppression mechanism, and the stable transmission of the bus signal is ensured. The innovation expands the synchronization jump width range, breaks through the traditional 1tq-4tq limitation, and improves the phase error correction capability. The intelligent state discrimination algorithm is used to accurately distinguish the leading, lagging and non-synchronization states. The baud rate counter value is directly corrected through the phase error quantization calculation module, the quantitative correction of the timing error is realized, and the stability of the bus communication and the data transmission accuracy are effectively improved.

The present disclosure relates to dynamic timing loop gain for compensating for phase interpolator nonlinearity. An integrated circuit transceiver having a digital timing recovery loop with phase interpolation can incorporate dynamic loop gain to compensate for nonlinearity of the phase interpolation. An illustrative integrated receiver circuit includes a phase interpolator, a sampling element, a timing error estimator, and a feedback circuit. The phase interpolator provides a sampling signal by applying a phase shift to a clock signal in response to a phase control signal. The sampling element produces a digital receive signal by sampling an analog receive signal in accordance with the sampling signal; the timing error estimator produces a timing error signal indicative of an estimated timing error of the sampling signal relative to the analog receive signal. The feedback circuit derives the phase control signal from the timing error signal using a scaling element configured to scale the estimated timing error by a scaling factor that depends on the phase control signal.

A method for recovering a clock from input data, in a deserializer that couples a transmission medium to receive circuitry of a data transceiver, includes operating, in a first clock recovery loop, on equalized input data from a data recovery loop to provide a first timing error signal, operating, in a second clock recovery loop, on unequalized input data to provide a second timing error signal, combining the first and second timing error signals, and deriving a recovered clock signal from the combined first and second timing error signals using an oscillator circuit. Combining the first and second timing error signals may include operating on the first and second timing error signals in a manner that filters the first timing error signal to remove low-frequency components including adaptation errors introduced by the data recovery loop, and that filters the second timing error signal to remove high frequency components including jitter.

The present subject matter relates to a method for operating a node of a communication system. The node is configured to support wireless backhauling in the communication system and support wireless access in the communication system. The method comprises: receiving from a node first data on a backhaul link and second data on an access link, determining transmit times of the first and second data using the received first data and second data, determining a timing error using the determined transmit times.

The invention provides a timing deviation compensation method and device for an orthogonal frequency division multiplexing signal, which can be applied to the technical field of signal processing. Comprising the following steps: performing up-sampling on a to-be-synchronized orthogonal frequency division multiplexing signal to obtain an up-sampling signal; according to a first matching degree between the time domain synchronization symbol sequence template and a target time domain synchronization symbol sequence, determining respective first-level timing of N to-be-synchronized orthogonal frequency division multiplexing symbols; for any to-be-synchronized orthogonal frequency division multiplexing symbol, obtaining a second-level timing error of the to-be-synchronized orthogonal frequency division multiplexing symbol according to a second matching degree between cyclic prefixes and tail sections, which are respectively corresponding to a plurality of candidate starting moments, in the up-sampling signal; performing timing compensation on the up-sampling signal according to respective first-level timing and second-level timing errors of the N to-be-synchronized orthogonal frequency division multiplexing symbols to obtain a compensated up-sampling signal; and obtaining an orthogonal frequency division multiplexing signal according to the compensation up-sampling signal.

The application discloses a high-precision time of arrival estimation method, equipment and medium for a burst frequency hopping communication system, relates to the field of time synchronization of a burst communication system, and comprises the following steps: a receiving end performs multi-channel down-conversion and 2 times symbol sampling on a frequency hopping signal, and performs correlation processing on a local sequence; non-coherent accumulation is performed on the correlation results after the correlation results are aligned according to a frequency hopping pattern and a delay difference, and a frame header stamping time of a peak time is recorded; a timing error estimation value is calculated by performing linear fitting on the correlation peak results; a corresponding compensation time is obtained by querying a time compensation table established offline, so as to correct the timing error estimation value, and a precise timing error estimation value is obtained; and finally, the precise estimation value is compensated to the frame header stamping time, and a high-precision time of arrival is output. The application realizes high-precision time synchronization under a low sampling rate, and effectively reduces hardware cost.

Examples of a receiver, a controller unit (e.g., for a receiver), and related methods (e.g., for a receiver) are provided. A receiver is provided that includes a tunable sample provider configured to provide samples of an input signal using tunable sample timing, a feedback path configured to provide a feedback signal to the tunable sample provider based on a timing error, wherein the feedback path includes a loop filter configured to provide sample timing information to the tunable sample provider, and a replacement value provider configured to provide replacement sample timing information that replaces the sample timing information provided by the feedback path when the input signal does not satisfy predetermined requirements for feedback-based sample timing adjustment, wherein the replacement value provider is configured to provide the replacement sample timing information taking into account timing error information or a quantity derived from the timing error information over a longer period of time than a period of time taken into account by the loop filter for providing the sample timing information.

The invention discloses a high-precision DTO time sequence control method and system. The method comprises the following steps: sequentially performing low-pass, band-stop, LMS self-adaptive and Kalman four-stage filtering on a time sequence error signal; a calculus algorithm of fixed parameters (Kp = 0.8, Ki = 0.1, and Kd = 0.5) is adopted to calculate the control quantity; and integrating a time sequence self-healing mechanism. The system is further provided with a collaborative interface used for interacting with an external system. According to the invention, complex interference can be effectively suppressed, nanosecond-level high-precision and high-stability sequential control is realized, and good system expansibility is achieved.

A communication device of a communications network can receive a request message from a network node of the communications network. The request message can request an indication of reference signal (“RS”) resources used by the communication device to communicate with the network node and an indication of a timing error group (“TEG”) identifier (“ID”) associated with the RS resources. The communication device can transmit the indication of the RS resources and the indication of the TEG ID to the network node.

A terminal comprising: a control unit that assumes that a reference signal associated with a group relating to a timing error is used in carrier aggregation for positioning; and a communication unit that transmits or receives the reference signal by carrier aggregation.

The application relates to the technical field of power electronic control, and provides a driving signal timing adjustment method and system for an IGBT series valve, which comprises the following steps: acquiring the working condition state parameters of each power switching device in N power switching devices, inputting a response time prediction model, outputting a predicted response time deviation, generating an expected response time, adjusting the output timing of the driving signals of each power switching device, and offsetting the predicted response time deviation; detecting the actual switching time of each power switching device, and generating an actual response time; based on the actual response time and the expected response time, calculating a timing error, and updating the model parameters of the response time prediction model; based on a unified time reference, controlling the N power switching devices, and performing synchronous switching, so as to minimize the current ripple when the N power switching devices work cooperatively. The application realizes closed-loop adaptive compensation of driving timing drift, and effectively suppresses the current ripple when multiple devices work cooperatively.

In some implementations, an open radio access network (O-RAN) radio unit (O-RU) may send capability information to an O-RAN distributed unit (O-DU), the capability information indicating a reporting capability of the O-RU for reporting timing error information. The O-RU may measure a timing error of the O-RU, the timing error comprising a residual error in a time delay at the O-RU after calibration. The O-RU may send a timing error report to the O-DU in accordance with the reporting capability of the O-RU, wherein the timing error report is indicative of the timing error.

The application discloses a parallel demodulation timing synchronization method for high-speed coherent spread spectrum, and relates to the field of wideband satellite communication covert communication and anti-jamming communication systems. The application adopts parallel processing demodulation to reduce processing clock, adopts a mode of adjusting the timing error of a spread spectrum communication delay-locked loop output to realize tracking timing synchronization of the spread spectrum communication, and the mode is that multiple parallel outputs are adopted to reduce processing clock, and the output clock of resampling is adjusted to realize synchronization of the local clock and the received data clock, which is beneficial to low signal-to-noise ratio demodulation, suitable for high chip rate or high bandwidth spread spectrum, and can be used for wideband satellite spread spectrum communication.

This invention describes an integrated circuit and a method for designing an integrated circuit including error detection and correction circuitry. The integrated circuit includes a data path arranged between the output of a first register timed by a system clock and a second register. The integrated circuit includes timing error detection and correction circuitry (EDAC) having a clock unit configured to receive a reference clock and provide a delayed reference clock. The EDAC includes a plurality of transition detectors coupled to corresponding nodes on the data path and error detection circuitry coupled to each transition detector. During design, the nodes are selected according to a desired timing window to be monitored. If a transition occurs during a snapshot of a time period between a transition corresponding to the reference clock and a corresponding transition of the delayed reference clock, the error detection circuitry flags an error. The timing correction circuitry coupled to the error detection circuitry outputs the system clock derived from the delayed reference clock.

The invention discloses a timing error detection method and device and a storage medium, and relates to the technical field of communication, and the method comprises the steps: obtaining a sampling signal; re-sampling the sampling signal through an interpolation filter to obtain an interpolated signal; inputting the interpolated signal, a pre-calculated theoretical intermediate value and the noise-suppressed signal into a high-order modulation timing synchronous detection error device to obtain a timing error; adjusting the interpolation filter based on the timing error; and outputting a final output signal through the adjusted interpolation filter. According to the invention, the timing error detection accuracy under a low signal-to-noise ratio can be improved.

The invention relates to an off-line voice broadcast noise removal method. The off-line voice broadcast noise removal method comprises the following steps: acquiring the playing duration and timing error of an audio to be played; connecting a mute audio clip at the tail end of the to-be-played audio according to the playing duration and the timing error to obtain a target playing audio; determining power amplifier turn-off time in the mute audio clip; and broadcasting the target playing audio, and turning off a power amplifier when the power amplifier turn-off time is up, so that the target playing audio is ended to be broadcasted after the power amplifier is turned off. According to the scheme of the invention, noise can be prevented from being generated when the audio playing is finished, and the user experience is improved.