690results about How to "Reduce static power consumption" patented technology

By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges on the corrugated substrate to be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy. Additional performance enhancement techniques such as pulse-shaped doping, “wrapped” gates, epitaxially grown conductive regions, epitaxially grown high mobility semiconductor materials (e.g. silicon-germanium, germanium, gallium arsenide, etc.), high-permittivity ridge isolation material, and narrowed base regions can be used in conjunction with the segmented channel regions to further enhance device performance.

An optically controlled microwave antenna that reduces the optical power consumed by the antenna and to enable polarimetric detection an optically controlled microwave antenna comprises an antenna array and a feed for illuminating said antenna array with and/or receiving microwave radiation. The antenna array comprises a plurality of antenna elements each including a waveguide, two optically controllable semiconductor elements arranged within the waveguide in front of the light transmissive portion of the second end portion, a controllable light source arranged at or close to the light transmissive portion of the second end portion for projecting a controlled light beam onto said semiconductor element for controlling its material properties, and a septum arranged within the waveguide in front of the light transmissive portion of the second end portion and separating said waveguide into two waveguide portions.

The present invention provides device components geometries and fabrication strategies for enhancing the electronic performance of electronic devices based on thin films of randomly oriented or partially aligned semiconducting nanotubes. In certain aspects, devices and methods of the present invention incorporate a patterned layer of randomly oriented or partially aligned carbon nanotubes, such as one or more interconnected SWNT networks, providing a semiconductor channel exhibiting improved electronic properties relative to conventional nanotubes-based electronic systems.

A method of operating a programmable logic device, including the steps of enabling resources of the programmable logic device being used in a circuit design implemented by the programmable logic device, and disabling unused or inactive resources of the programmable logic device that are not being used in the circuit design. The step of disabling can include de-coupling the unused or inactive resources from one or more power supply terminals. Alternatively, the step of disabling can include regulating a supply voltage applied to the unused or inactive resources. The step of disabling can be performed in response to configuration data bits stored by the programmable logic device and/or in response to user controlled signals. The step of disabling can be initiated during design time and/or run time of the programmable logic device.

A memory system uses multiple pulse amplitude modulation (multi-PAM) output drivers and receivers to send and receive multi-PAM signals. A multi-PAM signal has more than two voltage levels, with each data interval now transmitting a “symbol” at one of the valid voltage levels. In one embodiment, a symbol represents two or more bits. The multi-PAM output driver drives an output symbol onto a signal line. The output symbol represents at least two bits that include a most significant bit (MSB) and a least significant bit (LSB). The multi-PAM receiver receives the output symbol from the signal line and determines the MSB and the LSB.

A memory circuit for use in a data processing circuit is described, in which memory cells have at least two states, each state being determined by both a first voltage level corresponding to a first supply line and a second voltage level corresponding to a second supply line. The memory circuit comprises a readable state in which information stored in a memory cell is readable and an unreadable state in which information stored in said memory cell is reliably retained but unreadable. Changing the first voltage level but keeping the second voltage level substantially constant effects a transition between the readable state and the unreadable state. In use, the static power consumption of the memory cell in the unreadable state is less than static power consumption of the memory cell in the readable state.

The invention discloses a wide-input voltage high-power supply rejection ratio reference voltage source. The reference voltage source comprises a self-bias circuit (1), a primary presetting circuit (2), a secondary presetting circuit (3), a bandgap reference core circuit (4) and a signal feedback circuit (5) which are sequentially connected. By using the self-bias circuit in a self-bias current mirror structure, the circuit can be started independently without using additional start circuits; by directly using the output of the secondary presetting circuit as the output of the reference voltage and simultaneously supplying power to the bandgap reference core circuit, the connection mode can improve the loading capacity of the reference voltage; by using the operational amplifier-free feedback loop for regulation, one clamping operational amplifier is removed from the traditional reference voltage source circuit, thereby saving the area and reducing the quiescent power dissipation; andcompared with the traditional bandgap reference voltage source circuit, the power supply rejection ratio of the output reference voltage, especially the performance under a high-frequency condition, is greatly improved.

The present invention is applicable to the field of electrics and provides an integrated circuit (IC) and a standby controlling method thereof. The IC comprises a reset device, a standby control device, a functional device and a power supply control device. The functional device at least comprises a functional unit that does not operate in a standby mode. The power supply control device is configured to supply power to the functional device, the standby control device and the reset device. The standby control device is configured to control the power supply control device to control a power supply voltage of the functional unit to be within a preset range below a normal operating voltage when a standby status signal is detected, and restore the power supply voltage into the normal operating voltage when a wake-up signal is detected; and the reset device is configured to reset the functional device when the system standby status signal is detected and release the resetting of the functional device when the wake-up signal is detected. The IC of the present invention reduces the time required by the IC to wake up from the standby mode while ensuring that the whole functional device has low static power consumption.

Power control circuitry is provided for controlling connection of a power source having a source voltage level to a switched power rail to provide power to an associated circuit block. The power control circuitry comprises a switch block for selectively connecting the switched power rail to the power source, and a switch controller for controlling operation of the switch block. A ring oscillator circuit is powered from the switched power rail and produces an oscillating output signal, and analysis circuitry is then used to analyse change in frequency of the oscillating output signal produced by the ring oscillator circuit during a period of time when the switched power rail is not at the source voltage level. The switch controller is then arranged to control at least one aspect of the operation of the switch block in dependence on the analysis. This technique provides a simple and effective digital technique for observing voltage changes on the switched power rail.

The invention discloses an equalizing charge method and an equalizing charger. The equalizing charge method comprises the following steps: (1) connecting N (N is integer and is more than or equal to 2) single batteries in a battery pack in parallel; (2) independently and quickly charging the N single batteries at the same time; and (3) after the single batteries meet the charge requirement, finishing charging the battery pack. The equalizing charge method of the invention changes the series discharge mode of the single batteries of the battery pack into a parallel mode to independently charge the batteries of the battery pack, thus independently controlling the charge process of the single batteries to ensure equalizing charge for the single batteries. The charger of the invention uses a single chip control center as the core, and simply and precisely realizes independent charge and independent control of the single batteries.

A low-power-consumption source driver for a liquid crystal display is provided. Morethan one middle voltage level for the level shifter and the output buffer is provided, in addition to the power supply voltage level VDD and the ground level GND, to provide different voltage levels for image data of different polarities. Hence, amplitude of the operational voltage of the level shifters and the analog circuits with different polarities can be reduced. It also can reduce the amplitude of the operational voltage of the level shifter and can reduce significantly the dynamic power consumption of the level shifter and the DAC. Because the voltage amplitude of the circuit is reduced and a low-voltage tolerated device can be used, so that the present invention can further reduce the cost of the circuit.

A method of operating a programmable logic device, including the steps of using a full V_DD supply voltage to operate one or more active blocks of the programmable logic device, and using a reduced supply voltage (e.g., ½ V_DD) to operate one or more inactive blocks of the programmable logic device. The full VDD supply voltage and reduced supply voltage can be provided to the blocks of the programmable logic device through high-voltage n-channel transistors. A boosted voltage, greater than VDD, is applied to the gate of an n-channel transistor to provide the full VDD supply voltage to an active block. A standby voltage, less than VDD, is applied to the gate of an n-channel transistor to provide the reduced supply voltage to an inactive block. The inactive blocks can be determined during run time and/or design time of the programmable logic device.

By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges on the corrugated substrate to be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy. Additional performance enhancement techniques such as pulse-shaped doping and “wrapped” gates can be used in conjunction with the segmented channel regions to further enhance device performance.

The invention discloses a bandgap reference voltage source which comprises a starting circuit, a core bandgap reference circuit and a high-order compensation circuit. The core bandgap reference circuit comprises PMOS tubes M1, M2 and M3, NPN triodes Q1 and Q2 and resistance units R1, RB1, RB2 and RA; and the high-order compensation circuit comprises PMOS tubes M4, M5, M6, M7, M8, M9, M10 and M11, NPN triodes Q3, Q4, Q5, Q6, Q7 and Q8 and resistance units R2 and R3. The bandgap reference voltage source disclosed by the invention adopts the high-order compensation circuit, thereby the temperature coefficient is reduced greatly; the circuits adopt the resistance ratio, thus the circuits can not be affected by the absolute value of the resistance, and the influence of the temperature coefficient of the resistance to the output quantity can be reduced. The bandgap reference voltage source has high power supply rejection ratio and can ensure that the circuits can resist the interference of a power supply.

The invention provides a 12-bit intermediate-rate successive approximation type analog-digital converter and relates to the field of analog-digital converters. The 12-bit intermediate-rate successive approximation type analog-digital converter comprises a sampling network, a differential capacitor array connected with the sampling network, and a comparator circuit connected with the differential capacitor array, wherein the differential capacitor array comprises a first capacitor array connected with the positive-phase input end of the comparator circuit, and a second capacitor array connected with the negative-phase input end of the comparator circuit; both the first capacitor array and the second capacitor array are composed of 11 groups of binary-structured bit capacitors, and the bottom plates of the redundant capacitors of the second capacitor array are constantly connected with a common-mode voltage VCM. The 12-bit intermediate-rate successive approximation type analog-digital converter solves the problems of large capacitor area and high power consumption of a traditional binary capacitor type structure.

The invention discloses a piezoelectric energy collection system and a control method thereof. The piezoelectric energy collection system comprises a piezoelectric energy collector, an active rectifier, a Buck-boost converter, an asynchronous control circuit, a self-startup precharge circuit, a peak detection circuit, an inductance input-end voltage zero-crossing detection circuit, a VDD-end energy storage unit, a charge current zero-crossing detection circuit of the VDD-end energy storage unit, a VST-end energy storage unit, a charge current zero-crossing detection circuit of the VST-end energy storage unit, an inter-storage-unit energy conversion circuit, an LDO voltage-stabilizing circuit, a VDD internal voltage-stabilizing circuit and a low-power reference current source and reference voltage generation circuit. According to the invention, an ultralow-power design technology is introduced, a conventional circuit structure is improved, performance optimization and structural innovation are performed on each circuit module, static power consumption of the whole circuit system is reduced to 111.1nW, and the energy conversion efficiency is as high as 89.4%. Besides, the system also has the advantages of small chip area, high integration, complete automation, high adaptive capacity to environment and the like.

The invention discloses a low-power design method for a wireless sensor network core chip. According to the low-power design method for the wireless sensor network core chip, the working mode of the chip is divided into a normal working mode and a low-power working mode, when the chip works in the normal working mode, the working frequency of the chip can be configured according to requirements of a specific application, and the clock frequency is reduced to save most dynamic power consumption due to unnecessary flipping of a clock; when the chip does not need to process tasks, the chip chooses to work in the low-power working mode, in the low-power working mode, the clock or power supplies in certain regions inside the chip can automatically turn off, and further the dynamic power consumption and the static power consumption are saved. According to the low-power design method for the wireless sensor network core chip, unnecessary power consumption can be reduced substantially whenever the chip works or sleeps, the service life of batteries is prolonged for wireless sensor network nodes, very important significance for power consumption reduction under the condition that the correct working of the wireless sensor network nodes is guaranteed is achieved.

The invention discloses a first-stage circuit structure of a pipelined analog-to-digital converter, which comprises a 4-digit fully parallel analog-to-digital converter, a code circuit and a residue gain analog-to-digital converter. A two-phase non-overlapping clock is adopted, a sampling phase samples input voltage, and a maintaining phase amplifies residual voltage. The residue gain analog-to-digital converter consists of a sub analog-to-digital converter, a subtracter and a residue amplifier. During sampling, the 4-digit fully parallel analog-to-digital converter conducts comparison and quantification on the input voltage and generates a 16-digit thermometer code which is converted to a 4-digit binary output code by the encoder. A lower pole plate of a sampling capacitor array is connected with the input voltage, and an upper pole plate thereof is connected with a common mode level for sampling an input. During maintaining, the sub analog-to-digital converter outputs different voltages to the sampling capacitor array according to a control of the thermometer code; subtraction from the input voltage is accomplished according to twice charge conservation; and a feedback capacitor is in bridge connection with the two ends of the residue amplifier to amplify the residual voltage by 8 times for use by a backward-stage circuit.

The invention discloses a novel static random access memory (SRAM) storage unit preventing a single particle from turning. The storage unit comprises a first input/output port, a first potential turning recovery driving circuit, a voltage retaining circuit, a second potential turning recovery driving circuit and a second input/output port which are connected in series with one another sequentially. An automatic recovery function for voltage turning when a sensitive node is impacted by a high-energy particle can be realized; according to a simulation result of a TSMC 0.18 mu_m process, a turning threshold value LETth is more than 500 MeV/(mg.cm<2>); compared with the conventional storage unit preventing the single particle from turning, the SRAM storage unit has the characteristic of high writing speed; the recovery time can be effectively shortened; by adopting a unidirectional clock and a small-clock amplitude, a clock network is relatively simple and relatively high in reliability; the clock is only connected with the gate of a read-write transistor, and the clock load is relatively small; and the sensitive node can be used for reinforcing multi-node turning of the single particle, which is caused by drains positioned on a P-type tube and an N-type tube..