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689results about How to "Reduce static power consumption" patented technology

Integrated circuit SoC chip circuit structure capable of realizing power reduction and method thereof

The invention relates to an integrated circuit SoC chip circuit structure capable of realizing power reduction and a method thereof. The SoC chip contains at least one working domain which powers off when idle and at least one real-time-domain which continuously powers on, wherein an isolator is arranged between the working domain and the real-time-domain, and the working domain and the real-time-domain are separately connected with an external power supply source. The method of the invention comprises the processes of working domain power-off treatment and working domain wakeup power-on treatment. By adopting the integrated circuit SoC chip circuit structure capable of realizing power reduction and the method thereof, when the chip is idle, the working domain is in power-off state and the real-time-domain generates quiescent power drain; if the leakage of the real-time-domain is ensured to be as low as possible, the quiescent power drain of the chip can be reduced to be as low as possible and the quiescent power drain of the SoC chip can be effectively reduced; the structure is simple and practical, the control process is fast and convenient, the work performance is stable and reliable and the range of application is wide, thus the structure lays a solid foundation for the application of higher precision integrated circuit process technology in portable devices and the further development of portable devices.

Piezoelectric energy collection system and control method thereof

The invention discloses a piezoelectric energy collection system and a control method thereof. The piezoelectric energy collection system comprises a piezoelectric energy collector, an active rectifier, a Buck-boost converter, an asynchronous control circuit, a self-startup precharge circuit, a peak detection circuit, an inductance input-end voltage zero-crossing detection circuit, a VDD-end energy storage unit, a charge current zero-crossing detection circuit of the VDD-end energy storage unit, a VST-end energy storage unit, a charge current zero-crossing detection circuit of the VST-end energy storage unit, an inter-storage-unit energy conversion circuit, an LDO voltage-stabilizing circuit, a VDD internal voltage-stabilizing circuit and a low-power reference current source and reference voltage generation circuit. According to the invention, an ultralow-power design technology is introduced, a conventional circuit structure is improved, performance optimization and structural innovation are performed on each circuit module, static power consumption of the whole circuit system is reduced to 111.1nW, and the energy conversion efficiency is as high as 89.4%. Besides, the system also has the advantages of small chip area, high integration, complete automation, high adaptive capacity to environment and the like.

Low-power design method for wireless sensor network core chip

The invention discloses a low-power design method for a wireless sensor network core chip. According to the low-power design method for the wireless sensor network core chip, the working mode of the chip is divided into a normal working mode and a low-power working mode, when the chip works in the normal working mode, the working frequency of the chip can be configured according to requirements of a specific application, and the clock frequency is reduced to save most dynamic power consumption due to unnecessary flipping of a clock; when the chip does not need to process tasks, the chip chooses to work in the low-power working mode, in the low-power working mode, the clock or power supplies in certain regions inside the chip can automatically turn off, and further the dynamic power consumption and the static power consumption are saved. According to the low-power design method for the wireless sensor network core chip, unnecessary power consumption can be reduced substantially whenever the chip works or sleeps, the service life of batteries is prolonged for wireless sensor network nodes, very important significance for power consumption reduction under the condition that the correct working of the wireless sensor network nodes is guaranteed is achieved.

First-stage circuit structure of pipelined analog-to-digital converter

The invention discloses a first-stage circuit structure of a pipelined analog-to-digital converter, which comprises a 4-digit fully parallel analog-to-digital converter, a code circuit and a residue gain analog-to-digital converter. A two-phase non-overlapping clock is adopted, a sampling phase samples input voltage, and a maintaining phase amplifies residual voltage. The residue gain analog-to-digital converter consists of a sub analog-to-digital converter, a subtracter and a residue amplifier. During sampling, the 4-digit fully parallel analog-to-digital converter conducts comparison and quantification on the input voltage and generates a 16-digit thermometer code which is converted to a 4-digit binary output code by the encoder. A lower pole plate of a sampling capacitor array is connected with the input voltage, and an upper pole plate thereof is connected with a common mode level for sampling an input. During maintaining, the sub analog-to-digital converter outputs different voltages to the sampling capacitor array according to a control of the thermometer code; subtraction from the input voltage is accomplished according to twice charge conservation; and a feedback capacitor is in bridge connection with the two ends of the residue amplifier to amplify the residual voltage by 8 times for use by a backward-stage circuit.

Novel static random access memory (SRAM) storage unit preventing single particle from turning

ActiveCN102723109ARealize the ability of flip reinforcementReduce rollover recovery timeDigital storageStatic random-access memoryClock network
The invention discloses a novel static random access memory (SRAM) storage unit preventing a single particle from turning. The storage unit comprises a first input/output port, a first potential turning recovery driving circuit, a voltage retaining circuit, a second potential turning recovery driving circuit and a second input/output port which are connected in series with one another sequentially. An automatic recovery function for voltage turning when a sensitive node is impacted by a high-energy particle can be realized; according to a simulation result of a TSMC 0.18 mu_m process, a turning threshold value LETth is more than 500 MeV/(<2>); compared with the conventional storage unit preventing the single particle from turning, the SRAM storage unit has the characteristic of high writing speed; the recovery time can be effectively shortened; by adopting a unidirectional clock and a small-clock amplitude, a clock network is relatively simple and relatively high in reliability; the clock is only connected with the gate of a read-write transistor, and the clock load is relatively small; and the sensitive node can be used for reinforcing multi-node turning of the single particle, which is caused by drains positioned on a P-type tube and an N-type tube..
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