57results about How to "Reduce static power consumption" patented technology

The present invention proposes a circuit and working method for realizing power supply monitoring with high efficiency and low power consumption, including a voltage divider circuit, a reference voltage source, a comparator, a high-speed power-on detection circuit, a NOR gate, a clock generation and shutdown circuit, a delay module and an output drive module. The voltage divider circuit is used to generate a reset threshold voltage that is proportional to the input voltage; the reference voltage source is used to generate a reference voltage that is independent of the power supply voltage and temperature; the comparator is used to compare the voltage after voltage division with the reference voltage; the high-speed power-on detection circuit is used to generate an on-chip reset signal of a power supply monitoring circuit with anti-interference capability; the clock generation and shutdown circuit is used to generate a clock signal of a delay unit and shut down a clock generation circuit; and the delay module is used for timing. It introduces a high-speed power-on detection circuit to avoid the reset failure problem caused by the comparator failing to flip in time or the power supply glitch interference, and at the same time introduces a clock shutdown circuit to effectively reduce power consumption.

The present invention relates to the technical field of low-power AI processors, and discloses a load balancing method, chip and storage medium of a low-power AI processor, the method comprising: partitioning cache resources for multiple neuromorphic cores in a low-power AI processor to obtain a double-layer cache structure; performing characteristic analysis on a target computing task, and constructing a directed acyclic graph of computing tasks and a dependency strength matrix; performing task segmentation to obtain a subtask partitioning scheme; creating a task-core mapping table; based on the task-core mapping table, organizing the neuromorphic core into multiple concentric ring layers to obtain a multi-layer ring collaborative computing network; based on the multi-layer ring collaborative computing network, calculating multiple performance indicators of each neuromorphic core, and performing dynamic load optimization to obtain a dynamic load optimization strategy. The present invention realizes load balancing of a low-power AI processor, and improves computing efficiency and energy utilization.

The invention provides a PQC and SM2 / 9 cooperative operation cryptographic chip and method based on an RISC-V architecture, and belongs to the technical field of cryptographic security. The chip comprises an RISC-V core and a configurable password collaborative operation unit, wherein the configurable password collaborative operation unit comprises a collaborative control state machine and a unified operation unit capable of being dynamically reconfigured. The method comprises the following steps: receiving and decoding a single cooperative operation instruction from an RISC-V core through a cooperative control state machine, and obtaining operation data feature information; the data length and the security level identification are extracted, and the optimal collaborative operation process is selected in a self-adaptive mode through comparison with a preset threshold value; and finally, dynamically configuring and scheduling a unified operation unit according to the selected process, and completing cooperative operation of the post-quantum cryptography algorithm and the SM2 / SM9 algorithm in an atomization mode. According to the method, deep fusion and intelligent scheduling of the two algorithms are realized on the hardware level, and the efficiency, the resource utilization rate and the safety of cooperative operation are improved.

The invention relates to the technical field of semiconductor devices, and discloses a wide bandgap power semiconductor device and a preparation method thereof. The method comprises: providing a substrate layer of a first conductivity type; forming a first doped region which is deep into the substrate layer and comprises a plurality of doped layers which are sequentially nested from outside to inside, wherein the doping concentrations of the plurality of doped layers are sequentially increased from outside to inside; forming a second doped region in the doped layer on the innermost side of the first doped region; forming an isolation layer on the first surface; forming a control electrode on the isolation layer; forming a first electrode on the first surface; a second electrode is formed on the second surface of the substrate layer. According to the invention, the first doped region which is located between the substrate layer and the second doped region and has the doping concentration gradually increased from outside to inside is formed through a mode of multiple times of ion implantation, so that transverse electric field constraint is constructed, transverse depletion of a channel region and a short channel effect under the condition of large voltage are inhibited, the channel width is reduced, and the performance of the device is improved. And the device performance and reliability are improved.

The invention discloses a high-speed low-power-consumption comparator of an SAR ADC, and relates to the technical field of analog or digital-analog hybrid integrated circuits. The comparator comprises a pre-amplification stage and a latch stage, an enable signal cp end of the pre-amplification stage is connected with an enable signal Ki, a positive input end of the pre-amplification stage is connected with a differential input positive end signal vp, a negative input end of the pre-amplification stage is connected with a differential input negative end signal vn, a positive output end vop is connected with a positive input end of the latch stage through a switch K1, and a negative output end von is connected with a positive input end of the latch stage through a switch K2. The switch K1 and the switch K2 are both controlled by an enable signal Ki; a differential input positive end signal vp is connected with the positive input end of the latch stage through a switch K3, a differential input negative end signal vn is connected with the positive input end of the latch stage through a switch K4, and the switch K3 and the switch K4 are both controlled by an inversion signal Kim of an enable signal Ki. According to the scheme, the gain and the bandwidth of the pre-amplification stage are improved, so that the speed and the precision of the pre-amplification stage are improved at the same time.

The invention discloses a volatile threshold switching device based on an atomic-scale geometric confinement layer and a preparation method thereof. The device comprises a substrate layer, a bottom electrode layer, a functional active layer, a geometric confinement layer and a top electrode layer which are stacked in sequence, the functional active layer is used for providing active metal ions to form conductive filaments; the functional active layer is made of a two-dimensional layered ferroelectric material; the geometric confinement layer is made of hexagonal boron nitride sheets, and the thickness range of the hexagonal boron nitride sheets is 1-5 hexagonal boron nitride atomic layers. According to the invention, the h-BN material with atomic-scale lattice defects is introduced as the geometric confinement layer, and the diameter of the conductive filament formed by copper ions in the functional active layer is physically limited by using the atomic-scale ion sieve effect of the h-BN material, so that the problem of failure caused by overgrowth of the filament in a traditional device is solved.

The application relates to a full GaN power electronic monolithic integrated circuit and a preparation method thereof, which comprises, from bottom to top, an insulating composite substrate, an AlN layer, a Si layer, a GaN / AlGaN buffer layer, a GaN layer and an AlGaN layer; a 2DEG layer is formed between the GaN layer and the AlGaN layer; the AlGaN layer is etched, a p-GaN layer is grown; a p-GaN layer gate portion is etched and filled with a passivation layer, and a gate metal is grown; source metal and drain metal are respectively grown on both sides of the p-GaN layer gate area; a deep groove is arranged between a driving circuit and a low-voltage tube, between a high-voltage tube and the low-voltage tube, and a medium is filled in the deep groove; and the full GaN power electronic monolithic integrated circuit is obtained through a top via and an interconnection process. The application can realize high efficiency and low power consumption, low parasitic effect, and reduce leakage current and switching loss.

The invention provides an optical waveguide and heterojunction two-dimensional material integrated nonvolatile storage structure and an application method, and relates to the technical field of photoelectron integration. A heterojunction two-dimensional material layer is arranged in an evanescent field area of an optical waveguide layer, so that when an electric field pulse is applied to the heterojunction two-dimensional material layer through a positive electrode layer and a negative electrode layer, the heterojunction two-dimensional material layer is not subjected to evanescent field pulse; the heterojunction two-dimensional material layer can generate various non-volatile heterojunction polarization states, so that the optical constant and the optical state of the non-volatile storage structure are changed, the optical state can be stored by utilizing the non-volatility, and the optical memory function is realized. Even under the condition of power failure, the stored optical state cannot be lost, and ultra-low static power consumption can be realized. The overturning of the polarization state of the heterojunction is realized by the overturning of the heterojunction domain, so that the power consumption of the nonvolatile storage structure is far lower than the heat power consumption required by a phase change memory or a thermo-optic device.

This invention relates to the field of power electronics technology, specifically to a switching relay control circuit and control method. The switching relay control circuit includes a signal control module, a power drive module, and a protection module. The signal control module receives an input control signal and outputs a drive signal. The power drive module responds to the drive signal by applying a first voltage to the relay coil to activate it, and automatically reduces the first voltage to a second voltage to maintain the activated state after activation. The second voltage is higher than the relay release voltage. The protection module provides unidirectional protection and voltage clamping for the circuit. This invention enables rapid and reliable relay activation, significantly reduces holding power consumption, and improves the circuit's anti-interference capability.

The present disclosure provides a voltage regulation circuit and a memory. The voltage regulation circuit comprises a power supply generation module, a selection control signal generation module and a voltage selection module. The power supply generation module is configured to generate a plurality of groups of transistor substrate voltages, wherein each group of transistor substrate voltages corresponds to at least one state of a sensitive amplifier. The selection control signal generation module is configured to generate a corresponding selection control signal based on the current state of the sensitive amplifier. The voltage selection module is configured to receive the plurality of groups of transistor substrate voltages and the selection control signal, and to select a corresponding group of transistor substrate voltages to output to the substrate end of a transistor in the sensitive amplifier in response to the selection control signal.

The present invention relates to the technical field of voltage detection, and specifically discloses a low static power consumption fast high and low voltage detection circuit and method, the circuit comprising: a Zener tube, the output end of which is electrically connected to the voltage to be detected; a high voltage NMOS tube, the drain of which is electrically connected to the input end of the Zener tube, and the gate of which is electrically connected to the power supply; a first and a second positive feedback NMOS tube, the gate of the first positive feedback NMOS tube and the drain of the second positive feedback NMOS tube are electrically connected to the source of the high voltage NMOS tube at the same time; a first resistor, one end of which is electrically connected to the source of the first and second positive feedback NMOS tubes at the same time, and the other end is electrically connected to the ground; a Schmidt inverter, the input of which is electrically connected to the drain of the first positive feedback NMOS tube, and the output is used as the logic signal output end of the detection circuit. The circuit structure of the present invention is simple, and a resistor voltage divider and a comparator are not used. The overall static current is not more than 1.5uA, and the high voltage detection flip delay and the low voltage detection flip delay are small, so that the low static power consumption fast high and low voltage detection function is realized.

The application provides a bionic event-driven reconfigurable analog / digital converter and electronic equipment, which comprises an adjustable signal folding circuit, a dynamic comparator circuit and a bionic control logic circuit, and any two of the adjustable signal folding circuit, the dynamic comparator circuit and the bionic control logic circuit are connected; the adjustable signal folding circuit receives an externally transmitted first voltage signal, folds the first voltage signal to obtain a to-be-compared signal under the condition of triggering a folding action, and transmits the to-be-compared signal to the dynamic comparator circuit; the dynamic comparator circuit generates a comparison result according to the received to-be-compared signal, and transmits the comparison result to the bionic control logic circuit; the bionic control logic circuit generates a bionic clock signal according to the comparison result, and transmits the bionic clock signal to the dynamic comparator circuit; and the dynamic comparator circuit is opened / closed according to the bionic clock signal. The application can reduce the static power consumption generated by the analog / digital converter during operation.

Embodiments of the present disclosure disclose an RC oscillator, an electronic device and a chip. The RC oscillator comprises: a current generation circuit comprising a transistor and a resistor, configured to output a bias current according to a power supply voltage, an inter-electrode voltage of the transistor and a resistance value of the resistor; a charging and discharging control circuit comprising a capacitor and connected to the current generation circuit, configured to charge the capacitor by the power supply voltage or discharge the capacitor by the bias current; and a logic control circuit connected to the current generation circuit and the charging and discharging control circuit, configured to compare a capacitor voltage of the capacitor with a voltage threshold determined based on the inter-electrode voltage, and control the charging and discharging control circuit to switch to a first stage or a second stage. The present disclosure does not need to design a complex voltage reference and current reference circuit, greatly simplifies the overall circuit structure, and saves chip area and power consumption.

The present invention discloses a nanosheet transistor with a heterogeneous gate dielectric and a preparation method thereof; the nanosheet transistor comprises: a substrate, a source region, a drain region, a gate material and a plurality of nanosheet channel layers; wherein the gate material covers the nanosheet channel layer to form a gate structure; the source region, the gate structure and the drain region are sequentially arranged on the substrate along the channel direction; the channel direction is the direction from the source region to the drain region; a heterogeneous gate dielectric layer is arranged between the adjacent surfaces of the gate material and the nanosheet channel layer and between the adjacent surfaces of the gate material and the substrate; the heterogeneous gate dielectric layer comprises a plurality of gate dielectric materials continuously arranged along the channel direction, and the relative dielectric constants of the plurality of gate dielectric materials gradually decrease with the channel direction; the source region is isolated from the gate region by a first isolation dielectric; the drain region is isolated from the gate region by a first isolation dielectric. The present invention reduces the short channel effect of a small-sized field effect transistor, reduces the off-state current leakage, and improves the electrical performance of a small-sized semiconductor device.

The application discloses an MCU chip and a switching method of working modes of the MCU chip, which comprises a first LDO circuit, a second LDO circuit and a switching circuit. The first LDO circuit and the second LDO circuit supply power to the MCU chip, and the switching circuit switches between the first LDO circuit and the second LDO circuit, so that the MCU chip works in different modes. The switching circuit comprises a copy controllable circuit and a copy circuit. According to the MCU chip, the copy controllable circuit copies the output current of the first LDO circuit to output a first copy current, the copy circuit copies the first copy current to output a second copy current to the second LDO circuit, the second LDO circuit establishes an internal loop based on the second copy current, and the current flow between the switching circuit and the first LDO circuit and the second LDO circuit is cut off, so that the output voltage drop caused by the transient change of the load when the first LDO circuit and the second LDO circuit are switched is avoided.

The present invention discloses an AC-coupled level shifter, belonging to the field of integrated circuits. In order to speed up the level conversion speed of high-speed signals, in the AC-coupled level shifter of the present invention, the input signal is connected to the gate of the first NMOS tube and the gate of the first PMOS tube, the source of the first PMOS tube is connected to the first device working voltage, the drain of the first PMOS tube is connected to the drain of the first NMOS tube, and the source of the first NMOS tube is connected to the first common ground terminal voltage; the drain of the first PMOS tube is also connected to the gate of the second NMOS tube and the gate of the second PMOS tube; the source of the second PMOS tube is connected to the second device working voltage, the drain of the second PMOS tube is connected to the drain of the second NMOS tube, and the source of the second NMOS tube is connected to the second common ground terminal voltage; the drain of the second PMOS tube leads to the output signal; the gate of the first NMOS tube is connected to the first end of the capacitor, and the drain of the second PMOS tube is connected to the second end of the capacitor. The present invention has the advantages of low delay and low duty cycle loss.

This application relates to the field of analog integrated circuit design and discloses an adaptive ramp compensation circuit system applied to buck-boost circuits. The system mainly includes a current sensor and a ramp signal generator. The current sensor mirrors the current of the pull-up power transistor to the pull-up mirror transistor at a specific ratio, converting it into a voltage signal through a sensing resistor. The ramp signal generator reduces the influence of the input voltage on the ramp signal slope through a voltage divider resistor network, and the switching state of the reset switch is controlled by a reset signal controlled by a pulse width modulation signal and a clock signal. By introducing a pulse width modulation control signal, this application ensures that the ramp signal generator operates only when the pull-up power transistor is on, effectively solving the subharmonic oscillation problem that may occur in buck-boost circuits when the duty cycle is greater than 50%. Simultaneously, the resistor voltage divider reduces the influence of the input voltage on the ramp signal, improving the circuit's stability and anti-interference capability.

The invention provides a low-leakage 21-tube D flip-flop circuit, which consists of ten PMOS (P-channel Metal Oxide Semiconductor) tubes P0-P9 and eleven NMOS (N-channel Metal Oxide Semiconductor) tubes N0-N10, and is characterized in that a main latch end and drain electrodes of P1 and P3 are connected with a drain electrode of N0 and grid electrodes of P4 and N3 to form a shared node i; the source electrode of the N0 is connected to a parallel node of the N10 and the N1; the grid electrode of the N0 is shared with the source electrode of the N2, the drain electrode of the P4, the drain electrode of the N3 and the grid electrode of the N4 to form an internal node ii; source electrodes of the N3 and the N4 are respectively connected with a drain electrode of the N5; the drain electrode of the N4 is connected with the drain electrode of the P5 to form a main latch structure output node iii; the grid electrode of the P5 is connected with the drain electrode of the N2; the slave latch end, the P6, the P7, the N6 and the N7 realize a cross coupling structure; the drain electrode of the N8 is connected with the source electrode of the N7; the grid electrode of the N8 and the drain electrode of the P8 are connected and jointly connected to the grid electrode of the P5 and the drain electrode of the N2; the structure is compact, and an effective solution is provided for digital chip design customized based on a standard cell library.

The utility model discloses a control circuit for speed regulation and positive and negative rotation switching of a DC motor of a laminator, which comprises an H-bridge control chip U3 integrated by field effect transistors Q1 to Q4. A first pin GND of the H-bridge control chip U3 is grounded, a second pin IN1 is the input end of PWM2, a third pin IN2 is the input end of PWM1, a fourth pin VREF is connected with a first resistor R1 and inputs reference voltage, a fifth pin VM is connected with a DC motor driving power supply and directly supplies power to the H-bridge control chip U3, a sixth pin OUT1 is connected with an inductor L3, a seventh pin ISEN is connected with a second resistor R2, an eighth pin OUT2 is connected with an inductor L2, the inductor L2 is connected with the positive electrode end of a DC motor, and the positive electrode end of the DC motor is connected with the negative electrode end of the DC motor. The inductor L3 is connected with the negative electrode end of the DC motor. The rotation speed of the DC motor is controlled by performing pulse width modulation (PWM) on an input signal, and forward and reverse rotation of the DC motor is switched.

The invention belongs to the field of power supplies, and provides a differential current compensation level shift circuit applied to a high-speed power supply system, which comprises a level shift module, the level shift module comprises a current mirror with a cross coupling structure, a main branch and a slave branch of the current mirror are respectively connected with source electrodes of different high-voltage LDMOS (Laterally Diffused Metal Oxide Semiconductor) tubes, and the source electrodes of the high-voltage LDMOS tubes are connected with the current mirror; grid electrodes of the two high-voltage LDMOS tubes input level signals needing to be latched respectively. The current mirror comprises two first current mirror units and two second current mirror units which form symmetrical structures. The latch module is used for latching a level signal output by the current mirror and comprises two first phase inverters and two second phase inverters, the two first phase inverters are connected with each other to form a storage unit, the positive input ends of the other two second phase inverters are connected to the storage unit, and the negative input ends of the other two second phase inverters are connected to the storage unit. The two first current mirror units are respectively connected with outputs of the two first current mirror units; according to the level shift circuit, the dv / dt change resistance of the level shift circuit can be improved while the signal transmission speed is not affected.

This application relates to the field of in-memory computing memory technology, and more particularly to a three-dimensional ferroelectric memory with an IGZO channel and its fabrication method. The three-dimensional ferroelectric memory with an IGZO channel includes: a bottom global gate line; a center select gate extending vertically relative to the bottom global gate line; a semiconductor stack structure including a gate metal layer, a ferroelectric layer, a gate oxide layer, and an IGZO channel sequentially surrounding the center select gate; a drain and a source extending horizontally relative to the center select gate into the semiconductor stack structure and contacting the ferroelectric layer; and multiple pairs of drains and sources spaced apart along the extension direction of the center select gate to form multiple ferroelectric memory transistor cells. The three-dimensional ferroelectric memory with an IGZO channel of this application improves the durability and reliability of non-volatile memory devices.

This application relates to an unlocking system, unlocking method, and vehicle. The power management module is configured to: in a sleep state, generate a first wake-up signal based on the door switch trigger time, and in response to the first wake-up signal, switch to a wake-up state, control the switch module to close, and send a second wake-up signal. The vehicle controller is configured to: in response to the second wake-up signal, wake up the near-field communication module to verify the key; after successful verification, if a key unlocking signal is received within a preset unlocking time, drive the unlocking / locking actuator to unlock; otherwise, generate a sleep signal. The power management module is also configured to: in response to the sleep signal, control the switch module to disconnect and switch to a sleep state. This application can solve the problems in related technologies where maintaining constant power to some modules to maintain the unlocking function accelerates battery depletion and damage; and where a complete power outage lacks an effective wake-up mechanism to restore system power for unlocking.

This invention discloses a multifunctional handheld electronic device and its control method, relating to the field of electronic product technology. The multifunctional handheld electronic device includes a grip component, a circuit board, and an expansion component. A first switch is mounted on the grip component and electrically connected to the circuit board. The circuit board, also mounted on the grip component, integrates a first functional module and a second switch. The expansion component is detachably connected to the grip component and is equipped with the second functional module. When the expansion component is mounted on the grip component, the second functional module is electrically connected to the circuit board, the second switch is in a first state, and the first switch controls the activation and deactivation of the second functional module. When the expansion component is not mounted on the grip component, the second switch is in a second state, and the first switch controls the activation and deactivation of the first functional module. By automatically switching the control object with a single button, the modular and rapid expansion of functions is achieved.

The utility model relates to an intelligent gas meter dual power supply switching power supply circuit, which adopts dual power supply design, automatically switches to the power supply with higher voltage by utilizing the voltage drop characteristic of diode, and does not need external control unit. At the same time, super capacitor is added as backup power supply to provide emergency power supply when dual power supply is powered off, ensuring data storage and valve operation. The power output module also has power supply control function, and realizes intermittent power supply or constant power supply through MOS tube, meeting the low power consumption requirement. In addition, the voltage conversion module works cooperatively to meet the high and low voltage load requirement, reduce power consumption, and prolong battery life. This design significantly improves the stability and reliability of the intelligent gas meter power supply system, providing users with more durable and stable use experience.

The utility model provides a working circuit of a PTC heater based on CAN communication. The working circuit is used for reducing power loss of a control side of the PTC heater. The working circuit comprises a low-voltage-side electrical area and a high-voltage-side electrical area, and the low-voltage-side electrical area and the high-voltage-side electrical area are connected through a digital isolation chip. The working circuit comprises three DCDC circuits, two circuits for converting DCDC into 5V adopt a BUCK topological structure and have very high conversion efficiency compared with an LDO (Low Dropout Regulator) circuit adopted in the traditional controller design, and the other DCDC flyback topological circuit adopts a flyback power supply control chip with an enabling function, so that when the PTC heater works normally, the PTC heater can be switched to 5V, and the conversion efficiency is very high. If the control command is not received for a long time, the MCU of the PTC heater forbids the enabling function of the flyback power supply control chip, so that the high-voltage side power supply is disconnected to achieve the purpose of reducing the working power consumption; in addition, the voltage reduction function is achieved on the high-voltage side and the low-voltage side through the DCDC circuit, so that the use efficiency of the power supply is greatly improved, and the purpose of reducing the power consumption of the PTC heater control area is achieved.

The utility model discloses a kind of MCU power supply control circuit of linear drive device, controller and electric furniture, for realizing the zero power consumption standby of MCU and load wake-up.The technical scheme is: in standby state, MCU is completely powered off, but a DC output port remains electrified.When external load is connected to the DC output port and generates current, a passive detection circuit consisting of sampling unit and detection unit generates trigger signal, the trigger signal turns on a first switching unit, thereby connecting the power supply of MCU, wakes up MCU to perform subsequent tasks.The utility model triggers MCU power-on by passive detection mode, completely solves the standby power consumption problem of equipment, simple structure, response sensitive.

The application relates to electromagnetic vibration conversion technology and discloses an electromagnetic vibration conversion system which comprises an electromagnetic vibration conversion electromechanical mechanism and a braking circuit connected in parallel at two input ends of the electromagnetic vibration conversion electromechanical mechanism, and the equivalent resistance of the braking circuit ranges from 0.001R L to 99.9R L , wherein R L is the impedance of the electromagnetic vibration conversion electromechanical mechanism. When the electromagnetic vibration conversion electromechanical mechanism works, the back electromotive force generated by free vibration is more distributed to the internal resistance of the electromagnetic vibration conversion electromechanical mechanism, so that the electromagnetic braking effect of the electromagnetic vibration conversion electromechanical mechanism is increased, the unnecessary free vibration is weakened, and the energy output distortion degree is reduced.

This invention discloses a high PSR, low power consumption, capacitor-free N-type low-dropout linear regulator, belonging to the field of analog integrated circuits. The regulator includes an error amplifier, a voltage buffer, a PSR enhancement circuit, and an NMOS power transistor. The voltage buffer uses a unity-gain negative feedback configuration, employing a smaller quiescent current at the same output impedance. At the output voltage... V OUT When the voltage rises, the error amplifier and voltage buffer suppress the rise through a negative feedback loop. V OUT To achieve circuit stability, the PSR enhancement circuit uses a high-pass filter for sampling. V OUT Ripple at mid-to-high frequencies creates negative feedback, generating gain that acts on... V OUT This ultimately improves power supply rejection at mid-to-high frequencies. Compared to PMOS transistors, using NMOS transistors as power transistors allows for a smaller footprint while maintaining the same current. This invention offers advantages such as low power consumption, high PSR, and small footprint, making it suitable for mobile smart terminals, embedded systems, low-power IoT devices, and various high-precision analog circuit systems sensitive to power supply noise.

A three-state content addressable memory and a storage unit thereof are proposed. The three-state content addressable storage unit includes a first transistor and a second transistor. The first transistor has a gate terminal for receiving a selection signal, a first terminal of the first transistor is coupled to a matching line, and a second terminal of the first transistor is coupled to a source line. The second transistor has a gate terminal for receiving a reverse selection signal, a first terminal of the second transistor is coupled to a matching line, and a second terminal of the second transistor is coupled to a source line. The first transistor and the second transistor both have a charge storage structure.

The application relates to the technical field of chip circuits, in particular to a special chip ADC circuit for a retinal prosthesis, which comprises a sampling switch module, a capacitor array module, a dynamic comparator, a digital control logic module and a digital correction module; the capacitor array module comprises a P-end capacitor array and an N-end capacitor array, the P-end capacitor array comprises a plurality of first capacitors connected in parallel, and each first capacitor is connected with a first control switch; the N-end capacitor array comprises a plurality of second capacitors connected in parallel, and each second capacitor is connected with a second control switch; the same direction end of the dynamic comparator is connected with the end capacitor of the P-end capacitor array, and the reverse end of the dynamic comparator is connected with the end capacitor of the N-end capacitor array; the digital control logic module is connected with the output end of the dynamic comparator; and the digital correction module is connected with the output end of the digital control logic module. The ADC circuit provided by the application is used for converting a sensor analog signal into a digital signal and realizes low power consumption and high resolution.