110results about How to "Reduce static power consumption" patented technology

The invention relates to the technical field of low-power-consumption AI processors, and discloses a load balancing method of a low-power-consumption AI processor, a chip and a storage medium, the method comprises the following steps: performing cache resource division on a plurality of neural mimicry cores in the low-power-consumption AI processor to obtain a double-layer cache structure; performing characteristic analysis on the target calculation task, and constructing a calculation task directed acyclic graph and a dependency intensity matrix; performing task segmentation to obtain a subtask division scheme; creating a task-core mapping table; organizing the neural mimicry core into a plurality of concentric ring layers based on the task-core mapping table to obtain a multi-layer ring cooperative computing network; and calculating a plurality of performance indexes of each neural mimicry core based on the multilayer annular cooperative computing network, and performing dynamic load optimization to obtain a dynamic load optimization strategy. According to the invention, the load balancing of the low-power AI processor is realized, and the calculation efficiency and the energy utilization rate are improved.

The invention discloses a digital auxiliary simulation LDO circuit without an off-chip capacitor. A simulation main loop of the circuit comprises an error amplifier, a buffer stage circuit, a simulation power stage circuit and a VG voltage detection circuit. The digital auxiliary loop includes a digital control logic circuit, a ring oscillator circuit, and a digital power stage circuit. By introducing the digital power adjusting tube, the parasitic capacitance of the grid electrode of the analog power tube is reduced, the pole of the grid electrode is located at high frequency, and on the basis, the super source follower is added to push the pole to higher frequency, so that the circuit has better loop stability. In a steady state, the digital auxiliary loop is forbidden, and the analog main loop can ensure strict adjustment, low quiescent current and no switching noise at the output end; when a load current suddenly changes, a ring oscillator in the digital auxiliary loop is called to generate a clock signal, and the number of conducted digital power tubes is changed, so that response time is not limited by a clock period, dependence on an external clock is avoided, meanwhile, voltage precision and rapid transient response are guaranteed, and static power consumption of the circuit is reduced.

The present invention proposes a circuit and working method for realizing power supply monitoring with high efficiency and low power consumption, including a voltage divider circuit, a reference voltage source, a comparator, a high-speed power-on detection circuit, a NOR gate, a clock generation and shutdown circuit, a delay module and an output drive module. The voltage divider circuit is used to generate a reset threshold voltage that is proportional to the input voltage; the reference voltage source is used to generate a reference voltage that is independent of the power supply voltage and temperature; the comparator is used to compare the voltage after voltage division with the reference voltage; the high-speed power-on detection circuit is used to generate an on-chip reset signal of a power supply monitoring circuit with anti-interference capability; the clock generation and shutdown circuit is used to generate a clock signal of a delay unit and shut down a clock generation circuit; and the delay module is used for timing. It introduces a high-speed power-on detection circuit to avoid the reset failure problem caused by the comparator failing to flip in time or the power supply glitch interference, and at the same time introduces a clock shutdown circuit to effectively reduce power consumption.

The invention discloses a micro electric field sensing device based on electrostatic force and piezoresistive effect coupling, which is characterized in that the micro electric field sensing device comprises a semiconductor film which is horizontally placed and can vertically and freely vibrate, and a metal film is arranged on the first surface of the semiconductor film; the second surface of the semiconductor film is connected with a boss structure and a substrate layer through a buried oxide layer, wherein the boss structure is formed by combining the peninsula-end cross beam and the arc-petal-shaped island; the periphery of the semiconductor film is connected with the fixed part of the device layer; the device layer is provided with a metal electrode area and four arc-shaped short beams, and the metal film is connected to the metal electrode area through the arc-shaped short beams; a plurality of ion implantation areas are embedded in the arc-shaped short beam, and groove structures are arranged among the ion implantation areas; and the ion implantation region forms a Wheatstone bridge structure through the metal electrode region. The miniature electric field sensing device has the advantages of being small in size, low in cost and power consumption, high in sensitivity, high in resolution, wide in linear range, high in structural stability and the like, and can be widely applied to the field of electric field sensing.

The invention discloses a logic lookup table circuit, which comprises a decoder circuit, a read control circuit, an MRAM (Magnetic Random Access Memory) storage circuit, a discharge read circuit, a reference unit circuit and a first NMOS (N-channel Metal Oxide Semiconductor) tube, the MRAM storage circuit has non-volatility, and the read control circuit only selects a certain storage unit in the MRAM storage circuit under the control of the decoder circuit; the storage unit is communicated with the discharge reading circuit and the first NMOS tube respectively, the discharge reading circuit can be discharged to the ground through the first NMOS tube, the storage state voltage of the storage unit is output to the amplifier circuit, and the reference unit circuit is communicated with the discharge reading circuit and the first NMOS tube respectively under the control of an external read enable signal, so that the storage state voltage of the storage unit is output to the amplifier circuit. Enabling the discharge reading circuit to discharge to the ground through a first NMOS tube, enabling the reference unit circuit to output a reference voltage to the amplifier circuit, and enabling the amplifier circuit to compare the storage state voltage with the reference voltage; the device has the advantages of small static power consumption, small transmission delay, and no disappearance of stored data even if the device is disconnected with a power supply.

The present invention relates to the technical field of low-power AI processors, and discloses a load balancing method, chip and storage medium of a low-power AI processor, the method comprising: partitioning cache resources for multiple neuromorphic cores in a low-power AI processor to obtain a double-layer cache structure; performing characteristic analysis on a target computing task, and constructing a directed acyclic graph of computing tasks and a dependency strength matrix; performing task segmentation to obtain a subtask partitioning scheme; creating a task-core mapping table; based on the task-core mapping table, organizing the neuromorphic core into multiple concentric ring layers to obtain a multi-layer ring collaborative computing network; based on the multi-layer ring collaborative computing network, calculating multiple performance indicators of each neuromorphic core, and performing dynamic load optimization to obtain a dynamic load optimization strategy. The present invention realizes load balancing of a low-power AI processor, and improves computing efficiency and energy utilization.

The invention discloses a power-on and power-off management method and device of a vehicle machine system, a storage medium and an electric vehicle, and belongs to the technical field of electric vehicles. When the power-off signal is received, detecting whether the electric vehicle is in a charging state; if the SOC is in the charging state, the in-vehicle infotainment system is controlled to enter a first state, and the first state means that the SOC is kept working normally, a screen is lightened to display charging information, and a power supply of peripheral equipment is cut off; if the SOC is not in the charging state, the vehicle machine system is controlled to enter a second state, and the second state means that the SOC is kept working normally, backlight of a screen is turned off, and a power supply of peripheral equipment is cut off; timing is started when the electric car is in the second state, and state information of the electric car is obtained in the timing process; and determining whether to control the vehicle machine system to enter a network dormancy state, wherein the network dormancy state refers to cutting off the power supply of the SOC and the screen. When the electric vehicle is used again after temporary parking and power-off, the time for waiting for SOC restarting is saved, and the static power consumption when the electric vehicle is not used for a long time can also be reduced.

The invention provides a PQC and SM2 / 9 cooperative operation cryptographic chip and method based on an RISC-V architecture, and belongs to the technical field of cryptographic security. The chip comprises an RISC-V core and a configurable password collaborative operation unit, wherein the configurable password collaborative operation unit comprises a collaborative control state machine and a unified operation unit capable of being dynamically reconfigured. The method comprises the following steps: receiving and decoding a single cooperative operation instruction from an RISC-V core through a cooperative control state machine, and obtaining operation data feature information; the data length and the security level identification are extracted, and the optimal collaborative operation process is selected in a self-adaptive mode through comparison with a preset threshold value; and finally, dynamically configuring and scheduling a unified operation unit according to the selected process, and completing cooperative operation of the post-quantum cryptography algorithm and the SM2 / SM9 algorithm in an atomization mode. According to the method, deep fusion and intelligent scheduling of the two algorithms are realized on the hardware level, and the efficiency, the resource utilization rate and the safety of cooperative operation are improved.

The invention discloses an LDO (Low Dropout Regulator) circuit based on current feedback, which comprises a transconductance amplifier for amplifying reference voltage into current and inputting the current into a positive phase input end of an error transresistance amplifier; the error transimpedance amplifier, the buffer, the second PMOS transistor, the first PMOS transistor and the current-current feedback network form an error current feedback loop, the negative phase input end of the error transimpedance amplifier receives feedback current from the current-current feedback network, and the output end of the error transimpedance amplifier outputs error voltage; the buffer receives the error voltage output by the error trans-impedance amplifier, generates a buffer stage output voltage and drives the second PMOS tube to generate an output voltage; the first PMOS transistor is used for detecting fluctuation of output voltage, if the output voltage fluctuates, current flowing through the first PMOS transistor changes, the current-current feedback network generates feedback current according to the current change of the first PMOS transistor, the feedback current is input to the negative phase input end of the error trans-impedance amplifier, and fluctuation of the output voltage is counteracted.

The invention relates to the technical field of semiconductor devices, and discloses a wide bandgap power semiconductor device and a preparation method thereof. The method comprises: providing a substrate layer of a first conductivity type; forming a first doped region which is deep into the substrate layer and comprises a plurality of doped layers which are sequentially nested from outside to inside, wherein the doping concentrations of the plurality of doped layers are sequentially increased from outside to inside; forming a second doped region in the doped layer on the innermost side of the first doped region; forming an isolation layer on the first surface; forming a control electrode on the isolation layer; forming a first electrode on the first surface; a second electrode is formed on the second surface of the substrate layer. According to the invention, the first doped region which is located between the substrate layer and the second doped region and has the doping concentration gradually increased from outside to inside is formed through a mode of multiple times of ion implantation, so that transverse electric field constraint is constructed, transverse depletion of a channel region and a short channel effect under the condition of large voltage are inhibited, the channel width is reduced, and the performance of the device is improved. And the device performance and reliability are improved.

The invention discloses a high-speed low-power-consumption comparator of an SAR ADC, and relates to the technical field of analog or digital-analog hybrid integrated circuits. The comparator comprises a pre-amplification stage and a latch stage, an enable signal cp end of the pre-amplification stage is connected with an enable signal Ki, a positive input end of the pre-amplification stage is connected with a differential input positive end signal vp, a negative input end of the pre-amplification stage is connected with a differential input negative end signal vn, a positive output end vop is connected with a positive input end of the latch stage through a switch K1, and a negative output end von is connected with a positive input end of the latch stage through a switch K2. The switch K1 and the switch K2 are both controlled by an enable signal Ki; a differential input positive end signal vp is connected with the positive input end of the latch stage through a switch K3, a differential input negative end signal vn is connected with the positive input end of the latch stage through a switch K4, and the switch K3 and the switch K4 are both controlled by an inversion signal Kim of an enable signal Ki. According to the scheme, the gain and the bandwidth of the pre-amplification stage are improved, so that the speed and the precision of the pre-amplification stage are improved at the same time.

The invention discloses an LDO (Low Dropout Regulator) circuit with high PSR (Power Supply Response) and enhanced transient response, which comprises an LDO basic circuit, a biasing circuit, a feedforward power supply ripple elimination path, an overshoot suppression path and an undershoot suppression path, wherein the biasing circuit and the LDO basic circuit are connected with the feedforward power supply ripple elimination path, the overshoot suppression path and the undershoot suppression path. All devices in the feedforward power supply ripple elimination path can be set based on the size of a power tube in the LDO basic circuit to offset power supply ripples, and therefore the PSR of the LDO circuit is improved. The feedforward power supply ripple elimination path and the undershoot suppression path are combined to realize circuit multiplexing, so that the static power consumption of the LDO circuit is reduced. The overshoot suppression path and the undershoot suppression path increase the conversion rate of an output node in a feedback mode, so that the transient response of the LDO circuit to large load changes is enhanced, and the overshoot voltage and the undershoot voltage of the output end are reduced.

The invention discloses a voltage stabilizer and a control method thereof, and the voltage stabilizer comprises a voltage reference circuit, a buffer circuit, a transmission circuit and an output circuit. The input end of the buffer circuit receives reference voltage provided by the voltage reference circuit, and the output end of the buffer circuit is connected to the input end of the transmission circuit; the output end of the transmission circuit is connected with the input end of the output circuit, and the output end of the output circuit is connected with a load. Through a control method of proportional adjustment of load current and buffer circuit current and combination of an awakening state and a dormant state, the voltage stabilizer disclosed by the invention has the beneficial effects of small area, high precision and ultra-low power consumption.

The invention discloses a volatile threshold switching device based on an atomic-scale geometric confinement layer and a preparation method thereof. The device comprises a substrate layer, a bottom electrode layer, a functional active layer, a geometric confinement layer and a top electrode layer which are stacked in sequence, the functional active layer is used for providing active metal ions to form conductive filaments; the functional active layer is made of a two-dimensional layered ferroelectric material; the geometric confinement layer is made of hexagonal boron nitride sheets, and the thickness range of the hexagonal boron nitride sheets is 1-5 hexagonal boron nitride atomic layers. According to the invention, the h-BN material with atomic-scale lattice defects is introduced as the geometric confinement layer, and the diameter of the conductive filament formed by copper ions in the functional active layer is physically limited by using the atomic-scale ion sieve effect of the h-BN material, so that the problem of failure caused by overgrowth of the filament in a traditional device is solved.

The application relates to a full GaN power electronic monolithic integrated circuit and a preparation method thereof, which comprises, from bottom to top, an insulating composite substrate, an AlN layer, a Si layer, a GaN / AlGaN buffer layer, a GaN layer and an AlGaN layer; a 2DEG layer is formed between the GaN layer and the AlGaN layer; the AlGaN layer is etched, a p-GaN layer is grown; a p-GaN layer gate portion is etched and filled with a passivation layer, and a gate metal is grown; source metal and drain metal are respectively grown on both sides of the p-GaN layer gate area; a deep groove is arranged between a driving circuit and a low-voltage tube, between a high-voltage tube and the low-voltage tube, and a medium is filled in the deep groove; and the full GaN power electronic monolithic integrated circuit is obtained through a top via and an interconnection process. The application can realize high efficiency and low power consumption, low parasitic effect, and reduce leakage current and switching loss.

The invention provides an optical waveguide and heterojunction two-dimensional material integrated nonvolatile storage structure and an application method, and relates to the technical field of photoelectron integration. A heterojunction two-dimensional material layer is arranged in an evanescent field area of an optical waveguide layer, so that when an electric field pulse is applied to the heterojunction two-dimensional material layer through a positive electrode layer and a negative electrode layer, the heterojunction two-dimensional material layer is not subjected to evanescent field pulse; the heterojunction two-dimensional material layer can generate various non-volatile heterojunction polarization states, so that the optical constant and the optical state of the non-volatile storage structure are changed, the optical state can be stored by utilizing the non-volatility, and the optical memory function is realized. Even under the condition of power failure, the stored optical state cannot be lost, and ultra-low static power consumption can be realized. The overturning of the polarization state of the heterojunction is realized by the overturning of the heterojunction domain, so that the power consumption of the nonvolatile storage structure is far lower than the heat power consumption required by a phase change memory or a thermo-optic device.

This invention relates to the field of power electronics technology, specifically to a switching relay control circuit and control method. The switching relay control circuit includes a signal control module, a power drive module, and a protection module. The signal control module receives an input control signal and outputs a drive signal. The power drive module responds to the drive signal by applying a first voltage to the relay coil to activate it, and automatically reduces the first voltage to a second voltage to maintain the activated state after activation. The second voltage is higher than the relay release voltage. The protection module provides unidirectional protection and voltage clamping for the circuit. This invention enables rapid and reliable relay activation, significantly reduces holding power consumption, and improves the circuit's anti-interference capability.

The present disclosure provides a voltage regulation circuit and a memory. The voltage regulation circuit comprises a power supply generation module, a selection control signal generation module and a voltage selection module. The power supply generation module is configured to generate a plurality of groups of transistor substrate voltages, wherein each group of transistor substrate voltages corresponds to at least one state of a sensitive amplifier. The selection control signal generation module is configured to generate a corresponding selection control signal based on the current state of the sensitive amplifier. The voltage selection module is configured to receive the plurality of groups of transistor substrate voltages and the selection control signal, and to select a corresponding group of transistor substrate voltages to output to the substrate end of a transistor in the sensitive amplifier in response to the selection control signal.

The present invention relates to the technical field of voltage detection, and specifically discloses a low static power consumption fast high and low voltage detection circuit and method, the circuit comprising: a Zener tube, the output end of which is electrically connected to the voltage to be detected; a high voltage NMOS tube, the drain of which is electrically connected to the input end of the Zener tube, and the gate of which is electrically connected to the power supply; a first and a second positive feedback NMOS tube, the gate of the first positive feedback NMOS tube and the drain of the second positive feedback NMOS tube are electrically connected to the source of the high voltage NMOS tube at the same time; a first resistor, one end of which is electrically connected to the source of the first and second positive feedback NMOS tubes at the same time, and the other end is electrically connected to the ground; a Schmidt inverter, the input of which is electrically connected to the drain of the first positive feedback NMOS tube, and the output is used as the logic signal output end of the detection circuit. The circuit structure of the present invention is simple, and a resistor voltage divider and a comparator are not used. The overall static current is not more than 1.5uA, and the high voltage detection flip delay and the low voltage detection flip delay are small, so that the low static power consumption fast high and low voltage detection function is realized.

The application provides a bionic event-driven reconfigurable analog / digital converter and electronic equipment, which comprises an adjustable signal folding circuit, a dynamic comparator circuit and a bionic control logic circuit, and any two of the adjustable signal folding circuit, the dynamic comparator circuit and the bionic control logic circuit are connected; the adjustable signal folding circuit receives an externally transmitted first voltage signal, folds the first voltage signal to obtain a to-be-compared signal under the condition of triggering a folding action, and transmits the to-be-compared signal to the dynamic comparator circuit; the dynamic comparator circuit generates a comparison result according to the received to-be-compared signal, and transmits the comparison result to the bionic control logic circuit; the bionic control logic circuit generates a bionic clock signal according to the comparison result, and transmits the bionic clock signal to the dynamic comparator circuit; and the dynamic comparator circuit is opened / closed according to the bionic clock signal. The application can reduce the static power consumption generated by the analog / digital converter during operation.

The utility model discloses a reverse connection protection circuit and a vehicle-mounted refrigerator compressor controller, the reverse connection protection circuit is used in the vehicle-mounted refrigerator compressor controller, and the reverse connection protection circuit comprises an MOS tube, a divider resistor and a voltage stabilizing diode. The drain electrode of the MOS tube is connected with the negative electrode of the external input circuit, and the source electrode of the MOS tube is connected with the negative electrode output end of the external input circuit. One end of the divider resistor is connected with the positive electrode of an external input circuit, the other end of the divider resistor is connected with the negative electrode of a voltage stabilizing diode, and the other end of the divider resistor is also connected with the grid electrode of the MOS tube. The positive electrode of the voltage stabilizing diode is connected with the source electrode of the MOS tube, and the negative electrode of the voltage stabilizing diode is also connected with the grid electrode of the MOS tube; wherein the grid electrode of the MOS tube is also connected with a main control chip, and the main control chip is used for controlling a post-stage circuit to stop.

Embodiments of the present disclosure disclose an RC oscillator, an electronic device and a chip. The RC oscillator comprises: a current generation circuit comprising a transistor and a resistor, configured to output a bias current according to a power supply voltage, an inter-electrode voltage of the transistor and a resistance value of the resistor; a charging and discharging control circuit comprising a capacitor and connected to the current generation circuit, configured to charge the capacitor by the power supply voltage or discharge the capacitor by the bias current; and a logic control circuit connected to the current generation circuit and the charging and discharging control circuit, configured to compare a capacitor voltage of the capacitor with a voltage threshold determined based on the inter-electrode voltage, and control the charging and discharging control circuit to switch to a first stage or a second stage. The present disclosure does not need to design a complex voltage reference and current reference circuit, greatly simplifies the overall circuit structure, and saves chip area and power consumption.

The present invention discloses a nanosheet transistor with a heterogeneous gate dielectric and a preparation method thereof; the nanosheet transistor comprises: a substrate, a source region, a drain region, a gate material and a plurality of nanosheet channel layers; wherein the gate material covers the nanosheet channel layer to form a gate structure; the source region, the gate structure and the drain region are sequentially arranged on the substrate along the channel direction; the channel direction is the direction from the source region to the drain region; a heterogeneous gate dielectric layer is arranged between the adjacent surfaces of the gate material and the nanosheet channel layer and between the adjacent surfaces of the gate material and the substrate; the heterogeneous gate dielectric layer comprises a plurality of gate dielectric materials continuously arranged along the channel direction, and the relative dielectric constants of the plurality of gate dielectric materials gradually decrease with the channel direction; the source region is isolated from the gate region by a first isolation dielectric; the drain region is isolated from the gate region by a first isolation dielectric. The present invention reduces the short channel effect of a small-sized field effect transistor, reduces the off-state current leakage, and improves the electrical performance of a small-sized semiconductor device.

The application discloses an MCU chip and a switching method of working modes of the MCU chip, which comprises a first LDO circuit, a second LDO circuit and a switching circuit. The first LDO circuit and the second LDO circuit supply power to the MCU chip, and the switching circuit switches between the first LDO circuit and the second LDO circuit, so that the MCU chip works in different modes. The switching circuit comprises a copy controllable circuit and a copy circuit. According to the MCU chip, the copy controllable circuit copies the output current of the first LDO circuit to output a first copy current, the copy circuit copies the first copy current to output a second copy current to the second LDO circuit, the second LDO circuit establishes an internal loop based on the second copy current, and the current flow between the switching circuit and the first LDO circuit and the second LDO circuit is cut off, so that the output voltage drop caused by the transient change of the load when the first LDO circuit and the second LDO circuit are switched is avoided.

The invention discloses a low-power-consumption TIA circuit for electric energy detection, and relates to the technical field of integrated circuits, the low-power-consumption TIA circuit comprises a ClassAB output stage circuit with a floating current source, the circuit is composed of MOSTT tubes M21, M22, M23, M24, M25, M26, M27 and M28, the floating current source is formed by the MOSTT tube 21 and the MOSTT tube 22, stable voltage bias is provided for grid electrodes of the MOSTT tube 23 and the MOSTT tube 24, and the floating current source is used for providing stable voltage bias for grid electrodes of the MOSTT tube 23 and the MOSTT tube 24. According to the low-power-consumption TIA circuit for electric energy detection, the power consumption of an electric energy metering circuit is reduced by using the TIA circuit with a ClassAB output stage, and the linearity of an input signal of the electric energy metering circuit is increased, so that the problem of high power consumption of a traditional TIA circuit is solved, and the static power consumption of the electric energy metering circuit can be further reduced.

The embodiment of the invention discloses a cabin car infotainment electricity supplementing control method and device, computer equipment and a storage medium. The method comprises the steps that according to car infotainment state information obtained by a car infotainment controller, the starting state of a car infotainment is judged; if the vehicle-mounted terminal is in the shutdown state, performing power supply control on the vehicle-mounted terminal according to a preset first power supply strategy; the first charging strategy comprises the step of judging whether the vehicle-mounted terminal meets a preset awakening condition or not; if the vehicle-mounted terminal meets the awakening condition, awakening a controller local area network connected with the vehicle-mounted terminal; according to the vehicle machine state information, judging whether the vehicle machine meets a preset upper high voltage condition or not; if the vehicle machine meets the high-voltage condition, generating a high-voltage request signal; and the vehicle-mounted battery performs high-voltage charging work on the vehicle machine according to the received high-voltage charging request signal. According to the method, under the condition that the vehicle is not used for a long time, it can be ensured that the vehicle machine is automatically charged when needed, over-discharge of the battery is prevented, and therefore the performance and the service life of the vehicle-mounted battery are protected.

The present invention discloses an AC-coupled level shifter, belonging to the field of integrated circuits. In order to speed up the level conversion speed of high-speed signals, in the AC-coupled level shifter of the present invention, the input signal is connected to the gate of the first NMOS tube and the gate of the first PMOS tube, the source of the first PMOS tube is connected to the first device working voltage, the drain of the first PMOS tube is connected to the drain of the first NMOS tube, and the source of the first NMOS tube is connected to the first common ground terminal voltage; the drain of the first PMOS tube is also connected to the gate of the second NMOS tube and the gate of the second PMOS tube; the source of the second PMOS tube is connected to the second device working voltage, the drain of the second PMOS tube is connected to the drain of the second NMOS tube, and the source of the second NMOS tube is connected to the second common ground terminal voltage; the drain of the second PMOS tube leads to the output signal; the gate of the first NMOS tube is connected to the first end of the capacitor, and the drain of the second PMOS tube is connected to the second end of the capacitor. The present invention has the advantages of low delay and low duty cycle loss.

The invention discloses an ultrasonic programmable digital modulation method with current-limiting protection and an excitation circuit. The circuit comprises an MCU microprocessor, a digital modulator, a signal receiving amplifier, an analog-to-digital converter, a programmable excitation control circuit, a transmit-receive change-over switch SW1 and a sampling impedance matching circuit connected with an ultrasonic sensor. The MCU microprocessor is used for receiving a sampling signal of the ultrasonic sensor and controlling the digital modulator to output an excitation signal; the programmable excitation control circuit comprises four field-effect tubes forming a full-bridge circuit, and a resistor R1 is connected in series with a power main loop to limit the maximum current and play a role in excitation current-limiting protection; the ultrasonic sensor and the sampling impedance matching circuit are connected and communicated with the signal receiving amplifier, the analog-to-digital converter and the MCU microprocessor through a pin 1 and a pin 3 of the SW1, and a sampling signal of the ultrasonic sensor is read by the MCU microprocessor through the signal receiving amplifier and the analog-to-digital converter.

This application relates to the field of analog integrated circuit design and discloses an adaptive ramp compensation circuit system applied to buck-boost circuits. The system mainly includes a current sensor and a ramp signal generator. The current sensor mirrors the current of the pull-up power transistor to the pull-up mirror transistor at a specific ratio, converting it into a voltage signal through a sensing resistor. The ramp signal generator reduces the influence of the input voltage on the ramp signal slope through a voltage divider resistor network, and the switching state of the reset switch is controlled by a reset signal controlled by a pulse width modulation signal and a clock signal. By introducing a pulse width modulation control signal, this application ensures that the ramp signal generator operates only when the pull-up power transistor is on, effectively solving the subharmonic oscillation problem that may occur in buck-boost circuits when the duty cycle is greater than 50%. Simultaneously, the resistor voltage divider reduces the influence of the input voltage on the ramp signal, improving the circuit's stability and anti-interference capability.

The invention provides a low-leakage 21-tube D flip-flop circuit, which consists of ten PMOS (P-channel Metal Oxide Semiconductor) tubes P0-P9 and eleven NMOS (N-channel Metal Oxide Semiconductor) tubes N0-N10, and is characterized in that a main latch end and drain electrodes of P1 and P3 are connected with a drain electrode of N0 and grid electrodes of P4 and N3 to form a shared node i; the source electrode of the N0 is connected to a parallel node of the N10 and the N1; the grid electrode of the N0 is shared with the source electrode of the N2, the drain electrode of the P4, the drain electrode of the N3 and the grid electrode of the N4 to form an internal node ii; source electrodes of the N3 and the N4 are respectively connected with a drain electrode of the N5; the drain electrode of the N4 is connected with the drain electrode of the P5 to form a main latch structure output node iii; the grid electrode of the P5 is connected with the drain electrode of the N2; the slave latch end, the P6, the P7, the N6 and the N7 realize a cross coupling structure; the drain electrode of the N8 is connected with the source electrode of the N7; the grid electrode of the N8 and the drain electrode of the P8 are connected and jointly connected to the grid electrode of the P5 and the drain electrode of the N2; the structure is compact, and an effective solution is provided for digital chip design customized based on a standard cell library.