10 results about "Residue amplifier" patented technology

The invention discloses a high-speed and high-linearity margin amplifier and an analog-to-digital converter, belongs to the technical field of integrated circuits, and solves the technical problem that an existing source follower cannot meet high-speed and high-linearity indexes. The amplifier comprises a margin amplifier bias and output module, a phase inverter and a linear transconductance unit based on an AB-class super source follower structure, wherein the bias and output module, the linear transconductance unit and the phase inverter are connected in sequence. The linear transconductance unit can generate high-linearity transconductance, so that the linearity of the whole margin amplifier is improved, the symmetry of the positive output end and the negative output end of the margin amplifier under the condition of high-frequency or large-swing input can be ensured, and the high-speed and high-linearity index can be effectively met. In addition, a gain calibration module resistant to temperature and process changes is further introduced, and the influence caused by follow-up system environment temperature changes can be automatically compensated.

A calibration method of a pipeline analog-to-digital converter (ADC) that includes a residue amplifier includes the following steps: (A) generating an offset voltage; (B) adjusting a first input voltage of the residue amplifier according to the offset voltage and a reference digital code; (C) converting an output voltage of the residue amplifier into a second digital code; (D) performing a correlation operation on the reference digital code and the second digital code to generate an intermediate gain; (E) recording the intermediate gain; (F) repeating step (A) to step (E) to record a plurality of intermediate gains; (G) selecting one of the intermediate gains as a digital gain according to the second digital code; and (H) generating an output digital code according to a first digital code, the reference digital code, the digital gain, and the second digital code.

A pipelined analog-to-digital converter includes a first stage circuit and a second stage circuit. The first stage circuit performs an analog-to-digital conversion on an analog input voltage to generate a first output signal including M higher bits among (M+N) bits of a digital output code corresponding to the analog input voltage, and generates a residue voltage corresponding to N lower bits among the (M+N) bits of the digital output code wherein M and N are natural numbers. The second stage circuit includes a residue amplifier configured to sequentially amplifying the residue voltage and a comparison voltage to generate an amplified residue voltage and an amplified comparison voltage.

A pipelined SAR ADC that is connected to receive an analog input voltage includes a first ADC stage, a residue amplifier, a second ADC stage, and calibration circuitry coupled and configured to add first and second ADC conversion results to form an uncalibrated digital value, and to apply calibration values to the uncalibrated digital value to obtain a calibrated digital value corresponding to a calibrated digital representation of the analog input voltage, where the calibration values include a first ADC stage DAC element mismatch calibration value corresponding to the first ADC conversion result, an offset calibration value, and a gain adjustment factor.

The invention discloses a GmC dynamic amplifier with high linearity, high temperature and power supply voltage stability, and relates to an integrated circuit technology. The amplifier comprises an amplifier main body part and a bias part for providing voltage bias for the main body part. Wherein the main body part of the amplifier adopts two differential pairs with asymmetric transistor width-to-length ratios, so that the linearity of transconductance of the amplifier is improved, and the linearity of the amplifier is improved when the input amplitude is relatively large; besides, a constant transconductance bias circuit is adopted in the bias part, transconductance of a transistor of the constant transconductance bias circuit is slightly affected by temperature and power voltage condition changes, and due to the effect of a current mirror, transconductance of a differential pair of the main body part and gain of the main body part also have high temperature and power voltage stability. The linearity of the dynamic GmC amplifier is higher than that of a traditional GmC amplifier, the gain can be kept relatively unchanged within a certain temperature and power supply voltage range, the advantages of low noise and low power consumption of the dynamic GmC amplifier are played, the defects of the dynamic GmC amplifier are overcome, the dynamic GmC amplifier can be used as a residual amplifier of a high-speed high-precision low-power-consumption assembly line SAR ADC, and the dynamic GmC amplifier can be used as a high-speed high-precision low-power-consumption assembly line SAR ADC. The method is widely applied to the high-precision and advanced fields such as medical imaging, biological detection, Internet of Things, instruments and meters, industrial process control and the like.

Disclosed are a pipelined successive approximation register analog-to-digital converter, an integrated circuit, and an electronic device. The pipelined successive approximation register analog-to-digital converter includes: a first-stage successive approximation register analog-to-digital converter (10), a residue amplifier (30), a second-stage successive approximation register analog-to-digital converter (20), and a digital coding unit (40).

The present invention discloses a high-speed and high-linearity residue amplifier and an analog-to-digital converter, belonging to the technical field of integrated circuits, and solving the technical problem that the existing source follower cannot meet the indexes of high speed and high linearity. The residue amplifier includes a bias and output module, an inverter, and a linear transconductance unit based on a class-AB super source follower structure, and the bias and output module, the linear transconductance unit, and the inverter are connected in sequence. The linear transconductance unit of the present invention can generate a transconductance with high linearity, thereby improving the linearity of the entire residue amplifier, and can ensure the symmetry of the positive and negative output terminals of the residue amplifier under the condition of high frequency or large swing input, so as to effectively meet the indexes of high speed and high linearity. In addition, the present invention also introduces a gain calibration module that resists temperature and process variations, which can automatically compensate for the influence brought by the subsequent system environment temperature change.

The invention relates to an analog-to-digital converter with an auto-zero residual amplification circuit. Examples of an analog-to-digital converter (ADC) are disclosed herein to enable automatic zeroing to be performed by amplifying a signal to improve a signal-to-noise ratio. The ADC may generate a first digital code representing an analog input signal and a second digital code based on a residue from the first digital code, and may combine the first digital code and the second digital code to generate a digital output code representing the analog input signal. The ADC may generate the second digital code using a first observed value and a second observed value representing an analog residual value of the residual.

A pipelined SAR ADC that is connected to receive an analog input voltage includes a first ADC stage, a residue amplifier, a second ADC stage, and calibration circuitry coupled and configured to add first and second ADC conversion results to form an uncalibrated digital value, and to apply calibration values to the uncalibrated digital value to obtain a calibrated digital value corresponding to a calibrated digital representation of the analog input voltage, where the calibration values include a first ADC stage DAC element mismatch calibration value corresponding to the first ADC conversion result, an offset calibration value, and a gain adjustment factor.

The present invention discloses a successive approximation - pipelined hybrid analog - to - digital converter and a timing control method. The successive approximation - pipelined hybrid analog - to - digital converter includes a first - stage analog - to - digital converter, a residue amplifier, a second - stage analog - to - digital converter, and a timing circuit module; the timing circuit module is configured to sequentially obtain a sampling clock signal and a first flag signal indicating that the first - stage analog - to - digital converter has completed quantization from the timing output terminal of the first - stage analog - to - digital converter, obtain a second flag signal indicating that the second - stage analog - to - digital converter has completed quantization from the timing output terminal of the second - stage analog - to - digital converter, generate an amplification clock signal according to the sampling clock signal, the first flag signal, and the second flag signal, and output the amplification clock signal to the timing control terminal of the residue amplifier; the residue amplifier is configured to perform residue amplification according to the amplification clock signal. The present invention realizes reducing the bit error rate of the successive approximation - pipelined hybrid analog - to - digital converter while improving the linearity.